CN100492907C - Master-slave type falling edge D trigger adopting sensitive amplifier structure - Google Patents

Abstract

Sensitive amplifier composed of two inverters connected to each other end to end constitutes first stage of the trigger. Two connected points form SALATCH_P and SALATCH_N nodes respectively. Two buffered inverters, two CMOS transfer gate, potential hold circuit, and output inverter connected to each other constitutes second stage. The said SALATCH_P and SALATCH_N are connected to input ends of the said buffered inverters respectively. The invention features simple structure, small area of circuit, low power consumption, and good characteristics of circuit time delay, setup time and metastable state time.

Description

Adopt the master-slave type trailing edge d type flip flop of sensitive amplifier structure

Technical field

Direct applied technical field is to adopt the trailing edge low-power consumption flip-flop circuit design of sensitive amplifier structure " to adopt the master-slave type trailing edge d type flip flop of sensitive amplifier structure ".The circuit that proposes is that a class is applicable to low amplitude of oscillation clock signal networks technology and the static CMOS flip-flop circuit of low-power consumption unit that need trailing edge to trigger.

Background technology

Along with the progress of CMOS integrated circuit fabrication process, the scale and the complexity of integrated circuit increase day by day, and power consumption of integrated circuit and heat dissipation problem more and more obtain the attention from industrial quarters and academia.Based on present integrated circuit (IC) design style, in the large scale digital Circuits System, the ratio that the energy of clock network consumption accounts for the total power consumption of entire circuit remains high always; Wherein, under the circuit working state, (trigger: energy Flip-Flop) becomes the important source of clock network energy consumption again in clock interconnection gauze and sequence circuit unit in consumption, and the power consumption ratio of the two has ever-increasing trend (to see document David E.Duarte, N.Vijaykrishnan, andMary Jane Irwin. " A Clock Power Model to Evaluate Impact of Architectural andTechnology Optimizations " .IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vo1.10, no.6, pp.844-855, December 2002.).

In the design of large scale integrated circuit, use the trigger that the clock trailing edge triggers simultaneously, this class trigger is commonly used to optimize circuit sequence, improves pipeline organization.Along with improving constantly that the design performance to large scale integrated circuit requires, the utilization of trailing edge trigger is more and more many, and its power consumption and delay performance receive publicity further in integrated circuit fields.

CMOS power consumption of integrated circuit source mainly contains dynamic power consumption, quiescent dissipation, short circuit current power consumption and leakage current power consumption.Wherein dynamic power consumption accounts for major part.Under certain circuit performance constraint, the dynamic power consumption P of CMOS integrated circuit node _DynamicIt is this node load capacitor C _L, supply voltage V _DDVoltage swing V with this node _SwingFunction, that is:

P _Dynamic＝C _LV _DDV _Swingfα (1)

Wherein, f is the operating frequency of circuit, and α is the signal activity.From formula (1), as seen, reduce α, C _L, V _DDAnd V _SwingAll can reduce the dynamic power consumption of circuit.Be different from the data-signal gauze, the clock cable netting gear has the characteristics of big interconnection line parasitic capacitance and high signal activity, by reducing the voltage signal amplitude of oscillation V of clock signal gauze _SwingCan be at the energy that guarantees to reduce under the condition of circuit performance to consume on the clock interconnection line.The flip-flop circuit unit is widely used in integrated circuit (IC) design, wherein also is no lack of the use of trailing edge flip-flop circuit.Be trailing edge flip-flop circuit cell schematics as shown in Figure 1.Be illustrated in figure 2 as the traditional trailing edge flip-flop circuit unit basic circuit structure that is widely used in the design of digital circuit standard cell lib.Here with complementary output in the Verisilicon0.15 μ m technology digital standard cell library, the flip-flop circuit unit F FDNHD1X that rising edge triggers is that the example explanation (is seen document " SPICE Model of 0.15um Generic (1.5V/3.3V) 1P7MProcess " Document number:GSMC_L015S7G0_SPI_V1.3 ﹠amp; " VeriSilicon GSMC0.15 μ m High-Density Standard Cell Library Databook ").The main feature of sort circuit structure is that circuit structure is fairly simple, only need connected mode exchange with cn end with the c end of tristate inverter, just can trigger and become the trailing edge triggering from rising edge, its shortcoming is that the load of clocked inverter is bigger, power consumption is big, is not suitable for the design of low-clock signal excursion clock network system.H.Kawaguchi propose a kind of flip-flop circuit RCSFF that can adopt low-voltage amplitude of oscillation clock signal to drive (see document H.Kawaguchi and T.Sakurai: " A Reduced Clock-Swing Flip-Flop (RCSFF) for 63% Power Reduction " ', IEEEJOURNAL OF SOLID-STATE CIRCUITS, VOL.33, NO.5, MAY1998, PP.807-811.), on this basis, the flip-flop circuit SAFF_CP that Y.Zhang proposes a kind of low-voltage amplitude of oscillation clock signal driving of condition presetting construction (sees document Y.Zhang, H.Yang, and H.Wang, " Low clock-swingconditional-precharge flip-flop for more than 30% power reduction; " Electron.Lett., vol.36, no.9, pp.785-786, Apr.2000.) as shown in Figure 3.But they only relate to the situation that rising edge triggers, and do not mention the design of low-power consumption trailing edge trigger.And this class trigger structure itself is only used the clock of a single-phase, does not have clocked inverter, and the mode that can not use traditional exchange clk and ckn (clk's is anti-phase) realizes the trailing edge trigger.If we add an inverter to clock simply, use SAFF_CP again, this inverter is always in somersault, wasteful energy, and worsened time-delay, can't adapt to the requirement of low-power consumption.If we seek the trigger that a kind of condition is put formula in advance, circuit structure and SAFF_CP antithesis, because it is the P pipe with respect to the more weak charging ability of N pipe, makes circuit time delay very big, infeasible in practice so.The design of low-power consumption trailing edge trigger exists blank to a certain extent.

G.M.Blare mentions that a kind of high-speed-differential is bilateral (sees document G.M.Blare along triggered flip-flop, " Comments on ' New Single-Clock COMS Latchs and Flip-Flops with ImprovedSpeed and Power Savings '; " IEEE J.Solid-StateCircuits, Vol.32, NO.10, pp.1610-1611, Oct.1997.), as shown in Figure 4.It is still rising edge triggering in essence, and the design of its trailing edge triggering part mainly is to have utilized clocked inverter.But the enlightening meaning of its partial circuit structure.

Summary of the invention

The objective of the invention is in order to adapt to the low-power consumption requirement, propose a kind of master-slave type trailing edge trigger structure that adopts sensitive amplifier structure.Its circuit structure is simple, and two complementary output end signals upset time-delay is symmetry comparatively, and delay performance improves significantly, and compares traditional digital standard unit and can save power consumption more than 20%, as shown in Figure 5.

The invention is characterized in:

1, adopt the master-slave type trailing edge d type flip flop of sensitive amplifier structure, it is characterized in that described d type flip flop is a kind of master-slave type static flip-flop, and the overall structure symmetry, two complementary output end signal upset time-delay symmetries, described d type flip flop contains:

Sensitive amplifying stage comprises:

The 15th inverter and the 16th inverter, the output of the 16th inverter links to each other with the input of the 15th inverter, constitutes the 1st intermediate node; The input of the 16th inverter links to each other with the output of the 15th inverter, constitutes the 2nd intermediate node;

The 1NMOS pipe, the source electrode of 1NMOS pipe links to each other with described the 2nd intermediate node; The grid of 1NMOS pipe connects the 3rd intermediate data signal; The substrate ground connection of 1NMOS pipe;

The 2NMOS pipe, the source electrode of 2NMOS pipe links to each other with described the 1st intermediate node; The substrate ground connection of 2NMOS pipe; The grid of 2NMOS pipe connects the 4th input data signal; The 4th input data signal and described the 3rd intermediate data signal inversion;

3NMOS pipe, the source electrode of 3NMOS pipe link to each other with the drain electrode of 2NMOS pipe with described 1NMOS pipe simultaneously; The grid of 3NMOS pipe connects the inversion signal of the 5th clock signal, i.e. the 6th input signal; The substrate of 3NMOS pipe and the back ground connection that links to each other that drains;

The 1st inverter, input termination the 4th input data signal of the 1st inverter, output is the 3rd intermediate data signal, receives the grid of described 1NMOS pipe;

The trigger output stage, contain:

The 4th inverter, the input of the 4th inverter links to each other with described the 2nd intermediate node;

The 5th inverter, the input of the 5th inverter links to each other with described the 1st intermediate node;

The 1CMOS transmission gate is managed both and is connect by the PMOS of the NMOS of a substrate ground connection pipe and a substrate biasing and forms, and the source electrode of described two pipes links to each other and then links to each other with the output of described the 4th inverter;

The 2CMOS transmission gate is managed both and is connect by the PMOS of the NMOS of a substrate ground connection pipe and a substrate biasing and forms, and the source electrode of described two pipes links to each other and then links to each other with the output of described the 5th inverter;

The 0th inverter, the 6th input signal CKN insert the grid of PMOS pipe in the input of described the 0th inverter and described the 1st, the 2 two cmos transmission gate simultaneously; The output of described the 0th inverter links to each other with the grid of NMOS pipe in described the 1st, the 2 two cmos transmission gate simultaneously;

The current potential retainer, contain two end to end each other inverters, i.e. the 6th inverter and the 7th inverter, wherein, the output of the input of described the 6th inverter and the 7th inverter links to each other, and NMOS pipe links to each other with the drain electrode of PMOS pipe in back and the described 1COMS transmission gate, forms the 7th intermediate node; The input of the output of described the 6th inverter and the 7th inverter links to each other, and NMOS pipe links to each other with the drain electrode of PMOS pipe in back and the described 2COMS transmission gate, forms the 8th intermediate node;

The 2nd inverter, the input of this inverter links to each other with described the 7th intermediate node, and output produces the 1st output signal of described trailing edge d type flip flop;

The 3rd inverter, the input of this inverter links to each other with described the 8th intermediate node, and output produces the 2nd output signal of described trailing edge d type flip flop.

2, the master-slave type trailing edge d type flip flop of employing sensitive amplifier structure according to claim 1 is characterized in that: described d type flip flop is a kind of master-slave type trailing edge d type flip flop with set function, also contains:

The 4th NMOS pipe, the source electrode of 4NMOS pipe links to each other with the drain electrode of 2NMOS with described 1NMOS pipe; The drain electrode of 4NMOS pipe links to each other with the source electrode of described 3NMOS pipe; The substrate ground connection of 4NMOS pipe;

The 10th inverter, the input of this inverter and the grid of described 4NMOS pipe are connected asserts signal after linking to each other;

The 5th NMOS pipe, the grid of 5NMOS pipe connects the output of described the 10th inverter; The source electrode of 5NMOS pipe connects described the 1st intermediate node; Ground connection after the drain electrode of 5NMOS pipe links to each other with substrate;

The 6th NMOS pipe, the source electrode of 6NMOS pipe connects described the 7th intermediate node; Ground connection after the drain electrode of 6NMOS pipe links to each other with substrate, and grid connects the inversion signal of asserts signal.

3, the master-slave type trailing edge d type flip flop of employing sensitive amplifier structure according to claim 1 is characterized in that: described d type flip flop is a kind of master-slave type trailing edge d type flip flop with reset function, also contains:

The 4th NMOS pipe, the source electrode of 4NMOS links to each other with the drain electrode of 2NMOS pipe with described 1NMOS pipe; The drain electrode of 4NMOS pipe links to each other with the source electrode of described 3NMOS pipe; The substrate ground connection of 4NMOS pipe;

The 10th inverter, the input of this inverter and the grid of described 4NMOS pipe are connected reset signal after linking to each other;

The 5th NMOS pipe, the grid of 5NMOS pipe connects the output of described the 10th inverter; The source electrode of 5NMOS pipe connects described the 2nd intermediate node; Ground connection after the drain electrode of 5NMOS pipe links to each other with substrate;

The 6th NMOS pipe, the source electrode of 6NMOS pipe connects described the 8th intermediate node; Ground connection after the drain electrode of 6NMOS pipe links to each other with substrate, and grid connects the inversion signal of reset signal.

4, the master-slave type trailing edge d type flip flop of employing sensitive amplifier structure according to claim 1 is characterized in that: described d type flip flop is a kind of master-slave type trailing edge d type flip flop with set and reset function, also contains:

Block the 41NMOS pipe that input channel is used during set, the source electrode of 41NMOS pipe links to each other with the drain electrode of described 1NMOS pipe; The drain electrode of 41NMOS pipe connects the source electrode of described 3NMOS pipe;

Block the 42NMOS pipe that input channel is used when resetting, the source electrode of 42NMOS pipe links to each other with the drain electrode of described 2NMOS pipe; The drain electrode of 42NMOS pipe connects the source electrode of described 3NMOS pipe; Ground connection after the substrate of 42NMOS pipe links to each other with the substrate of described 41NMOS pipe;

The 10th inverter, the input of this inverter and the grid of described 41NMOS pipe are connected asserts signal after linking to each other; The inversion signal of this inverter output asserts signal;

The 1st NOR gate, input of this NOR gate with connect reset signal after the grid of described 42NMOS pipe links to each other, and the inversion signal of another input termination asserts signal;

The 52NMOS pipe of reset signal control, the grid of 52NMOS pipe connect the middle inverted reset control signal of output of described the 1st NOR gate; The source electrode of 52NMOS connects described the 2nd intermediate node, and the drain electrode ground connection afterwards that links to each other with substrate;

The 62NMOS pipe of reset signal control, the source electrode of 62NMOS pipe connects described the 8th intermediate node; Inverted reset control signal in the middle of the grid of 62NMOS pipe connects, and the drain electrode ground connection afterwards that links to each other with substrate;

The 51PMOS pipe of asserts signal control, the grid of 51PMOS pipe connects asserts signal; The source electrode of 51PMOS connects described the 2nd intermediate node, and drain electrode with connect power supply after substrate links to each other;

The 61PMOS pipe of asserts signal control, the grid of 61PMOS pipe connects asserts signal; The source electrode of 61PMOS connects described the 8th intermediate node, and drain electrode with connect power supply after substrate links to each other.

The invention has the beneficial effects as follows: with traditional digital standard unit triggers device circuit FFDNHD1X relatively, the FFDNHD1X_SCB_FCS trigger that the present invention proposes can be saved and is higher than 20% power consumption under identical test condition.And the structure of circuit obtains simplifying, and circuit area is less, the circuit delay characteristic, and settling time and metastable state time response are improved obviously.The circuit engineering that is proposed is suitable as the digital circuit standard cell and is applied in the low power consumption integrated circuit design very much.

Description of drawings

Fig. 1. trailing edge flip-flop circuit cell schematics, D is the data-signal input, CKN is a clock signal input terminal, Q and Q _bBe the complementary signal output;

The flip-flop circuit unit F FDNHD1X circuit structure diagram that complementary output and trailing edge trigger in Fig. 2 .Verisilicon 0.15 μ m technology digital standard cell library;

Fig. 3 .SAFF_CP flip-flop circuit structure chart;

Fig. 4. the bilateral circuit structure diagram of a kind of high-speed-differential along triggered flip-flop;

Fig. 5. the trailing edge trigger FFDNHD1X_SCB_FCS circuit structure diagram of sensitive amplifier structure of the present invention.

Fig. 6. the trailing edge flip-flop circuit structure chart of another kind of sensitive amplifier structure.

Fig. 7. a kind of trailing edge flip-flop circuit structure chart of modified model sensitive amplifier structure.

Fig. 8. the FFDNSHD1X_SCB_FCS flip-flop circuit structure chart of band asynchronous set end.

Fig. 9. the FFDNRHD1X_SCB_FCS flip-flop circuit structure chart of band asynchronous reset end.

Figure 10. the FFDNSRHD1X_SCB_FCS flip-flop circuit structure chart of band asynchronous set, reset terminal.

Embodiment

The technical scheme that the present invention solves its technical problem is: the master-slave type trailing edge trigger FFDNHD1X_SCB_FCS of the employing sensitive amplifier structure that the present invention proposes, as shown in Figure 5.The core texture of first order circuit is by two end to end sensitive amplifier structures that constitute of inverter.There is positive feedback in this structure, can acceleration mode stable, its bistable characteristic is convenient to preserve data again.The D signal is controlled SALATCH_P respectively with the difference input structure, and two drop-down discharge loops of SALATCH_N reach complementary input.Control discharge loop in the lump by ckn driving N pipe again.Do so at first and come drive circuit with the N tube discharge, circuit working speed is fast, secondly is that domain is symmetry comparatively with the difference input, and rising time delay, decline time delay are more or less the same.Second level circuit adopts buffer inverter successively, transmission gate, current potential holding unit (holder), output stage.In order to improve circuit working speed, the present invention has adopted complete symmetrical structure, though angle from pure logic function, perhaps buffer inverter XIVG5 and transmission gate XOUT2 are unnecessary among Fig. 5, but they have been arranged, partial node QI, QNI just are not only simple filling electric current or draw electric current, but when one of them node irritated electric current, another node is drawn electric current.Above-mentioned design has obviously reduced the time delay of circuit, makes comparatively symmetry of time-delay of circuit output end rising edge and trailing edge time-delay simultaneously.And like this after the design, task to the driving of circuit second level node is mainly born by two buffer inverter, the pipe sizing of current potential holding unit (holder) can be done very for a short time, has also just reduced the electric capacity of node QI, QNI, thereby has improved circuit working speed.Wherein, current potential holding unit (holder) has not only been eliminated the ternary effect of transmission gate output, but also has become a speed-raising unit to a certain extent.

First order discharge loop is blocked when ckn is low level, and D and DB signal input branch road are blocked, QI, QNI, SALATCH_P, and the SALATCH_N node potential is kept under the effect of current potential holding unit (holder).Next interim when the ckn rising edge, first order discharge loop is opened, SALATCH_P, and the SALATCH_N current potential overturns with the upset of input D and DB signal.Note transmission gate XOUT1 this moment, XOUT2 blocks, so two buffer XIVG4, XIVG5 are close to zero load.The second level keeps original state under the effect of HOLDER simultaneously.When the clock trailing edge arrived, D and DB input path were cut off, and the first order keeps original state constant, and transmission gate is opened, and drives the second level and changes to new state output.Certainly, if we strengthen the size of the first order, do not want these two buffer XIVG4, XIVG5, and allow sense amplifier directly drive the back level, this logically is feasible, but this two buffers have been arranged, isolate the two-stage node capacitor well, helped reducing the sense amplifier size, avoided small tubes to drive heavy load, make circuit performance more stable, whole time-delay is reduced.Though this circuit does not have preliminary filling, let slip journey in advance, as long as the D state is constant, circuit is not with the unnecessary upset of ckn, the circuit internal capacitance is all very little again, so the very big power consumption that reduced! Even a clocked inverter has been used in the second level, but its load is very light, and comparatively speaking, power consumption can be accepted.

Circuit shown in Figure 6 is the blank of Fig. 5.Its basic principle is identical with FFDNHD1X_SCB_FCS.Difference is: in the circuit shown in Figure 6, D and DB signal are that the P pipe of controlling by two ckn simply is added to node SALATCH_P, SALATCH_N's, do also simpler and easyly like this, in first order circuit when upset, is on one side D and DB draw electric current, irritate electric current on one side, speed is also very fast.But power consumption increases much on the sort circuit D signal pins, and is relatively more responsive to inner node capacitor, is difficult for regulating.

Circuit shown in Figure 7 is a kind of distortion and improvement of Fig. 5 circuit.Its basic principle is identical with FFDNHD1X_SCB_FCS, and difference mainly is to have increased by three in the first order to drive the P pipe.By D, DB, CLK control, three N that draw in the circuit connecting mode up and down manage antithesis, the driving tube action compensating that draws in the function up and down to these three pipes respectively.Do the obvious time delay that reduced like this.Weak point is that power consumption increases to some extent, and layout drawing is difficulty relatively.

Essential features of the present invention is: at first, flip-flop circuit adopts sensitive amplifier structure, and D and DB signal are under clock control, by the input of discharge paths symmetry.Secondly buffer inverter, transmission gate, the structure of current potential holding unit (holder): isolate the two-stage node capacitor with buffer inverter are adopted in the second level; Come control timing with transmission gate; Eliminate ternary node with the current potential holding unit, stable potential, raising speed.At last, second level circuit adopts complete symmetrical structure, and the data that the first order is preserved are independently delivered to the second level, has improved second level operating rate like this, and it is relatively more symmetrical also to make the time-delay of data output end rising edge, trailing edge delay time.

For FFDNHD1X_SCB_FCS trigger more proposed by the invention performance characteristics with respect to traditional flip-flop circuit FFDNHD1X, we adopt Versilicon 1.5-V 0.15 μ m technology, use circuit simulation tools HSPICE that two kinds of circuit structures have been carried out the emulation comparative analysis.

Table 1 is depicted as two kinds of flip-flop circuit dynamic power consumption data relatively.Clock signal input CLK is 100MHz in the emulation of circuit dynamic power consumption, 50% duty ratio square-wave signal (0V one 1.5V).Data-signal input D is 20MHz, and 50% duty ratio square-wave signal (0V-1.5V).Input signal change-over time is 0.104ns.Flip-flop circuit output termination 20fF capacitive load.Q Loaded wherein, Qb Empty represent Q output termination 20fF capacitive load, its complementary output end Qb zero load (promptly not connecing load).Qb Loaded, Q Empty represent Qb output termination 20fF capacitive load, and the zero load of Q output.The dynamic power consumption data unit is microwatt (μ w).

Table 1 trigger dynamic power consumption relatively

	Q Loaded， Qb Empty(μw)	Qb Loaded，Q Empty(μW)
			FFDNHD1X	5.816	5.851
FFDNHD1X_SCB_FCS	4.614	4.608
			Save the power consumption ratio	20.7％	21.2％

Table 2 is depicted as the comparison of two kinds of flip-flop circuit delay performances.The definition mode of delay performance is as follows: when the upset of input data D signal during far away in advance in the hopping edge of clk, clk is not subjected to the influence of metastable state effect to the time-delay of output Q, this time-delay is called static time delay, and 105% of static time delay is defined as time-delay (Delay).When clk when the time-delay of output Q equals Delay (be static time delay 105%), the upset of input data D signal is with respect to being defined as pre-set time of the hopping edge of clk the metastable state cycle (Tmp); Metastable state cycle and this moment time-delay and be defined as total time-delay (being Total Delay=Tmp+Delay).

Two kinds of flip-flop circuits adopt identical circuit arrangement, and input signal change-over time is 0.05ns, and complementary output end Q and Qb load are 0.02pF.RISE and FALL represent output signal rising edge and output signal trailing edge respectively; Tmp, Delay and Total Delay are the data targets of Q output under above-mentioned definition.Delay data unit is nanosecond (ns).

Table 2 trigger Total Delay relatively

Table 3 is that two kinds of structure trigger chip areas compare.Wherein in the rule of layout design, its width is fixed, and length is necessary for the integral multiple of 0.56 μ m.The unit of length is a micron (μ m).The unit of area is square micron (μ m ²).

Table 3 trigger chip area relatively

	Width (μ m)	Length (μ m)	Area (μ m 2)
				FFDNHD1X	4.32	9.52	9.52*4.32
FFDNHD1X_SCB_FCS	4.32	10.08	10.08*4.32

By above-mentioned data more as can be seen, structure of testing trigger of the present invention is compared with the corresponding construction of traditional digital standard unit, bigger advantage is arranged on power consumption, and the performance of total time-delay also has greatly improved simultaneously, and Total Delay and chip area are suitable substantially.Advantage with these performances makes it be well suited for being applied in the low power consumption digital large scale integrated circuit.

In this structural series, consider the setting of expanded function end, following several trigger is then arranged.

1.FFDNSHD1X_SCB_FCS be this serial trailing edge d type flip flop that only has set function, as shown in Figure 8.Its basic principle is consistent with FFDNHD1X_SCB_FCS.In the realization of set function, by managing (M4) at first order discharge loop string one N, guarantee when set, to block input channel, utilize circuit positive feedback characteristic then, only need at first order node SALATCH_N, the drop-down N pipe (M5, M6) that connects an asserts signal S control on the node QI of the second level respectively is just passable.Has the unit F FDNSHD1X comparative result of identical function shown in table 11, table 12 and table 13 in the power consumption of its circuit, time-delay and area performance and the Verisilicon 1.5-V 0.15 μ m technology digital standard cell library.Test condition is the 1.5V DC level for the SN input signal, and other conditions are identical with the test condition of FFDNHD1X_SCB_FCS.

Table 11 trigger dynamic power consumption relatively

	Q Loaded， Qb Empty(μw)	Qb Loaded，Q Empty(μW)
			FFDNSHD1X	6.173	6.209
FFDNSHD1X_SCB_FCS	4.899	4.900
			Save the power consumption ratio	20.6％	21.1％

Table 12 trigger Total Delay relatively

Table 13 trigger chip area relatively

	Width (μ m)	Length (μ m)	Area (μ m 2)
				FFDNSHD1X	4.32	10.64	10.64*4.32
FFDNSHD1X_SCB_FCS	4.32	11.76	11.76*4.32

2.FFDNRHD1X_SCB_FCS be this serial trailing edge d type flip flop that only has reset function, as shown in Figure 9.Its basic principle is consistent with FFDNHD1X_SCB_FCS.On Implementation for Reset Function, by managing (M4) at first order discharge loop string one N, guarantee when resetting, to block input channel, utilize circuit positive feedback characteristic then, only need at first order node SALATCH_P, the drop-down N pipe (M5, M6) that connects a reset signal R control on the node QNI of the second level respectively is just passable.Has the unit F FDNRHD1X comparative result of identical function shown in table 21, table 22 and table 23 in the power consumption of its circuit, time-delay and area performance and the Verisilicon1.5-V0.15 μ m technology digital standard cell library.Test condition is the 1.5V DC level for the RN input signal, and other conditions are identical with the test condition of FFDNHD1X_SCB_FCS.

Table 21 trigger dynamic power consumption relatively

	Q Loaded， Qb Empty(μw)	Qb Loaded，Q Empty(μW)
			FFDNRHD1X	6.701	6.695
FFDNRHD1X_SCB_FCS	4.659	4.664
			Save the power consumption ratio	30.5％	30.3％

Table 22 trigger Total Delay relatively

Table 23 trigger chip area relatively

	Width (μ m)	Length (μ m)	Area (μ m 2)
				FFDNRHD1X	4.32	12.32	12.32*4.32
FFDNRHD1X_SCB_FCS	4.32	12.32	12.32*4.32

3.FFDNSRHD1X_SCB_FCS be this serial trailing edge d type flip flop that only has set, reset function, as shown in figure 10.Its basic principle is consistent with FFDNHD1X SCB_FCS.On set, Implementation for Reset Function, by managing (MS4, MR4) at two N of first order discharge loop string, guarantee to block input channel in set, when resetting, utilize circuit positive feedback characteristic then, only need at first order node SALATCH_P, connect respectively on the node QNI of the second level asserts signal SN control on draw P pipe (MS5, MS6) to realize set; At first order node SALATCH_P, the drop-down N pipe (M5, M6) that connects a reset signal R control on the node QNI of the second level is respectively realized resetting.Here why adopt that drop-down to realize resetting be that discharge capability is strong, can use the small size pipe because N pipe opening speed is fast: why adopt to draw on the P pipe and realize that set is because layout design is considered easily.Set-reset priority is by RN, and the SN combinational logic determines.Has the unit F FDNSRHD1X comparative result of identical function shown in table 31, table 32 and table 33 in the power consumption of its circuit, time-delay and area performance and the Verisilicon 1.5-V 0.15 μ m technology digital standard cell library.Test condition is that SN, RN input signal are the 1.5V DC level, and other conditions are identical with the test condition of FFDNHD1X_SCB_FCS.

Table 31 trigger dynamic power consumption relatively

	Q Loaded， Qb Empty(μw)	Qb Loaded，Q Empty(μw)
			FFDNSRHD1X	6.438	6.460
FFDNSRHD1X_SCB_FCS	5.162	5.152
			Save the power consumption ratio	20.0％	20.2％

Table 32 trigger Total Delay relatively

Table 33 trigger chip area relatively

	Width (μ m)	Length (μ m)	Area (μ m 2)
				FFDNSRHD1X	4.32	13.44	13.44*4.32
FFDNSRHD1X_SCB_FCS	4.32	15.12	15.12*4.32

Claims (4)

1, adopt the master-slave type trailing edge d type flip flop of sensitive amplifier structure, it is characterized in that described d type flip flop is a kind of master-slave type static flip-flop, and the overall structure symmetry, two complementary output end signal upset time-delay symmetries, described d type flip flop contains:

Sensitive amplifying stage comprises:

The 15th inverter and the 16th inverter, the output of the 16th inverter links to each other with the input of the 15th inverter, constitutes the 1st intermediate node; The input of the 16th inverter links to each other with the output of the 15th inverter, constitutes the 2nd intermediate node;

The 1st NMOS pipe, the source electrode of 1NMOS pipe links to each other with described the 2nd intermediate node; The grid of 1NMOS pipe connects the 3rd intermediate data signal; The substrate ground connection of 1NMOS pipe;

The 2nd NMOS pipe, the source electrode of 2NMOS pipe links to each other with described the 1st intermediate node; The substrate ground connection of 2NMOS pipe; The grid of 2NMOS pipe connects the 4th input data signal; The 4th input data signal and described the 3rd intermediate data signal inversion;

The 3rd NMOS pipe, the source electrode of 3NMOS pipe link to each other with the drain electrode of 2NMOS pipe with described 1NMOS pipe simultaneously; The grid of 3NMOS pipe connects the inversion signal of the 5th clock signal, i.e. the 6th input signal; The substrate of 3NMOS pipe and the back ground connection that links to each other that drains;

The 1st inverter, input termination the 4th input data signal of the 1st inverter, output is the 3rd intermediate data signal, receives the grid of described 1NMOS pipe;

The trigger output stage, contain:

The 4th inverter, the input of the 4th inverter links to each other with described the 2nd intermediate node;

The 5th inverter, the input of the 5th inverter links to each other with described the 1st intermediate node;

The 1st cmos transmission gate is managed both and is connect by the PMOS of the NMOS of a substrate ground connection pipe and a substrate biasing and forms, and the source electrode of described two pipes links to each other and then links to each other with the output of described the 4th inverter;

The 2nd cmos transmission gate is managed both and is connect by the PMOS of the NMOS of a substrate ground connection pipe and a substrate biasing and forms, and the source electrode of described two pipes links to each other and then links to each other with the output of described the 5th inverter;

The 0th inverter, the 6th input signal CKN insert the grid of PMOS pipe in the input of described the 0th inverter and described the 1st, the 2 two cmos transmission gate simultaneously; The output of described the 0th inverter links to each other with the grid of NMOS pipe in described the 1st, the 2 two cmos transmission gate simultaneously;

The current potential retainer, contain two end to end each other inverters, i.e. the 6th inverter and the 7th inverter, wherein, the output of the input of described the 6th inverter and the 7th inverter links to each other, and NMOS pipe links to each other with the drain electrode of PMOS pipe in back and the described 1COMS transmission gate, forms the 7th intermediate node; The input of the output of described the 6th inverter and the 7th inverter links to each other, and NMOS pipe links to each other with the drain electrode of PMOS pipe in back and described the 2nd COMS transmission gate, forms the 8th intermediate node;

The 2nd inverter, the input of this inverter links to each other with described the 7th intermediate node, and output produces the 1st output signal of described trailing edge d type flip flop;

The 3rd inverter, the input of this inverter links to each other with described the 8th intermediate node, and output produces the 2nd output signal of described trailing edge d type flip flop.

2, the master-slave type trailing edge d type flip flop of employing sensitive amplifier structure according to claim 1 is characterized in that: described d type flip flop is a kind of master-slave type trailing edge d type flip flop with set function, also contains:

The 4th NMOS pipe, the source electrode of the 4th NMOS pipe links to each other with the drain electrode of the 2nd NMOS with described the 1st NMOS pipe; The drain electrode of the 4th NMOS pipe links to each other with the source electrode of described the 3rd NMOS pipe; The substrate ground connection of the 4th NMOS pipe;

The 10th inverter, the grid of the input of this inverter and described the 4th NMOS pipe is connected asserts signal after linking to each other;

The 5th NMOS pipe, the grid of the 5th NMOS pipe connects the output of described the 10th inverter; The source electrode of the 5th NMOS pipe connects described the 1st intermediate node; Ground connection after the drain electrode of the 5th NMOS pipe links to each other with substrate;

The 6th NMOS pipe, the source electrode of the 6th NMOS pipe connects described the 7th intermediate node; Ground connection after the drain electrode of the 6th NMOS pipe links to each other with substrate, and grid connects the inversion signal of asserts signal.

3, the master-slave type trailing edge d type flip flop of employing sensitive amplifier structure according to claim 1 is characterized in that: described d type flip flop is a kind of master-slave type trailing edge d type flip flop with reset function, also contains:

The 4th NMOS pipe, the source electrode of the 4th NMOS links to each other with the drain electrode of 2NMOS pipe with described 1NMOS pipe; The drain electrode of the 4th NMOS pipe links to each other with the source electrode of described the 3rd NMOS pipe; The substrate ground connection of the 4th NMOS pipe;

The 10th inverter, the input of this inverter and the grid of described 4NMOS pipe are connected reset signal after linking to each other;

The 5th NMOS pipe, the grid of 5NMOS pipe connects the output of described the 10th inverter; The source electrode of 5NMOS pipe connects described the 2nd intermediate node; Ground connection after the drain electrode of 5NMOS pipe links to each other with substrate;

The 6NMOS pipe, the source electrode of 6NMOS pipe connects described the 8th intermediate node; Ground connection after the drain electrode of 6NMOS pipe links to each other with substrate, and grid connects the inversion signal of reset signal.

4, the master-slave type trailing edge d type flip flop of employing sensitive amplifier structure according to claim 1 is characterized in that: described d type flip flop is a kind of master-slave type trailing edge d type flip flop with set and reset function, also contains:

Block the 41NMOS pipe that input channel is used during set, the source electrode of 41NMOS pipe links to each other with the drain electrode of described 1NMOS pipe; The drain electrode of 41NMOS pipe connects the source electrode of described 3NMOS pipe;

Block the 42NMOS pipe that input channel is used when resetting, the source electrode of 42NMOS pipe links to each other with the drain electrode of described 2NMOS pipe; The drain electrode of 42NMOS pipe connects the source electrode of described 3NMOS pipe; Ground connection after the substrate of 42NMOS pipe links to each other with the substrate of described 41NMOS pipe;

The 10th inverter, the input of this inverter and the grid of described 41NMOS pipe are connected asserts signal after linking to each other; The inversion signal of this inverter output asserts signal;

The 1st NOR gate, input of this NOR gate with connect reset signal after the grid of described 42NMOS pipe links to each other, and the inversion signal of another input termination asserts signal;

The 52NMOS pipe of reset signal control, the grid of 52NMOS pipe connect the middle inverted reset control signal of output of described the 1st NOR gate; The source electrode of 52NMOS connects described the 2nd intermediate node, and the drain electrode ground connection afterwards that links to each other with substrate;

The 62NMOS pipe of reset signal control, the source electrode of 62NMOS pipe connects described the 8th intermediate node; Inverted reset control signal in the middle of the grid of 62NMOS pipe connects, and the drain electrode ground connection afterwards that links to each other with substrate;

The 51PMOS pipe of asserts signal control, the grid of 51PMOS pipe connects asserts signal; The source electrode of 51PMOS connects described the 2nd intermediate node, and drain electrode with connect power supply after substrate links to each other;

The 61PMOS pipe of asserts signal control, the grid of 61PMOS pipe connects asserts signal; The source electrode of 61PMOS connects described the 8th intermediate node, and drain electrode with connect power supply after substrate links to each other.

Images