CN109525222B - A single-phase clock double-edge D flip-flop - Google Patents

Abstract

The invention discloses a single-phase clock double-edge D trigger, comprising: the circuit comprises a rising edge trigger circuit 1, a falling edge trigger circuit 2, two inverters and a two-input NAND gate circuit 3. In the Cadence environment, the UMC 28nmCMOS process is adopted to carry out analog simulation on the single-phase clock double-edge D trigger, and a simulation result shows that the circuit can finish correct sampling transmission of data on the rising edge and the falling edge of a clock signal, and has high response speed and low energy consumption delay product. The single-phase clock double-edge D trigger circuit is simple in structure, the number of the transistors is small, the single-phase clock double-edge D trigger is good in performance, and the single-phase clock double-edge D trigger circuit has wide application prospects in a high-speed and low-power-consumption digital processing system.

Description

A Single-Phase Clock Double-Edge D Flip-Flop

technical field

The invention belongs to the field of D flip-flops, in particular to a single-phase clock double-edge D flip-flop.

Background technique

In today's large-scale integrated circuit design field, reducing power consumption and increasing data processing rate are key areas of concern. Flip-flops are widely used in digital integrated circuit systems. Flip-flops can not only control the jump process of circuit work, but also can be used to implement frequency dividers, counters and registers. In digital systems, about 30% to 70% of system power consumption is used to drive clock networks and flip-flops, and the transfer time of flip-flops also limits the rate of data processing. Therefore, in the current high-speed, low-power digital processing system, it is of great significance to seek a low-power, high-speed flip-flop.

Among various flip-flops, D flip-flops are the most commonly used components. D flip-flops can be divided into single-edge triggers (clock rising or falling edge triggers) and double-edge triggers (clock rising and falling edges perform data sampling and transmission respectively). Compared with the single-edge D flip-flop, the double-edge D flip-flop can achieve twice the data processing volume under the condition of the same clock rate, so it can better meet the high-speed and low-power requirements of digital integrated circuit development .

As shown in Figure 3, the traditional falling-edge D flip-flop is composed of an inverter, a CMOS transmission gate, etc., and a total of 16 transistors (the inverters INV1 and INV2, and the CMOS transmission gates TG1 and TG2 are all composed of two CMOS transistors constitute). In Figure 3, CLK represents the clock signal, and CLKB represents the inverse signal of CLK. When the clock CLK is valid (the clock jumps from high level to low level), the circuit can transmit the input data D to the output node Q (Q=D ); when the clock CLK stops (the clock is at a low level), the circuit can still maintain its own logic level at the output node. The main disadvantage of the traditional D flip-flop is that the capacitive load of the clock signal is very large, which will increase the power consumption of the clock network. At the same time, the D flip-flop implemented by the CMOS transmission gate also has the problem of signal reverse conduction, which may affect the subsequent circuit. The state of the first-stage latch causes the register to output incorrect data.

Contents of the invention

The object of the present invention is to provide a single-phase clock double-edge D flip-flop to solve the above problems.

To achieve the above object, the present invention adopts the following technical solutions:

A single-phase clock double-edge D flip-flop, comprising a rising-edge trigger circuit (1), a falling-edge trigger circuit (2), a first inverter INV1, a second inverter INV2, and a two-input NAND gate circuit (3 ); the rising edge trigger circuit (1) is connected to the two-input NAND gate circuit (3), and the falling edge trigger circuit (2) is connected to the two-input NAND gate circuit (3) through the second inverter INV2; the rising edge trigger circuit Circuit (1) is connected to the first inverter INV1.

Further, the rising edge trigger circuit includes a first PMOS transistor PM1, a second PMOS transistor PM2, a first NMOS transistor NM1 and a second NMOS transistor NM2; the source of the first PMOS transistor PM1 is connected to the power supply voltage Vdd, and the gate is connected to the clock The signal CLK is connected, and the drain is connected to the drain of the first NMOS transistor NM1 and the gate of the second NMOS transistor NM2; the source of the second PMOS transistor PM2 is connected to the power supply voltage Vdd, and the gate is connected to the clock signal CLK, The drain is connected to the drain of the second NMOS transistor NM2, the gate of the fifth PMOS transistor PM5, and the gate of the sixth NMOS transistor NM6; the source of the first NMOS transistor NM1 is connected to the ground line Gnd, and the gate It is connected with the output terminal of the first inverter INV1; the source of the second NMOS transistor NM2 is connected with the ground line Gnd.

Further, the falling edge trigger circuit includes a third PMOS transistor PM3, a fourth PMOS transistor PM4, a third NMOS transistor NM3, and a fourth NMOS transistor NM4; the source of the third PMOS transistor PM3 is connected to the power supply voltage Vdd, and the gate is connected to the input The signal D is connected, and the drain is connected to the drain of the third NMOS transistor NM3 and the gate of the fourth PMOS transistor PM4; the source of the fourth PMOS transistor PM4 is connected to the power supply voltage Vdd, and the drain is connected to the fourth NMOS transistor NM4 The drain of the drain is connected to the input end of the second inverter INV2; the gate of the third NMOS transistor NM3 is connected to the clock signal CLK, and the source is connected to the ground line Gnd; the gate of the third NMOS transistor NM4 is connected to the ground line Gnd. The clock signal CLK is connected, and the source is connected to the ground line Gnd.

Further, the two-input NAND gate circuit includes a fifth PMOS transistor PM5, a sixth PMOS transistor PM6, a fifth NMOS transistor NM5, and a sixth NMOS transistor NM6; the source of the fifth PMOS transistor PM5 is connected to the power supply voltage Vdd, and the gate It is connected to the drain of the second PMOS transistor PM2, the drain of the second NMOS transistor NM2, and the gate of the sixth NMOS transistor NM6, and the drain is connected to the drain of the sixth PMOS transistor PM6 and the drain of the sixth NMOS transistor NM6. pole and the output terminal Q are all connected; the source of the sixth PMOS transistor PM6 is connected to the power supply voltage Vdd, and the gate is connected to the gate of the fifth NMOS transistor NM5 and the output terminal of the second inverter INV2; the fifth The source of the NMOS transistor NM5 is connected to the ground line Gnd, and the drain is connected to the source of the sixth NMOS transistor NM6.

Further, the input terminal of the first inverter INV1 is connected to the input signal D, and the output terminal is connected to the gate of the first NMOS transistor NM1; the input terminal of the second inverter INV2 is connected to the drain of the fourth PMOS transistor PM4 and The drains of the fourth NMOS transistor NM4 are connected to each other, and the output terminals are connected to the gate of the fifth NMOS transistor NM5 and the gate of the sixth PMOS transistor PM6.

Compared with the prior art, the present invention has the following technical effects:

Because the edge trigger circuit of the present invention is only composed of four transistors, the propagation delay of the circuit is short and thus has a fast response speed. The formula for calculating the energy consumption delay product is as follows:

EDP＝P _av t _p ²

In the formula, P _av represents the average power consumption of each flip of the output signal. It can be seen from the above formula that the energy consumption delay product EDP is proportional to the square of the circuit propagation delay, and the circuit has a low energy consumption delay product because the propagation delay of the circuit is short.

The single-phase clock double-edge D flip-flop of the invention has a simple circuit structure and fewer transistors, is a double-edge D flip-flop with good performance, and has wide application prospects in high-speed, low-power digital processing systems.

Description of drawings

Fig. 1 is the circuit diagram of single-phase clock double-edge D flip-flop of the present invention;

Fig. 2 is a logic simulation timing diagram of the single-phase clock double-edge D flip-flop of the present invention.

Fig. 3 is a circuit diagram of a traditional falling edge D flip-flop;

Detailed ways

The present invention is further described below in conjunction with accompanying drawing:

1 is a circuit diagram of a single-phase clock double-edge D flip-flop described in an embodiment of the present invention, and the double-edge D flip-flop includes a rising edge trigger circuit 1, a falling edge trigger circuit 2, two inverters and Two-input NAND gate circuit 3.

Referring to FIG. 1 , the rising edge trigger circuit 1 includes: a first PMOS transistor PM1 , a second PMOS transistor PM2 , a first NMOS transistor NM1 and a second NMOS transistor NM2 . in,

The source of the first PMOS transistor PM1 is connected to the power supply voltage Vdd, the gate is connected to the clock signal CLK, and the drain is connected to the drain of the first NMOS transistor NM1 and the gate of the second NMOS transistor NM2; The source of the second PMOS transistor PM2 is connected to the power supply voltage Vdd, the gate is connected to the clock signal CLK, and the drain is connected to the drain of the second NMOS transistor NM2, the gate of the fifth PMOS transistor PM5, and the gate of the sixth NMOS transistor NM6 The source of the first NMOS transistor NM1 is connected to the ground line Gnd, and the gate is connected to the output of the first inverter INV1; the source of the second NMOS transistor NM2 is connected to the ground line Gnd.

Referring to FIG. 1 , the falling edge trigger circuit 2 includes: a third PMOS transistor PM3 , a fourth PMOS transistor PM4 , a third NMOS transistor NM3 and a fourth NMOS transistor NM4 . in,

The source of the third PMOS transistor PM3 is connected to the power supply voltage Vdd, the gate is connected to the input signal D, and the drain is connected to the drain of the third NMOS transistor NM3 and the gate of the fourth PMOS transistor PM4; The source of the four PMOS transistors PM4 is connected to the power supply voltage Vdd, and the drain is connected to the drain of the fourth NMOS transistor NM4 and the input terminal of the second inverter INV2; the gate of the third NMOS transistor NM3 is connected to the clock signal CLK is connected, and the source is connected to the ground line Gnd; the gate of the third NMOS transistor NM4 is connected to the clock signal CLK, and the source is connected to the ground line Gnd.

Referring to FIG. 1, the two-input NAND gate circuit 3 includes: the fifth PMOS transistor PM5, the sixth PMOS transistor

PM6, the fifth NMOS transistor NM5 and the sixth NMOS transistor NM6. in,

The source of the fifth PMOS transistor PM5 is connected to the power supply voltage Vdd, the gate is connected to the drain of the second PMOS transistor PM2, the drain of the second NMOS transistor NM2 and the gate of the sixth NMOS transistor NM6, and the drain is It is connected to the drain of the sixth PMOS transistor PM6, the drain of the sixth NMOS transistor NM6, and the output terminal Q; the source of the sixth PMOS transistor PM6 is connected to the power supply voltage Vdd, and the gate is connected to the fifth NMOS transistor NM5. The gate is connected to the output terminal of the second inverter INV2; the source of the fifth NMOS transistor NM5 is connected to the ground line Gnd, and the drain is connected to the source of the sixth NMOS transistor NM6.

Referring to Fig. 1, the input terminal of the first inverter INV1 is connected to the input signal D, and the output terminal is connected to the gate of the first NMOS transistor NM1; the input terminal of the second inverter INV2 is connected to the gate of the fourth PMOS transistor The drain of PM4 is connected to the drain of the fourth NMOS transistor NM4, and the output terminal is connected to the gate of the fifth NMOS transistor NM5 and the gate of the sixth PMOS transistor PM6.

Next, the operating principle of the single-phase clock double-edge D flip-flop described in the present invention is described as follows:

First analyze the trigger process of the rising edge of the clock, please refer to the rising edge trigger circuit 1 in Figure 1. When the input signal D1 is at a low level and the clock signal CLK is at a low level, the first NMOS transistor NM1 is turned off, and the first PMOS transistor PM1 is turned on, so that the node A is charged to a high level. At this time, the second NMOS transistor NM2 and the second PMOS transistor PM2 are turned on, and by properly setting the sizes of NM2 and PM2, the charging of node B can be made greater than the discharging, so node B will be charged to a high level. When the clock signal CLK transitions from low level to high level, that is, when the rising edge of the clock arrives, the first PMOS transistor PM1 and the second PMOS transistor PM2 will be cut off, and node A remains at the original high level. The second NMOS transistor NM2 is turned on, and the node B will be discharged to a low level "0" through NM2, and at this time, the low level of the input signal D1 is correctly transmitted to the output node B. When the input signal D1 is at a high level and the clock signal CLK is at a low level, the first NMOS transistor NM1 and the first PMOS transistor PM1 are turned on. By setting the sizes of NM1 and PM1 reasonably, the discharge of node A can be made greater than the charge. Therefore, node A will be discharged to a low level "0". At this time, the second NMOS transistor NM2 is turned off, and the second PMOS transistor PM2 is turned on, so the node B will be charged to a high level through PM2. When the clock signal CLK transitions from low level to high level, that is, when the rising edge of the clock arrives, the first PMOS transistor PM1 and the second PMOS transistor PM2 will be cut off, and node A remains at the original low level "0 ”, the second NMOS transistor NM2 is turned off, so the node B remains at the original high level, and at this time the high level of the input signal D1 is correctly transmitted to the output node B. When the clock signal CLK is at a high level, the first PMOS transistor PM1 and the second PMOS transistor PM2 are cut off, and if the input signal D1 transitions from a high level to a low level, the first NMOS transistor NM1 will be cut off, and node A will remain If the original low level is "0", then the second NMOS transistor NM2 will be cut off, and the node B will maintain the original high level. When the clock signal CLK is at a high level, the first PMOS transistor PM1 and the second PMOS transistor PM2 are cut off, and if the input signal D1 changes from a low level to a high level, the first NMOS transistor NM1 will be turned on, and node A will be turned on. After NM1 is discharged to a low level "0", the second NMOS transistor NM2 is turned off, and the node B will maintain the original low level "0". To sum up, the rising edge trigger circuit 1 can correctly realize the rising edge triggering of the clock signal CLK, and transmit the input signal D1 to the output node B correctly. When CLK is at a low level, the output node B is always at a high level, and when CLK is at a high level, the output node B will not be disturbed by changes in the input signal D1.

Then analyze the trigger process of the falling edge of the clock, please refer to the falling edge trigger circuit 2 in FIG. 1 . When the input signal D is at a high level and the clock signal CLK is at a high level, the third NMOS transistor NM3 is turned on, and the third PMOS transistor PM3 is turned off, so the node C is discharged to a low level “0”. At this time, the fourth NMOS transistor NM4 and the fourth PMOS transistor PM4 are turned on. By setting the sizes of NM4 and PM4 reasonably, the discharge of node F can be made greater than the charge, so node F will be discharged to a low level through NM4. 0". When the clock signal CLK transitions from a high level to a low level, that is, when the falling edge of the clock arrives, the third NMOS transistor NM3 and the fourth NMOS transistor NM4 will be cut off, and the node C remains at the original low level "0 ”, the fourth PMOS transistor PM4 is turned on, the node F will be charged to a high level through PM4, and at this time, the high level of the input signal D is correctly transmitted to the output node F. When the input signal D is at low level and the clock signal CLK is at high level, the third NMOS transistor NM3 and the third PMOS transistor PM3 are turned on. By setting the sizes of NM3 and PM3 reasonably, the charging of node C can be made greater than the discharging. Thus node C will be charged to a high level. At this time, the fourth PMOS transistor PM4 is turned off, and the fourth NMOS transistor NM4 is turned on, so the node F will be discharged to a low level “0” through NM4 . When the clock signal CLK transitions from a high level to a low level, that is, when the falling edge of the clock arrives, the third NMOS transistor NM3 and the fourth NMOS transistor NM4 will be turned off, and the node C remains at the original high level. The fourth PMOS transistor PM4 is turned off, so the node F remains at the original low level “0”, and the low level of the input signal D is correctly transmitted to the output node F at this time. When the clock signal CLK is at low level, the third NMOS transistor NM3 and the fourth NMOS transistor NM4 are cut off, and if the input signal D changes from high level to low level, the third PMOS transistor PM3 will be turned on, and node C will be turned on. After PM3 is charged to a high level, the fourth PMOS transistor PM4 is turned off, and the node F will maintain the original high level. When the clock signal CLK is at low level, the third NMOS transistor NM3 and the fourth NMOS transistor NM4 are cut off, if the input signal D changes from low level to high level, the third PMOS transistor PM3 will be cut off, and node C will remain The original high level, then the fourth PMOS transistor PM4 is cut off, and the node F will maintain the original low level "0". To sum up, the falling edge trigger circuit 2 can correctly realize the falling edge triggering of the clock signal CLK, and transmit the input signal D to the output node F correctly. When CLK is at a high level, the output node F is always at a low level "0", and when CLK is at a low level, the output node F will not be disturbed by the change of the input signal D.

The analysis of the above two circuit characteristics shows that when the rising edge trigger circuit 1 is at the high level of the clock pulse CLK, the level of the output node B depends on the input signal at the required setup time before the rising edge of the clock pulse CLK The value of D1, the output node B will be charged to a high level or discharged to a low level "0", during the low level of the clock pulse CLK, the output node B has a path connected to the power supply voltage Vdd, and will be charged to a high level level. When the falling edge trigger circuit 2 is at the low level of the clock pulse CLK, the level of the output node F depends on the value of the input signal D at the required setup time before the falling edge of the clock pulse CLK, and the output node F will be charged When the clock pulse CLK is at a high level, the output node F has a path connected to the ground line Gnd and will be discharged to a low level “0”. Therefore, the two circuits are functionally complementary, and the output node F(B) has a path connected to the ground line Gnd (power supply voltage Vdd) while the clock pulse CLK is at the high level (low level).

Using the characteristics of the above two circuits, when the rising edge of the clock signal CLK arrives, the output of the falling edge trigger circuit 2 is always 0 when the CLK is high, so that the structure of the rising edge trigger circuit 1 can be used as a signal output; When the falling edge of the clock signal CLK arrives, the output of the rising edge trigger circuit 1 is always 1 when the CLK is low, so that the structure of the falling edge trigger circuit 2 can be used as a signal output to complete the function of the double edge trigger. The double-edge D flip-flop circuit structure is shown in Figure 1, and the combined output structure is a two-input NAND gate circuit 3 . When the clock pulse CLK transitions from a low level to a high level, the rising edge trigger circuit 1 realizes data sampling transmission, and the circuit node F is pre-discharged to a low level "0", and the second inverter INV2 makes the node E is a high level, so that the output value Q of the NAND gate circuit 3 depends on the value of the node B. When the clock pulse CLK transitions from a high level to a low level, the falling edge trigger circuit 2 realizes data sampling transmission, and the circuit node B is precharged to a high level, so that the output value Q of the NAND gate circuit 3 depends on the node F value. Finally, to make the output data have the same polarity as the input data, two inverters INV1 and INV2 are inserted in the circuit.

In summary, the single-phase clock double-edge D flip-flop of the present invention is controlled by a combination of a rising-edge D flip-flop circuit, a falling-edge trigger circuit, two inverters, and two-input NAND gate circuits. The edge and the falling edge can complete the correct sampling transmission of the input data at the output terminal respectively. During the stable period of the clock level, the output node will not be disturbed by the state change of the input signal, and a double-edge D flip-flop controlled by a single-phase clock is realized.

The single-phase clock double-edge D flip-flop of the present invention is realized by using UMC 28nm CMOS technology. In the Cadence environment, the double-edge D flip-flop is simulated and verified, the ambient temperature is 27°C, the process angle is TT, and the power supply voltage is 1.05V.

Please refer to FIG. 3. FIG. 3 is a logic simulation timing diagram of a single-phase clock double-edge D flip-flop described in an embodiment of the present invention, wherein CLK is a clock signal, D is an input signal, and B is an output signal of node B. E is the output signal of node E, and Q is the final output signal of the double-edge D flip-flop. From the simulation results, it can be seen that the output state of node B jumps on the rising edge of the clock signal, and the output state of node F jumps on the falling edge of the clock signal, and finally

The state of the output signal Q transitions on both rising and falling edges. During the stable period of the clock signal level, the output signal Q will not be disturbed by the state change of the input signal, and the logic function of the entire flip-flop is correct, which is a single-phase clock double-edge D flip-flop.

Table 1 Timing parameters of simulation experiment results (take the circuit in Figure 1 as the simulation object)

Table 2 Irms and EDP of flip-flops at different flip rates (taking the circuit in Figure 1 as the simulation object)

Table 1 is the timing parameters of the simulation experiment results. It can be seen from the data in the table that the single-phase clock double-edge D flip-flop of the present invention has excellent performance. When triggering on the rising edge, the maximum propagation delay is only 14.71ps; when triggering on the falling edge, the maximum propagation delay is only 16.67ps. Table 2 is the power consumption evaluation of the circuit. When the voltage and simulation time of the circuit are fixed, the root mean square current Irms and the energy consumption delay product EDP of the circuit are used as evaluation standards under different data flipping rates. As can be seen from the data in Table 2, the single-phase clock double-edge D flip-flop of the present invention has a very small energy consumption delay product, and when the data turnover rate is 50%, the EDP is only 443.89 (fJ.ps); When the data turnover rate is 100%, the EDP is only 246.27(fJ.ps).

The single-phase clock double-edge D flip-flop of the present invention can not only complete the correct sampling and transmission of data at the rising edge and falling edge of the clock signal, but also has fast response speed and low energy consumption delay product. The single-phase clock double-edge D flip-flop has a simple circuit structure and a small number of transistors. It is a double-edge D flip-flop with good performance and has broad application prospects in high-speed, low-power digital processing systems.

Finally, it should be pointed out that the above-mentioned embodiment description is not a limitation of the present invention, but only a feasible solution of the present invention, and those skilled in the relevant technical fields can make modifications, additions and replacements within the spirit and principles of the present invention. , should be within the protection scope of the present invention.

Claims (3)

1. A double-edge D flip-flop of a single-phase clock is characterized in that it comprises a rising edge trigger circuit (1), a falling edge trigger circuit (2), the first inverter INV1, the second inverter INV2 and two input The NAND gate circuit (3); the rising edge trigger circuit (1) is connected to the two-input NAND gate circuit (3), and the falling edge trigger circuit (2) is connected to the two-input NAND gate circuit ( 3); The rising edge trigger circuit (1) is connected to the first inverter INV1; The rising edge trigger circuit includes a first PMOS transistor PM1, a second PMOS transistor PM2, a first NMOS transistor NM1 and a second NMOS transistor NM2; the source of the first PMOS transistor PM1 is connected to the power supply voltage Vdd, and the gate is connected to the clock signal CLK , the drain is connected to the drain of the first NMOS transistor NM1 and the gate of the second NMOS transistor NM2; the source of the second PMOS transistor PM2 is connected to the power supply voltage Vdd, the gate is connected to the clock signal CLK, and the drain is connected to the The drain of the second NMOS transistor NM2, the gate of the fifth PMOS transistor PM5, and the gate of the sixth NMOS transistor NM6 are all connected; the source of the first NMOS transistor NM1 is connected to the ground line Gnd, and the gate is connected to the first NMOS transistor NM1. The output terminal of the inverter INV1 is connected; the source of the second NMOS transistor NM2 is connected to the ground line Gnd; The falling edge trigger circuit includes a third PMOS transistor PM3, a fourth PMOS transistor PM4, a third NMOS transistor NM3, and a fourth NMOS transistor NM4; the source of the third PMOS transistor PM3 is connected to the power supply voltage Vdd, and the gate is connected to the input signal D , the drain is connected to the drain of the third NMOS transistor NM3 and the gate of the fourth PMOS transistor PM4; the source of the fourth PMOS transistor PM4 is connected to the power supply voltage Vdd, and the drain is connected to the drain of the fourth NMOS transistor NM4 Both are connected to the input ends of the second inverter INV2; the gate of the third NMOS transistor NM3 is connected to the clock signal CLK, and the source is connected to the ground line Gnd; the gate of the fourth NMOS transistor NM4 is connected to the clock signal CLK Connected, the source is connected to the ground Gnd. 2. A kind of single-phase clock double-edge D flip-flop according to claim 1, wherein the two-input NAND gate circuit comprises a fifth PMOS transistor PM5, a sixth PMOS transistor PM6, a fifth NMOS transistor NM5 and a fifth NMOS transistor NM5. Six NMOS transistors NM6; the source of the fifth PMOS transistor PM5 is connected to the power supply voltage Vdd, and the gate is in phase with the drain of the second PMOS transistor PM2, the drain of the second NMOS transistor NM2, and the gate of the sixth NMOS transistor NM6 connected, the drain is connected to the drain of the sixth PMOS transistor PM6, the drain of the sixth NMOS transistor NM6 and the output terminal Q; the source of the sixth PMOS transistor PM6 is connected to the power supply voltage Vdd, and the gate is connected to the fifth NMOS transistor The gate of the transistor NM5 is connected to the output terminal of the second inverter INV2; the source of the fifth NMOS transistor NM5 is connected to the ground line Gnd, and the drain is connected to the source of the sixth NMOS transistor NM6. 3. A kind of single-phase clock double-edge D flip-flop according to claim 1, characterized in that, the input terminal of the first inverter INV1 is connected with the input signal D, and the output terminal is connected with the gate of the first NMOS transistor NM1 connected; the input end of the second inverter INV2 is connected to the drain of the fourth PMOS transistor PM4 and the drain of the fourth NMOS transistor NM4, and the output end is connected to the gate of the fifth NMOS transistor NM5 and the sixth PMOS transistor PM6 The gates are connected in phase.

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