CN109525222B - Double-edge D trigger of single-phase clock - Google Patents
Double-edge D trigger of single-phase clock Download PDFInfo
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Abstract
The invention discloses a single-phase clock double-edge D trigger, comprising: the circuit comprises a rising edge trigger circuit 1, a falling edge trigger circuit 2, two inverters and a two-input NAND gate circuit 3. In the Cadence environment, the UMC 28nmCMOS process is adopted to carry out analog simulation on the single-phase clock double-edge D trigger, and a simulation result shows that the circuit can finish correct sampling transmission of data on the rising edge and the falling edge of a clock signal, and has high response speed and low energy consumption delay product. The single-phase clock double-edge D trigger circuit is simple in structure, the number of the transistors is small, the single-phase clock double-edge D trigger is good in performance, and the single-phase clock double-edge D trigger circuit has wide application prospects in a high-speed and low-power-consumption digital processing system.
Description
Technical Field
The invention belongs to the field of D triggers, and particularly relates to a single-phase clock double-edge D trigger.
Background
In the present field of large scale integrated circuit design, reducing power consumption and increasing data processing rate are important concerns. The flip-flop is widely applied to a digital integrated circuit system, and the flip-flop not only can control the jumping process of the circuit operation, but also can be used for realizing a frequency divider, a counter, a register and the like. In digital systems, approximately 30% to 70% of the system power consumption is used to drive the clock network and flip-flops, whose transmission time also limits the rate of data processing. Therefore, in the present digital processing system with high speed and low power consumption, the seeking of a trigger with low power consumption and high speed has important significance.
Among the various flip-flops, the D flip-flop is the most commonly used element. The D flip-flop can be divided into a single edge flip-flop (rising edge or falling edge of the clock) and a double edge flip-flop (rising edge and falling edge of the clock respectively perform data sampling transmission). Compared with a single-edge D trigger, the double-edge D trigger can realize twice data processing amount under the condition of consistent clock rate, thereby better meeting the requirements of high rate and low power consumption of digital integrated circuit development.
As shown in fig. 3, the conventional falling edge D flip-flop is composed of 16 transistors (in which the inverters INV1 and INV2 and the CMOS transmission gates TG1 and TG2 are both composed of two CMOS transistors), an inverter, a CMOS transmission gate, and the like. In fig. 3, CLK represents a clock signal, CLKB represents an inverted signal of CLK, and when the clock CLK is active (the clock jumps from high to low), the circuit can transfer input data D to an output node Q (Q = D); when the clock CLK stops (the clock goes low), the circuit can still maintain its logic level at the output node. The main disadvantage of the conventional D flip-flop is that the capacitive load of the clock signal is large, which may cause the power consumption of the clock network to increase, and meanwhile, the D flip-flop implemented by using the CMOS transmission gate also has a signal reverse conduction problem, so that the subsequent circuit may affect the state of the first stage latch, causing the register to output wrong data.
Disclosure of Invention
The present invention provides a single-phase clock double-edge D flip-flop to solve the above problems.
In order to achieve the purpose, the invention adopts the following technical scheme:
a single-phase clock double-edge D flip-flop comprises a rising edge trigger circuit (1), a falling edge trigger circuit (2), a first inverter INV1, a second inverter INV2 and a two-input NAND gate circuit (3); the rising edge trigger circuit (1) is connected with the two-input NAND gate circuit (3), and the falling edge trigger circuit (2) is connected to the two-input NAND gate circuit (3) through a second inverter INV 2; the rising edge trigger circuit (1) is connected with the first inverter INV1.
Further, the rising edge trigger circuit comprises a first PMOS tube PM1, a second PMOS tube PM2, a first NMOS tube NM1 and a second NMOS tube NM2; the source electrode of the first PMOS tube PM1 is connected with a power supply voltage Vdd, the grid electrode of the first PMOS tube PM1 is connected with a clock signal CLK, and the drain electrode of the first PMOS tube PM1 is connected with the drain electrode of the first NMOS tube NM2; the source electrode of the second PMOS tube PM2 is connected with a power supply voltage Vdd, the grid electrode of the second PMOS tube PM2 is connected with a clock signal CLK, and the drain electrode of the second NMOS tube NM2, the grid electrode of the fifth PMOS tube PM5 and the grid electrode of the sixth NMOS tube NM6 are all connected; the source electrode of the first NMOS tube NM1 is connected with a ground wire Gnd, and the grid electrode of the first NMOS tube NM1 is connected with the output end of the first inverter INV1; the source of the second NMOS transistor NM2 is connected to the ground Gnd.
Further, the falling edge trigger circuit comprises a third PMOS transistor PM3, a fourth PMOS transistor PM4, a third NMOS transistor NM3 and a fourth NMOS transistor NM4; the source electrode of the third PMOS tube PM3 is connected with a power supply voltage Vdd, the grid electrode of the third PMOS tube PM3 is connected with an input signal D, and the drain electrode of the third PMOS tube PM3 is connected with the drain electrode of the third NMOS tube NM3 and the grid electrode of the fourth PMOS tube PM 4; the source electrode of the fourth PMOS tube PM4 is connected with a power supply voltage Vdd, and the drain electrode of the fourth PMOS tube PM4 is connected with the drain electrode of the fourth NMOS tube NM4 and the input end of the second inverter INV 2; the grid electrode of the third NMOS tube NM3 is connected with a clock signal CLK, and the source electrode is connected with a ground wire Gnd; the grid electrode of the third NMOS tube NM4 is connected with a clock signal CLK, and the source electrode is connected with a ground wire Gnd.
Further, the two-input nand gate circuit comprises a fifth PMOS transistor PM5, a sixth PMOS transistor PM6, a fifth NMOS transistor NM5 and a sixth NMOS transistor NM6; a source electrode of the fifth PMOS tube PM5 is connected with a power supply voltage Vdd, a grid electrode of the fifth PMOS tube PM5 is connected with a drain electrode of the second PMOS tube PM2, a drain electrode of the second NMOS tube NM2 and a grid electrode of the sixth NMOS tube NM6, and a drain electrode of the fifth PMOS tube PM6, a drain electrode of the sixth NMOS tube NM6 and an output end Q are connected; the source electrode of the sixth PMOS tube PM6 is connected with the power supply voltage Vdd, and the grid electrode of the sixth NMOS tube NM5 is connected with the output end of the second inverter INV 2; the source of the fifth NMOS transistor NM5 is connected to the ground Gnd, and the drain is connected to the source of the sixth NMOS transistor NM6.
Further, the input end of the first inverter INV1 is connected to the input signal D, and the output end is connected to the gate of the first NMOS transistor NM 1; an input end of the second inverter INV2 is connected to both the drain of the fourth PMOS transistor PM4 and the drain of the fourth NMOS transistor NM4, and an output end is connected to both the gate of the fifth NMOS transistor NM5 and the gate of the sixth PMOS transistor PM 6.
Compared with the prior art, the invention has the following technical effects:
the edge trigger circuit is only composed of 4 transistors, so that the propagation delay of the circuit is short, and the response speed is high. The energy consumption delay product calculation formula is shown as follows:
EDP＝P av t p 2
in the formula P av Representing the average power consumption per flip of the output signal. From the above equation, the EDP is proportional to the square of the propagation delay of the circuit, and has a low EDP product because the propagation delay of the circuit is short.
The single-phase clock double-edge D trigger circuit has a simple structure and a small number of transistors, is a double-edge D trigger with good performance, and has wide application prospect in a high-speed and low-power-consumption digital processing system.
Drawings
FIG. 1 is a circuit diagram of a single-phase clock double-edge D flip-flop according to the present invention;
fig. 2 is a logic simulation timing diagram of the single-phase clock double-edge D flip-flop of the present invention.
FIG. 3 is a circuit diagram of a conventional falling edge D flip-flop;
Detailed Description
The invention is further described below with reference to the accompanying drawings:
fig. 1 is a circuit diagram of a single-phase clock double-edge D flip-flop according to an embodiment of the present invention, where the double-edge D flip-flop includes a rising edge flip-flop 1, a falling edge flip-flop 2, two inverters, and a two-input nand gate 3.
Referring to fig. 1, the rising edge trigger circuit 1 includes: the transistor comprises a first PMOS (P-channel metal oxide semiconductor) transistor PM1, a second PMOS transistor PM2, a first NMOS (N-channel metal oxide semiconductor) transistor NM1 and a second NMOS transistor NM2. Wherein,
the source electrode of the first PMOS tube PM1 is connected with a power supply voltage Vdd, the grid electrode of the first PMOS tube PM1 is connected with a clock signal CLK, and the drain electrode of the first PMOS tube PM1 is connected with the drain electrode of the first NMOS tube NM2; the source electrode of the second PMOS tube PM2 is connected with a power supply voltage Vdd, the grid electrode of the second PMOS tube PM2 is connected with a clock signal CLK, and the drain electrode of the second PMOS tube PM2, the grid electrode of the fifth PMOS tube PM5 and the grid electrode of the sixth NMOS tube NM6 are connected; the source electrode of the first NMOS tube NM1 is connected with a ground wire Gnd, and the grid electrode of the first NMOS tube NM1 is connected with the output of the first inverter INV1; and the source electrode of the second NMOS tube NM2 is connected with the ground wire Gnd.
Referring to fig. 1, the falling edge trigger circuit 2 includes: a third PMOS transistor PM3, a fourth PMOS transistor PM4, a third NMOS transistor NM3, and a fourth NMOS transistor NM4. Wherein,
the source electrode of the third PMOS tube PM3 is connected with a power supply voltage Vdd, the grid electrode of the third PMOS tube PM3 is connected with an input signal D, and the drain electrode of the third PMOS tube PM3 is connected with the drain electrode of the fourth PMOS tube PM 4; the source electrode of the fourth PMOS tube PM4 is connected with a power supply voltage Vdd, and the drain electrode of the fourth PMOS tube PM4 is connected with the drain electrode of the fourth NMOS tube NM4 and the input end of the second inverter INV 2; the grid electrode of the third NMOS tube NM3 is connected with a clock signal CLK, and the source electrode is connected with a ground wire Gnd; the grid electrode of the third NMOS tube NM4 is connected with a clock signal CLK, and the source electrode is connected with a ground wire Gnd.
Referring to fig. 1, the two-input nand gate circuit 3 includes: fifth PMOS pipe PM5 and sixth PMOS pipe
PM6, a fifth NMOS transistor NM5, and a sixth NMOS transistor NM6. Wherein,
the source electrode of the fifth PMOS tube PM5 is connected with a power supply voltage Vdd, the grid electrode of the fifth PMOS tube PM5 is connected with the drain electrode of the second PMOS tube PM2, the drain electrode of the second NMOS tube NM2 and the grid electrode of the sixth NMOS tube NM6, and the drain electrode of the fifth PMOS tube PM6 is connected with the drain electrode of the sixth NMOS tube NM6 and the output end Q; the source electrode of the sixth PMOS tube PM6 is connected with a power supply voltage Vdd, and the grid electrode of the sixth PMOS tube PM6 is connected with the grid electrode of the fifth NMOS tube NM5 and the output end of the second inverter INV 2; and the source electrode of the fifth NMOS tube NM5 is connected with the ground wire Gnd, and the drain electrode of the fifth NMOS tube NM5 is connected with the source electrode of the sixth NMOS tube NM6.
Referring to fig. 1, an input end of the first inverter INV1 is connected to an input signal D, and an output end is connected to a gate of the first NMOS transistor NM 1; the input end of the second inverter INV2 is connected to the drain of the fourth PMOS transistor PM4 and the drain of the fourth NMOS transistor NM4, and the output end is connected to the gate of the fifth NMOS transistor NM5 and the gate of the sixth PMOS transistor PM 6.
The working principle of the single-phase clock double-edge D flip-flop of the present invention is described as follows:
first, the triggering process of the clock rising edge is analyzed, please refer to the rising edge triggering circuit 1 in fig. 1. When the input signal D1 is low and the clock signal CLK is low, the first NMOS transistor NM1 is turned off, and the first PMOS transistor PM1 is turned on, so that the node a is charged to a high level. At this time, the second NMOS transistor NM2 and the second PMOS transistor PM2 are turned on, and by reasonably setting the size of NM2 and PM2, the charge of the node B is greater than the discharge, so the node B will be charged to a high level. When the clock signal CLK changes from low level to high level, that is, when the clock rising edge arrives, the first PMOS transistor PM1 and the second PMOS transistor PM2 will be turned off, the node a still remains at the original high level, the second NMOS transistor NM2 is turned on, the node B will discharge to low level "0" through NM2, and at this time, the low level of the input signal D1 is correctly transmitted to the output node B. When the input signal D1 is at a high level and the clock signal CLK is at a low level, the first NMOS transistor NM1 and the first PMOS transistor PM1 are turned on, and by reasonably setting the size of NM1 and PM1, the discharging of the node a is greater than the charging, so that the node a is discharged to a low level "0". At this time, the second NMOS transistor NM2 is turned off, and the second PMOS transistor PM2 is turned on, so that the node B is charged to a high level through PM 2. When the clock signal CLK changes from low level to high level, that is, when the clock rising edge arrives, the first PMOS transistor PM1 and the second PMOS transistor PM2 will be turned off, the node a still remains at the original low level "0", and the second NMOS transistor NM2 is turned off, so the node B still remains at the original high level, and at this time, the high level of the input signal D1 is correctly transmitted to the output node B. When the clock signal CLK is at a high level, the first PMOS transistor PM1 and the second PMOS transistor PM2 are turned off, and if the input signal D1 jumps from a high level to a low level, the first NMOS transistor NM1 is turned off, the node a maintains the original low level "0", the second NMOS transistor NM2 is turned off, and the node B maintains the original high level. When the clock signal CLK is at a high level, the first PMOS transistor PM1 and the second PMOS transistor PM2 are turned off, and if the input signal D1 changes from a low level to a high level, the first NMOS transistor NM1 is turned on, and the node a discharges to a low level "0" through the NM1, then the second NMOS transistor NM2 is turned off, and the node B keeps the original low level "0". In summary, the rising edge trigger circuit 1 can correctly realize the rising edge triggering of the clock signal CLK, and correctly transmit the input signal D1 to the output node B. When the CLK is low, the output node B is constantly high, and when the CLK is high, the output node B is not disturbed by the change of the input signal D1.
The triggering process of the clock falling edge is analyzed, please refer to the falling edge triggering circuit 2 in fig. 1. When the input signal D is at a high level and the clock signal CLK is at a high level, the third NMOS transistor NM3 is turned on, the third PMOS transistor PM3 is turned off, and the node C is discharged to a low level "0". At this time, the fourth NMOS transistor NM4 and the fourth PMOS transistor PM4 are turned on, and by reasonably setting the size of NM4 and PM4, the discharging of the node F is greater than the charging, so that the node F will be discharged to the low level "0" through NM4. When the clock signal CLK changes from high level to low level, that is, when the clock falling edge arrives, the third NMOS transistor NM3 and the fourth NMOS transistor NM4 will be turned off, the node C still remains at the original low level "0", the fourth PMOS transistor PM4 is turned on, the node F will be charged to high level through the node PM4, and at this time, the high level of the input signal D is correctly transmitted to the output node F. When the input signal D is at a low level and the clock signal CLK is at a high level, the third NMOS transistor NM3 and the third PMOS transistor PM3 are turned on, and by reasonably setting the size of NM3 and PM3, the charging of the node C is greater than the discharging, so the node C is charged at a high level. At this time, the fourth PMOS transistor PM4 is turned off, and the fourth NMOS transistor NM4 is turned on, so that the node F is discharged to the low level "0" through NM4. When the clock signal CLK changes from high level to low level, that is, when the clock falling edge arrives, the third NMOS transistor NM3 and the fourth NMOS transistor NM4 will be turned off, the node C still remains at the original high level, and the fourth PMOS transistor PM4 is turned off, so the node F still remains at the original low level "0", and at this time, the low level of the input signal D is correctly transmitted to the output node F. When the clock signal CLK is at a low level, the third NMOS transistor NM3 and the fourth NMOS transistor NM4 are turned off, and if the input signal D changes from a high level to a low level, the third PMOS transistor PM3 is turned on, and the node C is charged to a high level through the PM3, so that the fourth PMOS transistor PM4 is turned off, and the node F maintains the original high level. When the clock signal CLK is at a low level, the third NMOS transistor NM3 and the fourth NMOS transistor NM4 are turned off, and if the input signal D jumps from a low level to a high level, the third PMOS transistor PM3 is turned off, and the node C keeps the original high level, then the fourth PMOS transistor PM4 is turned off, and the node F keeps the original low level "0". In summary, the falling edge trigger circuit 2 can correctly realize the falling edge trigger of the clock signal CLK, and correctly transmit the input signal D to the output node F. When CLK is high, the output node F is constantly low "0", and when CLK is low, the output node F is not disturbed by the change of the input signal D.
An analysis of the above two circuit characteristics shows that the rising edge trigger circuit 1 has the level of the output node B during the high level of the clock pulse CLK, which is charged to the high level or discharged to the low level "0" depending on the value of the input signal D1 at the required settling time before the rising edge of the clock pulse CLK, and has a path connected to the power supply voltage Vdd during the low level of the clock pulse CLK, which is charged to the high level. The falling edge trigger circuit 2 is configured such that during the low level of the clock pulse CLK, the level of the output node F is dependent on the value of the input signal D at the required settling time before the falling edge of the clock pulse CLK, and the output node F will be charged to the high level or discharged to the low level "0", and during the high level of the clock pulse CLK, the output node F has a path connected to the ground Gnd and will be discharged to the low level "0". Therefore, the two circuits are functionally complementary, and the output node F (B) has a path connected to the ground Gnd (power supply voltage Vdd) during the period when the clock pulse CLK is high (low).
By utilizing the characteristics of the two circuits, when the rising edge of the clock signal CLK comes, the falling edge trigger circuit 2 outputs a constant 0 when the CLK is at a high level, so that the structure of the rising edge trigger circuit 1 can be used as a signal to output; when the falling edge of the clock signal CLK comes, the falling edge trigger circuit 2 can be used as a signal output to complete the function of double-edge trigger by utilizing the characteristic that the rising edge trigger circuit 1 outputs constant 1 when the CLK is at a low level. The structure of the double-edge D flip-flop circuit is shown in FIG. 1, and the combined output structure is a two-input NAND gate circuit 3. When the clock pulse CLK changes from low level to high level, the rising edge trigger circuit 1 implements data sampling transmission, and the circuit node F is pre-discharged to low level "0", and the node E is made high level by the second inverter INV2, so that the output value Q of the nand gate circuit 3 depends on the value of the node B. When the clock pulse CLK changes from high level to low level, the falling edge trigger circuit 2 implements data sampling transmission, and the circuit node B is precharged to high level, so that the output value Q of the nand gate circuit 3 depends on the value of the node F. Finally, in order to make the output data have the same polarity as the input data, two inverters INV1 and INV2 are inserted in the circuit.
In summary, the single-phase clock double-edge D flip-flop of the present invention can respectively complete the correct sampling transmission of the input data at the output end on the rising edge and the falling edge of the clock by the combined control of the rising edge D flip-flop circuit, the falling edge flip-flop circuit, the two inverters, and the two input nand gates. During the stable period of the clock level, the output node is not interfered by the change of the state of the input signal, and the double-edge D trigger controlled by the single-phase clock is realized.
The single-phase clock double-edge D trigger is realized by adopting a UMC 28nm CMOS process. And (3) carrying out simulation verification on the double-edge D trigger in a Cadence environment, wherein the environment temperature is 27 ℃, the process angle is TT, and the power supply voltage is 1.05V.
Referring to fig. 3, fig. 3 is a logic simulation timing diagram of a single-phase clock double-edge D flip-flop according to an embodiment of the present invention, where CLK is a clock signal, D is an input signal, B is an output signal of a node B, E is an output signal of a node E, and Q is a final output signal of the double-edge D flip-flop. As can be seen from the simulation results, the output state of the node B jumps at the rising edge of the clock signal, the output state of the node F jumps at the falling edge of the clock signal, and finally
The state of the output signal Q transitions on both rising and falling edges. During the period of stable clock signal level, the output signal Q is not interfered by the change of the input signal state, the logic function of the whole trigger is correct, and the trigger is a single-phase clock double-edge D trigger.
TABLE 1 timing parameters of simulation test results (with the circuit of FIG. 1 as the simulation object)
TABLE 2 Irms and EDP for flip-flops at different slew rates (subject to simulation by the circuit of FIG. 1)
Table 1 shows the timing parameters of the simulation experiment results, and it can be seen from the data in the table that the single-phase clock double-edge D flip-flop of the present invention has excellent performance. When the rising edge triggers, the maximum propagation delay only needs 14.71ps; at falling edge triggering, the maximum propagation delay needs only 16.67ps. Table 2 shows the power consumption evaluation of the circuit, and when the voltage and the simulation time of the circuit are fixed, the root mean square current Irms and the power consumption delay product EDP of the circuit are used as evaluation criteria at different data inversion rates. As can be seen from the data in table 2, the single-phase clock double-edge D flip-flop of the present invention has a very small power consumption delay product, and at a data flip-flop rate of 50%, the EDP is only 443.89 (fj.ps); at a data turnover rate of 100%, the EDP was only 246.27 (fj.ps).
The single-phase clock double-edge D trigger can finish correct sampling transmission of data on the rising edge and the falling edge of a clock signal, and has high response speed and low energy consumption delay product. The single-phase clock double-edge D trigger circuit is simple in structure, few in transistor number, good in performance and wide in application prospect in a high-speed and low-power-consumption digital processing system.
Finally, it should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and are merely possible implementations of the invention, and those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention.
Claims (3)
1. A single-phase clock double-edge D flip-flop is characterized by comprising a rising edge trigger circuit (1), a falling edge trigger circuit (2), a first inverter INV1, a second inverter INV2 and a two-input NAND gate circuit (3); the rising edge trigger circuit (1) is connected with the two-input NAND gate circuit (3), and the falling edge trigger circuit (2) is connected to the two-input NAND gate circuit (3) through a second inverter INV 2; the rising edge trigger circuit (1) is connected with the first inverter INV1;
the rising edge trigger circuit comprises a first PMOS (P-channel metal oxide semiconductor) tube PM1, a second PMOS tube PM2, a first NMOS (N-channel metal oxide semiconductor) tube NM1 and a second NMOS tube NM2; the source electrode of the first PMOS tube PM1 is connected with a power supply voltage Vdd, the grid electrode of the first PMOS tube PM1 is connected with a clock signal CLK, and the drain electrode of the first PMOS tube PM1 is connected with the drain electrode of the first NMOS tube NM2; the source electrode of the second PMOS tube PM2 is connected with a power supply voltage Vdd, the grid electrode of the second PMOS tube PM2 is connected with a clock signal CLK, and the drain electrode of the second NMOS tube NM2, the grid electrode of the fifth PMOS tube PM5 and the grid electrode of the sixth NMOS tube NM6 are all connected; the source electrode of the first NMOS tube NM1 is connected with a ground wire Gnd, and the grid electrode of the first NMOS tube NM1 is connected with the output end of the first inverter INV1; the source electrode of the second NMOS tube NM2 is connected with a ground wire Gnd;
the falling edge trigger circuit comprises a third PMOS tube PM3, a fourth PMOS tube PM4, a third NMOS tube NM3 and a fourth NMOS tube NM4; the source electrode of the third PMOS tube PM3 is connected with a power supply voltage Vdd, the grid electrode of the third PMOS tube PM3 is connected with an input signal D, and the drain electrode of the third PMOS tube PM3 is connected with the drain electrode of the fourth PMOS tube PM 4; the source electrode of the fourth PMOS tube PM4 is connected with the power supply voltage Vdd, and the drain electrode of the fourth PMOS tube PM4 is connected with the drain electrode of the fourth NMOS tube NM4 and the input end of the second inverter INV 2; the grid electrode of the third NMOS tube NM3 is connected with a clock signal CLK, and the source electrode is connected with a ground wire Gnd; and the grid electrode of the fourth NMOS tube NM4 is connected with a clock signal CLK, and the source electrode is connected with a ground wire Gnd.
2. The single-phase clock double-edge D flip-flop according to claim 1, wherein the two-input NAND gate circuit comprises a fifth PMOS transistor PM5, a sixth PMOS transistor PM6, a fifth NMOS transistor NM5 and a sixth NMOS transistor NM6; the source electrode of the fifth PMOS tube PM5 is connected with a power supply voltage Vdd, the grid electrode of the fifth PMOS tube PM5 is connected with the drain electrode of the second PMOS tube PM2, the drain electrode of the second NMOS tube NM2 and the grid electrode of the sixth NMOS tube NM6, and the drain electrode of the fifth PMOS tube PM6 is connected with the drain electrode of the sixth NMOS tube NM6 and the output end Q; the source electrode of the sixth PMOS tube PM6 is connected with the power supply voltage Vdd, and the grid electrode of the sixth NMOS tube NM5 is connected with the output end of the second inverter INV 2; the source of the fifth NMOS transistor NM5 is connected to the ground Gnd, and the drain is connected to the source of the sixth NMOS transistor NM6.
3. The single-phase clock double-edge D flip-flop according to claim 1, wherein an input terminal of the first inverter INV1 is connected to the input signal D, and an output terminal thereof is connected to a gate of the first NMOS transistor NM 1; an input end of the second inverter INV2 is connected to both the drain of the fourth PMOS transistor PM4 and the drain of the fourth NMOS transistor NM4, and an output end is connected to both the gate of the fifth NMOS transistor NM5 and the gate of the sixth PMOS transistor PM 6.
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| CN114050807B (en) * | 2021-11-05 | 2024-03-26 | 安徽大学 | Master-slave trigger based on TFET |
| CN118297011B (en) * | 2024-06-06 | 2024-09-13 | 天水天光半导体有限责任公司 | Simulation optimization method of D trigger and D trigger |
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| CN1697320A (en) * | 2005-06-15 | 2005-11-16 | 清华大学 | Sensitive amplifier structured falling edge CMOS trigger |
| CN1702963A (en) * | 2005-06-09 | 2005-11-30 | 清华大学 | Synchronous enabled type condition presetting CMOS trigger |
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| US9520877B2 (en) * | 2014-12-16 | 2016-12-13 | Intel Corporation | Apparatus and method for detecting or repairing minimum delay errors |
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| CN1702963A (en) * | 2005-06-09 | 2005-11-30 | 清华大学 | Synchronous enabled type condition presetting CMOS trigger |
| CN1697320A (en) * | 2005-06-15 | 2005-11-16 | 清华大学 | Sensitive amplifier structured falling edge CMOS trigger |
| CN102723930A (en) * | 2012-06-29 | 2012-10-10 | 北京大学 | Double-edge D trigger |
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