CN1702963A - Synchronous enabled type condition presetting CMOS trigger - Google Patents
Synchronous enabled type condition presetting CMOS trigger Download PDFInfo
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Abstract
This invention relates to simultaneous CMOS trigger in D trigger technique field, which is characterized by the following: it is composed of simultaneous circuit and first and second locking connection, wherein, the circuit comprises two CMOS transmission gates for inputting data signal and one output signal of the second locker and the two gates outputs the data signals to the first locker under the control of the anti-phase signals. The first locker adopts input data controlled pre-charging circuit and the second locker adopts two same circuits parameter single phase clock, wherein, the output end is symmetric to the down end with one circuit of output end of the two locker to realize the stability of the clock signal in low level.
Description
Technical field
The circuit that is proposed is the part of " condition prechargig CMOS trigger " series.Feature is to have " synchronous scanning " the direct applied technical field of control is to adopt the design of low-power consumption flip-flop circuit.
Background technology
Along with the progress of CMOS integrated circuit fabrication process, the scale and the complexity of integrated circuit increase day by day, and power consumption of integrated circuit and heat dissipation problem more and more obtain the attention from industrial quarters and academia.Based on present integrated circuit (IC) design style, in the large scale digital Circuits System, the ratio that the energy of clock network consumption accounts for the total power consumption of entire circuit remains high always; Wherein, under the circuit working state, (trigger: energy Flip-Flop) becomes the important source of clock network energy consumption again in clock interconnection gauze and sequence circuit unit in consumption, and the power consumption ratio of the two has ever-increasing trend (to see document David E.Duarte, N.Vijaykrishnan, and Mary Jane Irwin, " A Clock Power Model to Evaluate Impact of Architecturaland Technology Optimizations ", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.10, no.6, pp.844-855, December 2002.).
CMOS power consumption of integrated circuit source mainly contains dynamic power consumption, quiescent dissipation, short circuit current power consumption and leakage current power consumption.Wherein dynamic power consumption accounts for major part.Under certain circuit performance constraint, the dynamic power consumption P of CMOS integrated circuit node
DynamicIt is this node load capacitor C
L, supply voltage V
DDVoltage swing V with this node
SwingFunction, that is:
P
Dynamic＝C
LV
DDV
Swingfα???????????????????????(1)
Wherein, f is the operating frequency of circuit, and α is the signal activity.From formula (1), as seen, reduce α, C
L, V
DDAnd V
SwingAll can reduce the dynamic power consumption of circuit.Be different from the data-signal gauze, the clock cable netting gear has the characteristics of big interconnection line parasitic capacitance and high signal activity, by reducing the voltage signal amplitude of oscillation V of clock signal gauze
SwingCan be at the energy that guarantees to reduce under the condition of circuit performance to consume on the clock interconnection line.The flip-flop circuit unit is widely used in integrated circuit (IC) design.Be the flip-flop circuit cell schematics as shown in Figure 1.Be illustrated in figure 2 as the traditional flip-flop circuit unit basic circuit structure that is widely used in the design of digital circuit standard cell lib, the main feature of sort circuit structure is that circuit structure is fairly simple, but clock signal upset each time all can cause the upset of circuit internal node, and circuit power consumption is bigger.H.Kawaguchi propose a kind of flip-flop circuit RCSFF that can adopt low-voltage amplitude of oscillation clock signal to drive (see document H.Kawaguchi and T.Sakurai: " A ReducedClock-Swing Flip-Flop (RCSFF) for 63%Power Reduction " ', IEEE JOURNAL OF SOLID-STATECIRCUITS, VOL.33, NO.5, MAY 1998, PP.807-811.), but the problem of sort circuit is when clock signal low level each time, extra energy consumption can be caused to circuit internal node condition presetting electricity in the capital.On the basis of RCSFF circuit, the flip-flop circuit SAFF_CP that SALATCH_P.Zhang proposes a kind of low-voltage amplitude of oscillation clock signal driving of condition condition presetting construction (sees document Y.Zhang, H.Yang, and H.Wang, " Low clock-swing conditional-prechargeflip-flop for more than 30%power reduction; " Electron.Lett., vol.36, no.9, pp.785-786, Apr.2000.), as shown in Figure 3.The maximum characteristics of this flip-flop circuit are if the flip-flop circuit input remains unchanged when the clock signal low level, and circuit can be to its internal node condition presetting between the clock signal low period.The employing of this technology greatly reduces the power consumption of flip-flop circuit itself.But, the problem that the SAFF_CP circuit exists is, because the output latch circuit has adopted cross-couplings NAND2 (NAND2: two input NAND gate) structure, can cause time-delay of flip-flop circuit output rising edge and trailing edge time-delay extremely asymmetric, bring potential problem for the use of circuit unit.Be illustrated in figure 4 as cross-couplings NAND2 latch circuit.With V
OutaOutput is an example, works as V
InaBe low level ' 0 ', simultaneously V
InbDuring for high level ' 1 ', signal is through NAND gate NAND2_a, makes V
OutaThe upset of generation rising edge; Work as V
InaBe high level ' 1 ', simultaneously V
InbDuring for low level ' 0 ', V
OutaUpset can be do not produced at once, but V will be waited until
OutbAt first be turned to high level ' 1 ', afterwards just can be at V
OutaThe upset of generation trailing edge.This shows, for the SAFF_CP circuit that adopts cross-couplings NAND2 latch circuit as output, output end signal produces the trailing edge upset and always has more the time-delay of a door than producing the rising edge upset, has therefore caused the circuit rising edge to delay time and the trailing edge asymmetric problem of delaying time.
When upset of a kind of output end signal trailing edge and rising edge upset are arranged on the basis that existing condition presetting construction flip-flop circuit is the SAFF_CP circuit its delay time symmetry and settling time very little condition presetting CMOS trigger SAFF_CP_BRF, as shown in Figure 5.
Summary of the invention:
A kind of applied circuit is proposed on existing SAFF_CP_BRF circuit base: synchronous enabled type condition presetting CMOS trigger SAFF_CP_BRF_EC, as shown in Figure 6.
The invention is characterized in: described CMOS trigger is the rising edge trigger, contains:
First order latch comprises:
The 1st " or " logical circuit, contain two NMOS pipes, be designated as MN9 pipe and MN8 pipe; The drain electrode of these two NMOS pipes links to each other, ground connection after substrate links to each other; The source electrode of this MN8 pipe and grid meet input data signal VD; The grid of this MN9 pipe meets input data signal VDb, and this VDb signal is the inversion signal of described VD signal, and the source electrode of this MN9 pipe connects clock signal clk;
The 2nd " or " logical circuit, contain two NMOS pipes, be designated as MN10 pipe and MN11 pipe; The drain electrode of these two NMOS pipes links to each other, ground connection after substrate links to each other; The source electrode of this MN10 pipe and grid meet input data signal VDb; The grid of this MN11 pipe meets input data signal VD, and the source electrode of this MN11 pipe connects clock signal clk;
1PMOS pipe is designated as the MP1 pipe, described the 1st " or " clock signal clk and input data signal VDb in the logical circuit form " or " logic, and link to each other through the drain electrode of MN9 pipe and the grid of described MP1 pipe; The source electrode of this MP1 pipe with meet supply voltage VDD after substrate links to each other;
2PMOS pipe is designated as the MP2 pipe, described the 2nd " or " clock signal clk and data data in the logical circuit form " or " logic, and link to each other with the grid of described MP2 pipe through the drain electrode of described MN11 pipe; The source electrode of this MP2 pipe with meet supply voltage VDD after substrate links to each other;
3PMOS pipe is designated as the MP3 pipe, the source electrode of this MP3 pipe with meet supply voltage VDD after substrate links to each other;
4PMOS pipe is designated as the MP4 pipe, the source electrode of this MP4 pipe with meet supply voltage VDD after substrate links to each other;
The 4NMOS pipe is designated as the MN4 pipe, forms node SALATCH_N after the grid of the source electrode while of this MN4 pipe and the drain electrode of described MP1 pipe and MP3 pipe, MP4 pipe links to each other; The grid of this MN4 pipe forms node SALATCH_P with grid, the MP4 pipe of described MP3 pipe after linking to each other with the drain electrode of MP2 pipe simultaneously; The substrate ground connection of this MN4 pipe;
The 5NMOS pipe is designated as the MN5 pipe, and the source electrode of this MN5 pipe links to each other with described node SALATCH_P; The grid of this MN5 pipe links to each other with described node SALATCH_N; The substrate ground connection of this MN5 pipe;
The 2NMOS pipe is designated as the MN2 pipe, and the source electrode of this MN2 pipe links to each other with the drain electrode of described MN4 pipe; The substrate ground connection of this MN2 pipe;
The 3NMOS pipe is designated as the MN3 pipe, and the source electrode of this MN3 pipe links to each other with the drain electrode of described MN5; The substrate ground connection of this MN3 pipe;
The 1NMOS pipe is designated as the MN1 pipe, and the source electrode of this MN1 pipe links to each other with the drain electrode of MN3 pipe with described MN2 pipe simultaneously; The grid of this MN1 pipe connects clock signal clk; The substrate ground connection of this MN1 pipe;
The 1st inverter is designated as inverter φ
1, this inverter φ
1Input and the grid of described MN2 pipe link to each other, form the input of input data signal VD; This inverter φ
1Output be the output of an input data signal VDb, this output links to each other with the grid of described MN3 pipe;
Second level latch comprises two single clock phase latch with same electrical mathematic(al) parameter, and this second level latch contains:
5PMOS pipe is designated as the MP0_1 pipe, the source electrode of this MP0_1 pipe with meet supply voltage VDD after substrate links to each other; The grid of this MP0_1 pipe meets described node SALATCH_P;
6PMOS pipe is designated as the MP0_2 pipe, the source electrode of this MP0_2 pipe with meet supply voltage VDD after substrate links to each other; The grid of this MP0_2 pipe meets described node SALATCH_N;
The 6NMOS pipe is designated as the MN1_1 pipe, and the grid of this MN1_1 pipe meets described node SALATCH_P, the substrate ground connection of this MN1_1 pipe;
The 7NMOS pipe is designated as the MN1_2 pipe, and the grid of this MN1_2 pipe meets described node SALATCH_N, the substrate ground connection of this MN1_2 pipe;
2nd, the 3 two inverter is designated as φ respectively
2And φ
3, described two anti-phase joining of inverter: the input of the 2nd inverter with link to each other simultaneously formation node QI again with the drain electrode of described MP0_1 pipe and the source electrode of MN1_1 pipe after the end of the output of the 3rd inverter links to each other; The 2nd inverter φ
2Output again with the 3rd inverter φ
3Input link to each other formation node QNI again with the drain electrode of described MP0_2 pipe and the source electrode of MN1_2 pipe after linking to each other;
The 8NMOS pipe is designated as the MN0_1 pipe, and the drain electrode of this MN0_1 pipe is the back ground connection that links to each other with substrate, and the grid of this MN0_1 pipe connects clock signal clk, and source electrode connects the drain electrode of described MN1_1 pipe;
The 9MOS pipe is designated as the MN0_2 pipe, and the drain electrode of this MN0_2 pipe is the back ground connection that links to each other with substrate, and grid connects clock signal clk, and source electrode connects the drain electrode of described MN1_2 pipe;
The 4th inverter is designated as inverter φ
4, this inverter φ
4Input link to each other with described node QNI, be output as the output Qb of described CMOS trigger;
The 5th inverter is designated as inverter φ
5, this inverter φ
5Input link to each other with described node QI, output signal is the another one output Q of described CMOS trigger;
Synchronous enabled circuit, the output of this circuit latchs it to described first, second two-stage synchronous enabled input signal VD is provided, and described synchronous enabled circuit comprises:
The 0th inverter is designated as inverter φ
0, this inverter φ
0Input link to each other with enable signal E, output signal is the inversion signal EN of enable signal;
The 1CMOS transmission gate contains two PMOS pipes parallel with one another and NMOS pipe, is designated as MPV pipe and MNN pipe successively respectively; Described MPV pipe with meet input data signal D after the source electrode of MNN pipe links to each other; Described MPV pipe and the grid that connects the MN2 pipe of described first order latch after the drain electrode of MNN pipe links to each other; The substrate of described MPV pipe meets supply voltage VDD, the substrate ground connection of MNN pipe;
The 2CMOS transmission gate contains two PMOS pipes parallel with one another and NMOS pipe, is designated as MPV ' pipe and MNN ' pipe respectively; Connect the grid of the MN2 pipe of described first order latch after the drain electrode parallel connection of described MPV ' pipe and MNN ' pipe; Meet the node QNI in the latch of the described second level after the source electrode parallel connection of described MPV ' pipe and MNN ' pipe; Synchronous enabled signal E links to each other with the grid of MPV ' pipe with described MNN pipe simultaneously; Described EN connects the grid of described MPV pipe and MNN ' pipe respectively; The substrate of described MPV ' pipe meets supply voltage VDD, the substrate ground connection of MNN ' pipe.
The invention has the beneficial effects as follows: can save with the trigger of identical function in the GSMC15 storehouse and be higher than 30% power consumption.The circuit delay characteristic quite or be better than circuit engineering that GSMC15 proposes and be suitable as very much the digital circuit standard cell and be applied in the low power consumption integrated circuit design.
Description of drawings
Fig. 1. the flip-flop circuit cell schematics, D is the data-signal input, and CK is a clock signal input terminal, and E is synchronous enabled signal input end, and Q and QN are the complementary signal output;
Fig. 2. (a) the flip-flop circuit unit F FEDHD1X circuit structure diagram that synchronous enabled type complementary output and rising edge trigger in the 0.15um technology digital standard cell library of GSMC; (b) signal generating circuit
Fig. 3 .SAFF_CP flip-flop circuit structure chart;
Fig. 4. cross-couplings NAND2 flip-latch circuit structure figure;
Fig. 5 .SAFF_CP_BRF flip-flop circuit structure chart;
Fig. 6. the SAFF_CP_BRF_EC flip-flop circuit structure chart that the present invention proposes;
Fig. 7 .SAFF_CP_BRF_EDCR flip-flop circuit structure chart;
Fig. 8. illustrate that the static time-delay of trigger, total time-delay define with figure.
Embodiment:
The technical scheme that the present invention solves its technical problem is: the synchronous enabled type condition presetting trigger SAFF_CP_BRF_EC that the present invention proposes, as shown in Figure 6.The SAFF_CP_BRF_EC trigger adopts the condition presetting technology to reduce the power consumption of flip-flop circuit own, and, can guarantee the complementary output end Q and the Q of SAFF_CP_BRF_EC trigger because the complementary output end of first order latch is connected respectively to two independently and have on the single clock phase latch of same circuits parameter
nCan realize the rising edge time-delay and the trailing edge time-delay of symmetry.With respect to the SAFF_CP flip-flop circuit, owing to removed NMOS pipe MN6 in the SAFF_CP_BRF_EC trigger, can improve characteristic settling time of circuit greatly, reduced dynamic power consumption, circuit structure is simpler simultaneously.Reduced by an extra high-voltage power supply line V in addition
Well(to PMOS pipe MP1, MP2 provides substrate biasing, V
Well＞V
DD), help using and designing of circuit more.
The operation principle of SAFF_CP_BRF_EC trigger is: two cmos transmission gates of synchronous enabled signal E and its inversion signal En control, a transmission when E=1, D delivers to output with data, output keeps two condition during E=0; Another transmission when E=0, the QNI identical with the Q waveform delivered to output, output keeps two condition during E=1.Two the transmission output connect together, a level trigger input signal is data D after during as the such E=1 of data input pin VD. of back level trigger, data D saltus step is followed in output under clock control, level trigger input signal just becomes QNI (with the Q homophase) after during E=0, also just realized " synchronous enabled ". clock signal clk and VD composition or logic also are connected to the grid that PMOS manages MP1, and clock signal clk and VDb (inversion signal of VD) composition or logic also are connected to the grid of PMOS pipe MP2 simultaneously.When CLK is a high level, MP1 and MP2 end, and NMOS pipe MN1 conducting if this moment, VD was a high level, makes node SALATCH_N discharge, and it is constant that node SALATCH_P keeps high level.This moment, second level latch was driven by node SALATCH_N and SALATCH_P, and because CLK is a high level, NMOS pipe MN4 and MN5 conducting make that trigger complementary output end Q is a high level, Q
bBe low level.When CLK is the low level while, if input signal VD still keeps high level, the MP1 remain off can not carry out condition presetting to node SALATCH_N; At this moment, for second level latch, because CLK is a low level, MN4 and MN5 end, and the complementary output signal of trigger also can be maintained.When CLK is the low level while, if input signal VD is turned to low level, the MP1 conducting is to SALATCH_N node condition presetting; And when next rising edge clock arrives, node SALATCH_P discharge, node SALATCH_N keeps high level and drives second level latch, makes that trigger complementary output end Q is a low level, Q
nBe high level.The output node SALATCH_N of first order latch and SALATCH_P are connected respectively to two independently and have on the single clock phase latch of same circuits parameter, this method of attachment not only can guarantee when CLK is low level, and the complementary output end of trigger is can the inhibit signal level constant; Simultaneously, can guarantee the complementary output end Q and the Q of SAFF_CP_BRF_EC trigger
nCan realize the rising edge time-delay and the trailing edge time-delay of symmetry.
Essential features of the present invention is: at first, it has reliable synchronous enabled control Enable.Secondly, the condition condition presetting control circuit that the flip-flop circuit employing is controlled by input data signal VD is finished the condition condition presetting process to the circuit internal node, has reduced the power consumption of trigger itself.The condition condition presetting process of first order latch cooperates second level latch, guarantees that circuit is a low level and during not to SALATCH_N or SALATCH_P node condition presetting electricity at CLK, and the complementary output end of trigger is can the inhibit signal level constant.Once more, the output node SALATCH_N of first order latch and SALATCH_P are connected respectively to two independently and have on the single clock phase latch of same circuits parameter, and this method of attachment can guarantee the complementary output end Q and the Q of SAFF_CP_BRF_EC trigger
bCan realize the rising edge time-delay and the trailing edge time-delay of symmetry.In addition, with respect to basic model trigger SAFF_CP, because the SAFF_CP_BRF_EC trigger has removed NMOS pipe MN6, can improve characteristic settling time of circuit greatly, dynamic power consumption also reduces, and circuit structure is simpler simultaneously, has reduced by an extra high-voltage power supply line V
Well(to PMOS pipe MP1, MP2 provides substrate biasing, V
Well＞V
DD), help using and designing of circuit more, increased current potential holding circuit (φ in output stage
2And φ
3Form).
For SAFF_CP_BRF_EC trigger more proposed by the invention performance, use circuit simulation tools HSPICE that two kinds of circuit structures have been carried out the post-simulation comparative analysis with respect to identical function trigger FFEDHD1X in the GSMC15 storehouse.Table 1 is depicted as two kinds of trigger post-simulation dynamic power consumptions and the circuit area data compare.Clock signal input CLK is 100MHz in the emulation of circuit dynamic power consumption, 50% duty ratio square-wave signal (0V-1.5V), and data-signal input D is 20MHz, 50% duty ratio square-wave signal (0V-1.5V).Data-signal has the time-delay of 1ns with respect to clock signal, and the edge width of all input signals all is 0.104ns. " Q load/Qn empty " expression: trigger output Q connects the 20fF capacitive load, and the Qn end is unsettled.Dynamic power consumption and circuit area data unit are respectively microwatt (uW) and micron * micron (um*um).
Table 1 trigger post-simulation dynamic power consumption, circuit area are relatively
| Dynamic power consumption (uW) | Circuit area (um*um) | ||
| ??Q?load/Qn?empty | ??Qn?load/Q?empty | ||
| ??FFEDHD1X | ??6.283 | ??6.313 | ??12.30*4.32 |
| ??SAFF_CP_BRF_EC | ??4.050 | ??4.028 | ??11.76*4.32 |
s
Table 2 is depicted as always the delay time comparison of TotalDelay of two kinds of trigger post-simulations.
As shown in Figure 8: D-CK time-delay vs CK-Q duration curve, increase along with the D-CK time-delay, the time-delay of CK-Q is tending towards a stable value---static time-delay (TstaticDelay), 105% times of the static time-delay of definition is D0, corresponding therewith D-CK time-delay is defined as Tmp, and D0+Tmp is defined as total time-delay (TotalDelay)
Two kinds of flip-flop circuits adopt identical circuit arrangement, and input signal change-over time is 0.05ns, and two outputs of circuit all meet load 20fF.RISE, FALL represent output signal rising edge and output signal trailing edge respectively; Delay data unit is nanosecond (ps).
Table 2 FFEDHD1X Chu Faqi ﹠amp; SAFF_CP_BRF_EC trigger post-simulation always delay time (TotalDelay)
| ??Edge | ??Tmp | ??D0 | ??Total?Delay | |
| ??FFEDHD1X | ??RISE | ??75.7 | ??311 | ??386.7 |
| ??FALL | ??131 | ??315 | ??446 | |
| ??SAFF_CP_BRF_EC | ??RISE | ??163 | ??221.5 | ??384.5 |
| ??FALL | ??192 | ??256 | ??448 |
Table 3 and table 3B are depicted as the relation that the static time-delays of two kinds of trigger post-simulations (TstaticDelay) change with circuit load.Two kinds of flip-flop circuits adopt identical circuit arrangement, and input signal change-over time is 0.104ns, and unit load is 4fF.The SAFF_CP_BRF_EC flip-flop circuit has suitable substantially circuit delay with respect to the FFEDHD1X trigger in the GSMC15 storehouse and the rising edge time-delay is basic identical with the trailing edge time-delay, does not consider the metastable state effect here.TQ and tQ
nRepresent the time-delay of in-phase output end, reversed-phase output respectively; RISE and FALL represent output signal rising edge and output signal trailing edge respectively; Delay data unit is nanosecond (ps).
Table 3A FFEDHD1X static time-delay of trigger post-simulation and load relationship
| Fan-out load/unit load | ??4 | ??8 | ??16 | ??32 | ??64 |
| The hopping edge | ??RISE | ??FALL | ??RISE | ??FALL | ??RISE | ??FALL | ??RISE | ??FALL | ??RISE | ??FALL |
| ??tQ(ns) | ??277 | ??284 | ??351 | ??345 | ??495 | ??449 | ??782 | ??644 | ??1356 | ??1031 |
| ??tQ n(ns) | ??369 | ??348 | ??438 | ??399 | ??580 | ??497 | ??867 | ??690 | ??1440 | ??1077 |
Table 3B SAFF_CP_BRF_EC static time-delay of trigger post-simulation and load relationship
| Fan-out load/unit load | ???????4 | ??????8 | ??????16 | ??????32 | ????????64 | |||||
| The hopping edge | ??RISE | ??FALL | ??RISE | ??FALL | ??RISE | ??FALL | ??RISE | ??FALL | ??RISE | ??FALL |
| ??tQ(ns) | ??201 | ??239 | ??274 | ??287 | ??417 | ??383 | ??704 | ??576 | ??1278 | ??963 |
| ??tQ n(ns) | ??224 | ??268 | ??295 | ??319 | ??442 | ??417 | ??728 | ??610 | ??1302 | ??996 |
Table 4A and table 4B are depicted as two kinds of trigger post-simulation time-delays and the input signal relation of change-over time.Two kinds of flip-flop circuits adopt identical circuit arrangement, and input signal unit is 0.05ns change-over time, and circuit load is 20fF.The SAFF_CP_BRF_EC flip-flop circuit has suitable substantially circuit delay with respect to the FFEDHD1X trigger in the GSMC15 storehouse and the rising edge time-delay is basic identical with the trailing edge time-delay, does not consider the metastable state effect here.TQ and tQ
nRepresent the time-delay of in-phase output end, reversed-phase output respectively; RISE and FALL represent output signal rising edge and output signal trailing edge respectively; Delay data unit is nanosecond (ns).
Table 4A FFEDHD1X trigger post-simulation time-delay and change-over time relation
Circuit load=20fF, the change-over time=0.05ns of unit
| Change-over time input change-over time/unit | ???????1 | ????????5 | ????????10 | ????????15 | ????????20 | |||||
| The hopping edge | ??RISE | ??FALL | ??RISE | ??FALL | ??RISE | ??FALL | ??RISE | ??FALL | ??RISE | ??FALL |
| ??tQ(ns) | ??296 | ??300 | ??334 | ??334 | ??365 | ??371 | ??388 | ??393 | ??408 | ??411 |
| ??tQ n(ns) | ??386 | ??361 | ??415 | ??399 | ??453 | ??431 | ??475 | ??455 | ??496 | ??474 |
Table 4B SAFF_CP_BRF_EC trigger post-simulation time-delay and change-over time relation
| Change-over time input change-over time/unit | ???????1 | ???????5 | ??????10 | ??????15 | ??????20 | |||||
| The hopping edge | ??RISE | ??FALL | ??RISE | ??FALL | ??RISE | ??FALL | ??RISE | ??FALL | ??RISE | ??FALL |
| ??tQ(ns) | ??211 | ??244 | ??242 | ??263 | ??273 | ??281 | ??297 | ??292 | ??311 | ??299 |
| ??tQ n(ns) | ??242 | ??281 | ??270 | ??298 | ??296 | ??313 | ??316 | ??325 | ??329 | ??332 |
Claims (1)
1. synchronous enabled type condition presetting CMOS trigger is characterized in that, described CMOS trigger is the rising edge trigger, contains:
First order latch comprises:
The 1st " or " logical circuit, contain two NMOS pipes, be designated as (MN9) pipe and (MN8) manage; The drain electrode of these two NMOS pipes links to each other, ground connection after substrate links to each other; The source electrode of this MN8 pipe and grid meet input data signal VD; The grid of this MN9 pipe meets input data signal VDb, and this VDb signal is the inversion signal of described VD signal, and the source electrode of this MN9 pipe connects clock signal clk;
The 2nd " or " logical circuit, contain two NMOS pipes, be designated as (MN10) pipe and (MN11) manage; The drain electrode of these two NMOS pipes links to each other, ground connection after substrate links to each other; The source electrode of this MN10 pipe and grid meet input data signal VDb; The grid of this MN11 pipe meets input data signal VD, and the source electrode of this MN11 pipe connects clock signal clk;
1PMOS pipe is designated as (MP1) pipe, described the 1st " or " clock signal clk and input data signal VDb in the logical circuit form " or " logic, and link to each other through the drain electrode of MN9 pipe and the grid of described MP1 pipe; The source electrode of this MP1 pipe with meet supply voltage VDD after substrate links to each other;
2PMOS pipe is designated as (MP2) pipe, described the 2nd " or " clock signal clk and data data in the logical circuit form " or " logic, and link to each other with the grid of described MP2 pipe through the drain electrode of described MN11 pipe; The source electrode of this MP2 pipe with meet supply voltage VDD after substrate links to each other;
3PMOS pipe is designated as (MP3) pipe, the source electrode of this MP3 pipe with meet supply voltage VDD after substrate links to each other;
4PMOS pipe is designated as (MP4) pipe, the source electrode of this MP4 pipe with meet supply voltage VDD after substrate links to each other;
The 4NMOS pipe is designated as (MN4) pipe, forms node SALATCH_N after the grid of the source electrode while of this MN4 pipe and the drain electrode of described MP1 pipe and MP3 pipe, MP4 pipe links to each other; The grid of this MN4 pipe forms node SALATCH_P with grid, the MP4 pipe of described MP3 pipe after linking to each other with the drain electrode of MP2 pipe simultaneously; The substrate ground connection of this MN4 pipe;
The 5NMOS pipe is designated as (MN5) pipe, and the source electrode of this MN5 pipe links to each other with described node SALATCH_P; The grid of this MN5 pipe links to each other with described node SALATCH_N; The substrate ground connection of this MN5 pipe;
The 2NMOS pipe is designated as (MN2) pipe, and the source electrode of this MN2 pipe links to each other with the drain electrode of described MN4 pipe; The substrate ground connection of this MN2 pipe;
The 3NMOS pipe is designated as (MN3) pipe, and the source electrode of this MN3 pipe links to each other with the drain electrode of described MN5; The substrate ground connection of this MN3 pipe;
The 1NMOS pipe is designated as (MN1) pipe, and the source electrode of this MN1 pipe links to each other with the drain electrode of MN3 pipe with described MN2 pipe simultaneously; The grid of this MN1 pipe connects clock signal clk; The substrate ground connection of this MN1 pipe;
The 1st inverter is designated as inverter φ
1, this inverter φ
1Input and the grid of described MN2 pipe link to each other, form the input of input data signal VD; This inverter φ
1Output be the output of an input data signal VDb, this output links to each other with the grid of described MN3 pipe;
Second level latch comprises two single clock phase latch with same electrical mathematic(al) parameter, and this second level latch contains:
5PMOS pipe is designated as (MP0_1) pipe, the source electrode of this MP0_1 pipe with meet supply voltage VDD after substrate links to each other; The grid of this MP0_1 pipe meets described node SALATCH_P;
6PMOS pipe is designated as (MP0_2) pipe, the source electrode of this MP0_2 pipe with meet supply voltage VDD after substrate links to each other; The grid of this MP0_2 pipe meets described node SALATCH_N;
The 6NMOS pipe is designated as (MN1_1) pipe, and the grid of this MN1_1 pipe meets described node SALATCH_P, the substrate ground connection of this MN1_1 pipe;
The 7NMOS pipe is designated as (MN1_2) pipe, and the grid of this MN1_2 pipe meets described node SALATCH_N, the substrate ground connection of this MN1_2 pipe;
2nd, the 3 two inverter is designated as φ respectively
2And φ
3, described two anti-phase joining of inverter: the input of the 2nd inverter with link to each other simultaneously formation node QI again with the drain electrode of described MP0_1 pipe and the source electrode of MN1_1 pipe after the end of the output of the 3rd inverter links to each other; The 2nd inverter φ
2Output again with the 3rd inverter φ
3Input link to each other formation node QNI again with the drain electrode of described MP0_2 pipe and the source electrode of MN1_2 pipe after linking to each other;
The 8NMOS pipe is designated as (MN0_1) pipe, and the drain electrode of this MN0_1 pipe is the back ground connection that links to each other with substrate, and the grid of this MN0_1 pipe connects clock signal clk, and source electrode connects the drain electrode of described MN1_1 pipe;
The 9MOS pipe is designated as (MN0_2) pipe, and the drain electrode of this MN0_2 pipe is the back ground connection that links to each other with substrate, and grid connects clock signal clk, and source electrode connects the drain electrode of described MN1_2 pipe;
The 4th inverter is designated as inverter φ
4, this inverter φ
4Input link to each other with described node QNI, be output as the output Qb of described CMOS trigger;
The 5th inverter is designated as inverter φ
5, this inverter φ
5Input link to each other with described node QI, output signal is the another one output Q of described CMOS trigger;
Synchronous enabled circuit, the output of this circuit latchs it to described first, second two-stage synchronous enabled input signal VD is provided, and described synchronous enabled circuit comprises:
The 0th inverter is designated as inverter φ
0, this inverter φ
0Input link to each other with enable signal E, output signal is the inversion signal EN of enable signal;
The 1CMOS transmission gate contains two PMOS pipes parallel with one another and NMOS pipe, is designated as MPV pipe and MNN pipe successively respectively; Described MPV pipe with meet input data signal D after the source electrode of MNN pipe links to each other; Described MPV pipe and the grid that connects the MN2 pipe of described first order latch after the drain electrode of MNN pipe links to each other; The substrate of described MPV pipe meets supply voltage VDD, the substrate ground connection of MNN pipe;
The 2CMOS transmission gate contains two PMOS pipes parallel with one another and NMOS pipe, is designated as MPV ' pipe and MNN ' pipe respectively; Connect the grid of the MN2 pipe of described first order latch after the drain electrode parallel connection of described MPV ' pipe and MNN ' pipe; Meet the node QNI in the latch of the described second level after the source electrode parallel connection of described MPV ' pipe and MNN ' pipe; Synchronous enabled signal E links to each other with the grid of MPV ' pipe with described MNN pipe simultaneously; Described EN connects the grid of described MPV pipe and MNN ' pipe respectively; The substrate of described MPV ' pipe meets supply voltage VDD, the substrate ground connection of MNN ' pipe.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB200510011905XA CN100364230C (en) | 2005-06-09 | 2005-06-09 | Synchronous enabled type condition presetting CMOS trigger |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB200510011905XA CN100364230C (en) | 2005-06-09 | 2005-06-09 | Synchronous enabled type condition presetting CMOS trigger |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1702963A true CN1702963A (en) | 2005-11-30 |
| CN100364230C CN100364230C (en) | 2008-01-23 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109412581A (en) * | 2017-08-18 | 2019-03-01 | 杭州晶华微电子有限公司 | A kind of clock failure of oscillation detection circuit |
| CN109525222A (en) * | 2018-11-16 | 2019-03-26 | 西安邮电大学 | A kind of single phase clock Double-edge D trigger |
| CN114978152A (en) * | 2022-05-10 | 2022-08-30 | 上海韬润半导体有限公司 | Latch circuit and digital-to-analog converter comprising same |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3230655B2 (en) * | 1996-06-17 | 2001-11-19 | 日本電気株式会社 | Dynamic latch circuit and flip-flop circuit |
| US6198323B1 (en) * | 1999-01-28 | 2001-03-06 | Lucent Technologies Inc. | Flip-flop having gated inverter feedback structure with embedded preset/clear logic |
| GB0013790D0 (en) * | 2000-06-06 | 2000-07-26 | Texas Instruments Ltd | Improvements in or relating to flip-flop design |
| US6777992B2 (en) * | 2002-04-04 | 2004-08-17 | The Regents Of The University Of Michigan | Low-power CMOS flip-flop |
| CN1268057C (en) * | 2002-10-18 | 2006-08-02 | 松下电器产业株式会社 | Flip-flop circuit |
-
2005
- 2005-06-09 CN CNB200510011905XA patent/CN100364230C/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109412581A (en) * | 2017-08-18 | 2019-03-01 | 杭州晶华微电子有限公司 | A kind of clock failure of oscillation detection circuit |
| CN109525222A (en) * | 2018-11-16 | 2019-03-26 | 西安邮电大学 | A kind of single phase clock Double-edge D trigger |
| CN109525222B (en) * | 2018-11-16 | 2022-11-04 | 西安邮电大学 | Double-edge D trigger of single-phase clock |
| CN114978152A (en) * | 2022-05-10 | 2022-08-30 | 上海韬润半导体有限公司 | Latch circuit and digital-to-analog converter comprising same |
| CN114978152B (en) * | 2022-05-10 | 2024-06-21 | 上海韬润半导体有限公司 | Latch circuit and digital-to-analog converter including the same |
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|---|---|
| CN100364230C (en) | 2008-01-23 |
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