CN1212573C - Low-amplitude differential interface circuit for on-chip system asynchronous IP interconnection - Google Patents
Low-amplitude differential interface circuit for on-chip system asynchronous IP interconnection Download PDFInfo
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Abstract
The present invention relates to a low-amplitude differential interface circuit used for the interconnection of asynchronous IP of a system on a chip, which belongs to the technical field of system design on a low power consumption CMOS chip. The present invention is characterized in that the present invention comprises a driver and a receiver, wherein the driver is an interconnection line driver of a sampling differential cascade connection inverter, and the receiver is a differential level triggering latch; the input signal of the latch is input from the sources of the NMOS tubes MN1 and MN2 of the latch, the clock signal of the latch is a local clock signal as a sampling clock for sampling input signals with low amplitude, and the frequency of the sampling clock is optimized to 2 times as the highest frequency of the input signals with the low amplitude; an NAND gate latch for reducing the distortion of the input signal again is coupled with the output end of the latch in cross coupling. The present invention has the advantages of small power consumption, small delay product of the power consumption, simple structure, stable performance in high frequency and high load, convenient use and convenient adjustment.
Description
Technical field
The low amplitude of oscillation difference interface circuit that is used for the asynchronous IP interconnection of SOC (system on a chip) belongs to Low-Power CMOS SOC (system on a chip) (SOC:System-On-Chip) design field, relate in particular to Low-Power CMOS system-on-chip designs technical field, more specifically relate to a kind of interface circuit that is used for each circuit I P intermodule interconnection of chip system based on the interconnection of asynchronous system IP core.
Background technology
Raising along with integrated circuit fabrication process, transistorized physical dimension constantly reduces, can constantly increasing by integrated number of transistors on the unit area, therefore is that the cost that improves the encapsulation of circuit heat dispersion introducing improves constantly, and the stability of circuit also has been subjected to very big influence.Simultaneously, the use widely of battery powered wireless device makes circuit power consumption become an important restrictions of circuit design day by day.Impelling traditional thus is the method for designing integrated circuit of the two dimension of target with area and performance, to being that the Three-dimension Target method for designing changes with low-power consumption, chip area and circuit performance.
The power consumption of integrated circuit source mainly contains dynamic power consumption, quiescent dissipation, short-circuit current power consumption and leakage current power consumption.Wherein dynamic power consumption accounts for major part.Under certain circuit performance constraint, the dynamic power consumption P of circuit node
DynamicIt is this node load capacitor C
L, supply voltage V
DDVoltage swing V with this node
SwingFunction, that is:
Wherein, f is the frequency of operation of circuit, and α is the signal activity.From formula (1), as seen, reduce α, C
L, V
DDAnd V
SwingAll can reduce the dynamic power consumption of circuit.The work of this paper mainly is exactly by reducing V at how
SwingReduce power consumption.
Integrated circuit (IC) design has entered the deep-submicron stage, and the ratio that interconnecting line power consumption accounts in the circuit overall power is increasing, is mainly reflected in the power consumption of the system that is operated in heavy load, high signal frequency and clock network.Dake Liu research points out that interconnection line and interconnection line driver account for 20% and 65% of total system power consumption respectively.Especially the design of micro-system chip (SOC:system-on-chip) has had requirements at the higher level to power consumption, for shortening the design production cycle, a large amount of reusable IP kernel (Reusable Intellectual Property Cores) and some connection communication modules are applied in the design process of SOC.Therefore, the huge energy of connection communication consumption makes the reduction interconnecting line power consumption obtain the attention of industry member and academia day by day between the IP kernel.
Reducing interconnecting line power consumption mainly can be by reducing the voltage swing V on the interconnection line
SwingMethod realize the key of this technology and difficult point are how to discern and recover low amplitude of oscillation signal.Design low amplitude of oscillation interconnection line interface circuit exactly specific to circuit engineering, at the transmitting terminal of interface circuit the full swing digital signal conversion is low amplitude of oscillation signal, low amplitude of oscillation signal is resumed again at receiving end through interconnection line transmission back and is the full swing signal.At present, the low amplitude of oscillation interconnection line interface circuit that has existed and used mainly contains traditional level shifting circuit (CLC:Conventional Level Converter), and difference is hanged down amplitude of oscillation interface circuit (DIFF:Differential Low-Swing Interface) and the low amplitude of oscillation interface circuit (PDIFF:PeusdodifferentialLow-Swing Interface) of pseudo-differential etc.For power consumption and performance that can correctly more various low amplitude of oscillation interface circuit structures, we set up a basic model to the low amplitude of oscillation interconnection line interface circuit of difference, as shown in Figure 1.Hereinafter breadboardin and analysis more all will be based upon on this model based.
Among Fig. 1 (a), full swing signal VIN becomes the low amplitude of oscillation signal of difference by interconnection line driver (Driver) to be transmitted on interconnection line.At an other end of interconnection line, receiver (Receiver) recovers to become difference full swing signal VOUT and VOUT_B to the low amplitude of oscillation signal of difference.Fig. 1 (b) is the T type equivalent-circuit model of interconnection line, and wherein R is an interconnection line T type equivalent resistance, C
LoadIt is the equivalent capacity load.
Fig. 2 is the simplest a kind of low amplitude of oscillation interface circuit, traditional level shifting circuit CLC (Conventional LevelConverter).The CLC interface circuit needs an extra reference voltage V
Ref(＜VDD) drives interconnection line, and making the amplitude of oscillation on the interconnection line is 0 to V
RefThe deficiency of this interface circuit is that noise robustness is poor, when significantly impulse disturbances is imported BUFF, may cause the receiver cisco unity malfunction; Simultaneously because the BUFF input signal is added in the metal-oxide-semiconductor grid, when interconnection line signal swing during less than the metal-oxide-semiconductor threshold voltage, BUFF can operate as normal yet.Above reason has limited the Min. that signal swing can reduce on the interconnection line.
Differential signal has good common-mode signal rejection, so noise robustness is very strong.Therefore on interconnection line, transmit differential signal and make that further reducing signal swing becomes possibility.Fig. 3 and Fig. 4 are respectively low amplitude of oscillation interface circuit DIFF (the Differential Low-swing Interface of difference, see document T.Burd.Energy efficient processor system design.Ph.D.dissertation, Univ.Calif., Berkeley, 2001) and low amplitude of oscillation interface circuit PDIFF (the PseudodifferentialLow-swing Interface of pseudo-differential, see document Zhang H.et al.Low-swing on-chip signaling techniques:effectiveness and robustness.IEEE Trans.VLSI Syst, 2000,8:264-272).DIFF and PDIFF can reduce power consumption to a certain extent, but the receiver architecture of the two is all very complicated; Simultaneously, because DIFF and PDIFF partly use global clock signal CLK to reduce the quiescent current power consumption at receiver, because the stray capacitance of global clock network is very big, therefore potential clock system power consumption is bigger, has limited the reduction of these two kinds of interface circuit oneself power consumptions.In addition, because transmitting each (bit) signal, PDIFF only needs an interconnection line, so can save more chip area than DIFF.But PDIFF is not a difference interface circuit truly, and the reduction of signal swing is subject to the threshold voltage of metal-oxide-semiconductor equally, and noise robustness is poor, so the energy force rate DIFF of the low amplitude of oscillation signal of PDIFF recovery is poor.
Summary of the invention
The objective of the invention is to propose the low amplitude of oscillation difference interface circuit DLTL of the asynchronous IP interconnection of a kind of SOC of being used for.
The low amplitude of oscillation difference interface circuit that is used for the asynchronous IP interconnection of SOC (system on a chip), contain the driver of series connection successively, interconnection line and receiver, it is characterized in that, it contains: driver is the interconnection line driver that adopts the differential type cascaded inverters, receiver is that differential level triggers latch, the input signal of this latch is from the source electrode input of its NMOS pipe MN1 and MN2, described MN1 pipe and meet the clock signal C lk of described differential level triggering latch after the grid of MN2 pipe links to each other, the clock signal C lk of this latch is a local clock signal, and Clk is 2 times that amplitude of oscillation signal highest frequency is hanged down in input as sampling clock to importing low amplitude of oscillation signal sampling and its frequency optimization.Described differential level triggers the output terminal cross-couplings of latch and a Sheffer stroke gate formula latch that is used for further reducing the input signal distortion.
Evidence: it is minimum that the present invention has power consumption, and the power consumption time-delay is actively little, and characteristics are easily debugged in stable performance under the high frequency heavy load situation, use, and structure is also very simple.
Description of drawings
Fig. 1. the basic model of interconnection line interface circuit
(identifier declaration) VIN: interconnection line interface circuit full swing input signal
VOUT, VOUT_B: interconnection line interface circuit full swing differential output signal
CLoad: interconnection line equivalent capacity load
R: interconnection line equivalent resistance load
Driver, From_Driver: the interconnection line driver is connected to the interconnection line drive side
Receiver, To_Receiver: the interconnection line receiver is connected to the interconnection line receiver end
Fig. 2. level shifting circuit CLC
(identifier declaration) and Fig. 1. in identical sign identical meaning is arranged
VDD: supply voltage
V
Ref: the additional reference supply voltage
BUFF: receiver end phase inverter
Fig. 3. difference is hanged down amplitude of oscillation interface circuit DIFF
(identifier declaration) and Fig. 1. and Fig. 2. in identical sign identical meaning is arranged
Clk: clock signal
Fig. 4. pseudo-differential is hanged down amplitude of oscillation interface circuit PDIFF
(identifier declaration) and Fig. 1., Fig. 2. and Fig. 3. in identical sign identical meaning is arranged
GND: ground connection
Fig. 5. adopt differential level to trigger the low amplitude of oscillation interface circuit DLTL of difference of latch structure
(identifier declaration) and Fig. 1., Fig. 2. and Fig. 3. in identical sign identical meaning is arranged
D1, D2: difference interconnection line driver
MN1, MN2, MP1, MP2: differential level latched flip flop
Fig. 6. power consumption and load relationship (300MHz signal frequency)
(identifier declaration) square: the corresponding curve of CMOS interconnection line interface circuit that does not adopt low amplitude of oscillation technology
Last triangle: the curve of DLTL interconnection line interface circuit correspondence
Following triangle: the curve of CLC interconnection line interface circuit correspondence
Circular: the curve of DIFF interconnection line interface circuit correspondence
Rhombus: the curve of PDIFF interconnection line interface circuit correspondence
Fig. 7. the long-pending and load relationship (300MHz signal frequency) of power consumption time-delay
(identifier declaration) and Fig. 6. in identical sign identical meaning is arranged
Fig. 8. power consumption and frequency input signal relation (1cm Metal1 interconnection line)
(identifier declaration) and Fig. 6. in identical sign identical meaning is arranged
Fig. 9. the long-pending and frequency input signal relation (1cm Metal1 interconnection line) of power consumption time-delay
(identifier declaration) and Fig. 6. in identical sign identical meaning is arranged
Figure 10 .DLTL is low, and amplitude of oscillation interface circuit is operated in 1cm Metal1 Interconnect Load, the analog waveform of 500MHz frequency input signal:
(a) input signal;
(b) output signal;
(c) 50mV amplitude of oscillation signal on the interconnection line
Embodiment
For overcoming the defective of low amplitude of oscillation difference interface circuit structure C LC, DIFF and PDIFF: promptly above-mentioned various interface circuit exist complex structure in varying degrees and be not suitable for the signal frequency height, situation such as load is big and signal swing is minimum, thereby limited the further reduction of these several interface circuit power consumptions.In order further to reduce interconnecting line power consumption, we propose a kind of low amplitude of oscillation interface circuit structure DLTL of difference brand-new, that can be used for the asynchronous IP interconnection of SOC, as shown in Figure 5.This low amplitude of oscillation difference interface circuit has low in energy consumption, and the power consumption time-delay is long-pending little, and advantage is easily debugged in stable performance and simple in structure under the high frequency heavy load situation.
The technical scheme that patent of the present invention solves its technical matters is:, circuit structure as shown in Figure 5, full swing signal VIN becomes the low amplitude of oscillation signal of difference through the interconnection line driving circuit, the signal swing on the interconnection line from 0 to reference voltage V
RefThe differential level that adopts acceptor circuit triggers latch DLTL (Differential Level-triggered Latch) low amplitude of oscillation interconnection line signal is reverted to the full swing signal.Differential level triggers latch and has simple circuit configuration, and (MP1 MP2) constitutes for MN1, MN2 by four metal-oxide-semiconductors.The low amplitude of oscillation signal of interconnection line difference is from the source electrode input of NMOS pipe MN1 and MN2, eliminated like this when grid is imported because the existence of metal-oxide-semiconductor threshold voltage and the restriction of the minimum amplitude of oscillation of signal, therefore can recover the signal of the littler amplitude of oscillation, we can be reduced to 50mV with voltage swing under TSMC 0.18-μ m technology.Clock signal clk on MN1 and the MN2 grid is the low amplitude of oscillation signal sampling clock of receiver input.According to the Nyquist sampling thheorem, requiring clock signal frequency is the twice of the low amplitude of oscillation signal highest frequency of input at least, and clock frequency is high more, and the distortion that then recovers the back signal is more little, but this can make the power consumption of clock part become big.In our work, weighed the distortion level of interface circuit output signal and the selection of clock frequency, clock frequency is controlled to just the low amplitude of oscillation signal highest frequency of input of twice.PMOS pipe MP1 and MP2 form positive-feedback circuit, and low amplitude of oscillation signal is reverted to the full swing signal, the amplitude of oscillation from 0 to VDD.The cross-linked Sheffer stroke gate of interface circuit output terminal is as latch, and effect is the distortion that further reduces output signal.
Essential features of the present invention is: adopt differential technique can reduce noise greatly, thereby can reduce the interconnection line signal swing, finally reduce interconnecting line power consumption.Receiver partly adopts differential level to trigger latch structure simultaneously, and input signal is from MN1, and the input of the source electrode of MN2 has been eliminated MOSFET grid level threshold voltage to further reducing the restriction of interconnection line signal swing.The clock signal clk of receiver part to importing low amplitude of oscillation signal sampling, requires its frequency to be at least 2 times of frequency input signal, to guarantee undistorted restoring signal as sampling clock.
The beneficial effect of patent of the present invention is: compared with the prior art, it is minimum that the present invention has power consumption, and the power consumption time-delay is actively little, stable performance and simple in structure under the high frequency heavy load situation, and use debugging also very simple and convenient.
In order to simulate comparison and to analyze the power consumption and the performance of various low amplitude of oscillation interconnection line interface circuits, basic model according to low amplitude of oscillation interconnection line interface circuit among Fig. 1, we adopt TSMC 0.18-μ m1.8-V standard digital CMOS technology library, use circuit simulation software HSPICE that various circuit structures are simulated; Interconnection line all is positioned at the Metal1 layer, and length is 1cm, and its equivalent electrical circuit is shown in Fig. 1 (b), and CLoad=2.12pF, R=150 Ω; Adopt cascaded inverters as the interconnection line driver.Simultaneously, we have also simulated power consumption under the different Interconnect Load conditions and power consumption time-delay long-pending (as Fig. 6, shown in Figure 7) when frequency input signal is 300MHz, and length is power consumption and the power consumption time-delay long-pending (as Fig. 8, shown in Figure 9) of interconnection line under the varying input signal frequency of 1cm.Because the time-delay of the driver of total interface circuit equates that therefore, the time-delay of interconnection line and receiver part is all only calculated in the time-delay in all charts.Data in the table 1 are listed when frequency input signal is 300MHz and 500MHz, and under guaranteeing that output square-wave signal Duty Cycle Distortion is less than 10% situation, the minimum signal amplitude of oscillation that various circuit structures can reach, power consumption and power consumption time-delay are long-pending.
The low amplitude of oscillation interface circuit performance of table 1 is (CLoad=2.12pF, R=150 Ω) relatively
| Circuit structure | The minimum signal amplitude of oscillation (V) | Circuit complexity * | 300MHz | 500MHz |
| Power consumption time-delay long-pending (mW) (pJ) | Power consumption time-delay long-pending (mW) (pJ) | |||
| CMOS ** 1.800 - DLTL 0.050 4 CLC 0.800 6 DIFF 0.200 12 PDIFF 0.500 11 | 7.23 3.44 0.97 0.86 6.37 3.74 6.02 2.27 5.86 2.84 | 11.72 5.64 1.57 1.39 9.72 5.71 10.10 3.82 8.95 4.34 | ||
*Circuit complexity only compares the number of transistors that the receiver part does not comprise output latch
*Do not adopt the asynchronous IP interconnect interface circuit of low amplitude of oscillation technology
Can see when the DLTL interface circuit changes along with Interconnect Load or frequency input signal, having minimum power consumption characteristics from Fig. 6 and Fig. 8 always.By Fig. 7 and Fig. 9 as can be known, when the DLTL interface circuit changes along with Interconnect Load or frequency input signal, also has the minimum long-pending characteristic of power consumption time-delay.Can also find that from Fig. 6-Fig. 9 when Interconnect Load or frequency input signal variation, DLTL is low, and amplitude of oscillation interface circuit has the mildest family curve, this shows that this interface circuit has very strong adaptability and stability.
Figure 10 be the low amplitude of oscillation interface circuit of the DLTL that proposes of this paper to be operated in length be that Metal1 layer Interconnect Load, the frequency input signal of 1cm is the voltage waveform under the 500MHz condition, wherein the signal swing on the interconnection line is 50mV.From Figure 10 as seen, though the interconnection line signal swing is by greatly degree reduction, but DLTL interface circuit distinct issues are that signal lag is excessive, but for asynchronous system, driver and receiver can be with different clock signals, and they can be nonsynchronous, and this also makes application of the low amplitude of oscillation interface circuit of DLTL become possibility.Simultaneously, with respect to the global clock that adopts in DIFF and the PDIFF interface circuit, the DLTL interface circuit adopts local clock, has also reduced the power consumption of high frequency clock load to a certain extent.
Claims (2)
1. the low amplitude of oscillation difference interface circuit that is used for the asynchronous IP interconnection of SOC (system on a chip), contain the driver of series connection successively, interconnection line and receiver, it is characterized in that, it contains: driver is the interconnection line driver that adopts the differential type cascaded inverters, receiver is that differential level triggers latch, the input signal of this latch is from the source electrode input of its NMOS pipe MN1 and MN2, described MN1 pipe and meet the clock signal C lk of described differential level triggering latch after the grid of MN2 pipe links to each other, the clock signal C lk of this latch is a local clock signal, and Clk is 2 times that amplitude of oscillation signal highest frequency is hanged down in input as sampling clock to importing low amplitude of oscillation signal sampling and its frequency optimization.
2. the low amplitude of oscillation difference interface circuit that is used for the asynchronous IP interconnection of SOC (system on a chip) according to claim 1, it is characterized in that: described differential level triggers the output terminal cross-couplings of latch and a Sheffer stroke gate formula latch that is used for further reducing the input signal distortion.
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| CN102684677B (en) * | 2012-06-01 | 2014-04-23 | 北京大学 | Delay-based dual-rail precharge logic input converter |
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