CN1300940C - High accuracy RC oscillator with optional frequency - Google Patents
High accuracy RC oscillator with optional frequency Download PDFInfo
- Publication number
- CN1300940C CN1300940C CNB2005100385823A CN200510038582A CN1300940C CN 1300940 C CN1300940 C CN 1300940C CN B2005100385823 A CNB2005100385823 A CN B2005100385823A CN 200510038582 A CN200510038582 A CN 200510038582A CN 1300940 C CN1300940 C CN 1300940C
- Authority
- CN
- China
- Prior art keywords
- inverter
- pipe
- adjustable
- nmos
- connects
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
The present invention relates to a selectable RC oscillator having highly accurate frequency, which comprises an externally connected resistor [R], a capacitor [C] and a discharging NMOS tube [N1], wherein the externally connected resistor [R] and the capacitor [C] form a charging circuit between a power supply [VDD] and a ground wire [VCC], the drain electrode [D] of the discharging NMOS tube [N1] is connected with the voltage end [V1] of the capacitor [C], a source electrode [S] is connected with the ground wire [VCC], and a grid electrode [G] is connected with the output end [V2] of the oscillator. The present invention is characterized in that the oscillator also comprises four phase inverters [from INV1 to INV4], a phase inverter [INV5] or an NAND gate [ND3], two NAND gates [ND1, ND2] and two threshold-adjustable phase inverters [SPINV1, SPINV2]. Compared with the prior art, the present invention has the following advantages of stabile oscillation frequency without change following the change of voltage, simple frequency adjusting principle, easy debugging, wide selectable ranges of the oscillation period of the oscillator and wide ranges of application.
Description
Technical field
The present invention relates to the MOS digital integrated circuit, be specifically related to a kind of high accuracy RC oscillator with optional frequency.
Background technology
The RC oscillator is resistance-capacitance oscillator (R: resistance; C: electric capacity).Existing common RC oscillator mainly is made up of resistance, electric capacity, inverter and discharge metal-oxide-semiconductor etc., and as shown in Figure 1, wherein, resistance R is an outer meeting resistance, and capacitor C, inverter INV1～INV4 and discharge NMOS pipe N1 are made of integrated circuit.
The operation principle of Fig. 1 circuit is as follows: when the voltage of V1 is lower than threshold voltage (or claiming overturn point) Vtinv1 of inverter INV1, INV1 is output as high level, this level is through inverter IINV2, INV3 and INV4 time-delay, oppositely, the signal V2 that exports after the shaping is low level.At this moment, discharge NMOS pipe N1 turn-offs, and VDD charges to capacitor C by resistance R, and the V1 current potential is risen.When V1 rose to a little more than Vtinv1, the upset of the output level of inverter INV1 was for low level, through inverter INV2, INV3, INV4 time-delay, oppositely, export high level after the shaping, promptly V2 becomes high level, thereby make discharge NMOS pipe N1 conducting, capacitor C is discharged rapidly by N1.V1 is dropped rapidly to Vtinv1 immediately and continues and descends fast, and the output switching activity of inverter INV1 is a high level, and this signal is through INV2, INV3, and INV4 time-delay, oppositely, become low level after the shaping, promptly V2 becomes low level, thereby N1 discharge NMOS pipe is turn-offed.So move in circles, just formed the RC vibration.The output waveform V2 that discharges and recharges waveform and RC oscillator of RC tie point V1 as shown in Figure 2.
Yet, the shortcoming that above-mentioned RC oscillator exists is: (1) poor stability, being frequency of oscillation produces bigger drift with the variation of vdd voltage, its reason is: after the threshold voltage of outer meeting resistance R and inverter INV1 is determined, the variation of vdd voltage brings the difference in capacitor C charging interval, and frequency of oscillation is changed.(2) cycle of oscillation, adjustability was poor, and promptly ordinary circumstance cycle of oscillation is a fixed value, but from the integrated circuit (IC) design angle, when requiring cycle of oscillation longer, must strengthen capacitance.The electric capacity of chip internal is generally made for pole plate by polycrystalline (POLY) or metal (METAL) etc., does big capacitance and will take bigger area, thereby increased the processing cost of chip.If attempting increases cycle of oscillation by increasing the outer meeting resistance value, then the frequency stability of oscillator can be affected again.
If the INV1 with among schmitt inverter replacement Fig. 1 can address the above problem (2).This is because schmitt inverter has two overturn points: import from low to high, export overturn point Vt1 from high to low; Input from high to low, from low to high overturn point Vt2 of output.Clearly, increase the difference between Vt1 and the Vt2, the cycle of oscillation that just can increase the RC oscillator.Though solved problem (2) like this, problem (1) still can not get solving, in any case change the size of each pipe in the circuit, all is difficult to obtain ideal results.Improve the threshold voltage of INV1, also can prolong cycle of oscillation, but still can't resolve problem (1).
Summary of the invention
The invention provides a kind of high accuracy RC oscillator with optional frequency, its objective is and when widening the RC oscillator optional scope of cycle of oscillation, to improve the stability of RC oscillator, to overcome the problem that above-mentioned RC oscillator exists.
For achieving the above object, first kind of technical scheme that the present invention adopts is: a kind of high accuracy RC oscillator with optional frequency comprises outer meeting resistance R, capacitor C, discharge the one NMOS pipe N1, four inverter INV1～INV4 of first to fourth, three NAND gate ND1～ND3 of first to the 3rd and first to second two adjustable threshold value inverter SPINV1, SPINV2;
Outer meeting resistance R and capacitor C constitute the serial connection charge loop between power vd D and ground wire VSS, wherein, and the outer meeting resistance R first termination power VDD, first end of the second termination capacitor C, the second termination ground wire VSS of capacitor C; The NMOS that discharges pipe N1 drain D meets the first end V1 of capacitor C, source S earth connection VSS, and grid G meets oscillator output end V2;
First threshold is adjustable inverter SPINV1 is made up of the 3rd to the 5th three PMOS pipe P3～P5 and the 5th NMOS pipe N5, it is in parallel after the 4th PMOS manages P4 and the 5th PMOS pipe P5 connects with the 3rd PMOS pipe P3, the source S of the 3rd PMOS pipe P3 and the 4th PMOS pipe P4 meets power vd D, the drain D of the 4th PMOS pipe P4 connects the source S of the 5th PMOS pipe, the drain D of the 3rd PMOS pipe P3 and the 5th PMOS pipe P5 connects the drain D of the 5th NMOS pipe N5, the source S earth connection VSS of the 5th NMOS pipe N5; The grid G of the 5th PMOS pipe P5 is as the selecting side frequently that shakes of the adjustable inverter SPINV1 of first threshold, the grid G parallel connection of the 3rd PMOS pipe P3, the 4th PMOS pipe P4 and the 5th NMOS pipe N5 is as the input of the adjustable inverter SPINV1 of first threshold, and the drain D of the 5th NMOS pipe N5 picks out the output as the adjustable inverter SPINV1 of first threshold;
The second adjustable threshold value inverter SPINV2 is made up of second to the 4th three NMOS pipe N2～N4 and the 6th PMOS pipe P6, it is in parallel after the 3rd NMOS manages N3 and the 4th NMOS pipe N4 connects with the 2nd NMOS pipe N2, the source S earth connection VSS of the 2nd NMOS pipe N2 and the 4th NMOS pipe N4, the source S of the 3rd NMOS pipe N3 connects the drain D of the 4th NMOS pipe N4, the drain D of the 2nd NMOS pipe N2 and the 3rd NMOS pipe N3 connects the drain D of the 6th PMOS pipe P6, and the source S of the 6th PMOS pipe P6 meets power vd D; The grid G of the 3rd NMOS pipe N3 is as the selecting side frequently that shakes of the second adjustable threshold value inverter SPINV2, the grid G parallel connection of the 2nd NMOS pipe N2, the 4th NMOS pipe N4 and the 6th PMOS pipe P6 is as the input of the second adjustable threshold value inverter SPINV2, and the drain D of the 6th PMOS pipe P6 picks out the output as the second adjustable threshold value inverter SPINV2;
Annexation between above-mentioned each logic element: the first end V1 of capacitor C is respectively with first, the second two adjustable threshold value inverter SPINV1, the input of SPINV2 connects, shake and select signal SEL one tunnel to connect the selecting side frequently that shakes of the second adjustable threshold value inverter SPINV2 frequently, another road first inverter INV1 connects the selecting side frequently that shakes of the adjustable inverter SPINV1 of first threshold, the input of the output termination first NAND gate ND1 of first threshold is adjustable inverter SPINV1, the output of the second adjustable threshold value inverter SPINV2 connects the input of the second NAND gate ND2 behind the second inverter INV2, the output of another input termination second NAND gate ND2 of the first NAND gate ND1, the output of another input termination first NAND gate ND1 of the second NAND gate ND2, the output of the second NAND gate ND2 connects the input of the 3rd NAND gate ND3 through the 3rd inverter INV3, another input termination enable signal ENABLE of the 3rd NAND gate ND3, the output of the 3rd NAND gate ND3 meets oscillator output end V2 through the 4th inverter INV4;
The threshold voltage vt m of three inverter INV2～INV4 of described second to the 4th and three NAND gate ND1～ND3 of first to the 3rd all is arranged on same theory design load (its error only is the technology manufacture deviation); First, second two adjustable threshold value inverter SPINV1, SPINV2 correspondences are shaken and are frequently selected signal SEL " 0 " with " 1 " two states two different threshold voltages to be arranged respectively, be that the adjustable inverter SPINV1 of first threshold has Vtp0 and Vtp1, when SEL=" 0 ", P5 turn-offs, and the threshold voltage of first threshold is adjustable inverter SPINV1 is Vtp0; When SEL=" 1 ", the P5 conducting, the threshold voltage of first threshold is adjustable inverter SPINV1 is Vtp1, obviously, Vtp0＜Vtp1.Equally, the second adjustable threshold value inverter SPINV2 has Vtn0 and Vtn1, and when SEL=" 0 ", N3 turn-offs, and the threshold voltage of the second adjustable threshold value inverter SPINV2 is Vtn0; When SEL=" 1 ", the N3 conducting, the threshold voltage of the second adjustable threshold value inverter SPINV2 is Vtn1, and Vtn0＞Vtn1; Satisfy following relation between described Vtp0, Vtp1, Vtn0, Vtn1 and the Vtm:
Vtp1＞Vtp0＞Vtm＞Vtn0＞Vtn1。
For achieving the above object, second kind of technical scheme that the present invention adopts is: a kind of high accuracy RC oscillator with optional frequency comprises outer meeting resistance R, capacitor C, discharge the one NMOS pipe N1, five inverter INV1～INV5 of first to the 5th, two NAND gate ND1～ND2 of first to second and first to second two adjustable threshold value inverter SPINV1, SPINV2;
Outer meeting resistance R and capacitor C constitute the serial connection charge loop between power vd D and ground wire VSS, wherein, and the outer meeting resistance R first termination power VDD, first end of the second termination capacitor C, the second termination ground wire VSS of capacitor C; The NMOS that discharges pipe N1 drain D meets the first end V1 of capacitor C, source S earth connection VSS, and grid G meets oscillator output end V2;
First threshold is adjustable inverter SPINV1 is made up of the 3rd to the 5th three PMOS pipe P3～P5 and the 5th NMOS pipe N5, it is in parallel after the 4th PMOS manages P4 and the 5th PMOS pipe P5 connects with the 3rd PMOS pipe P3, the source S of the 3rd PMOS pipe P3 and the 4th PMOS pipe P4 meets power vd D, the drain D of the 4th PMOS pipe P4 connects the source S of the 5th PMOS pipe, the drain D of the 3rd PMOS pipe P3 and the 5th PMOS pipe P5 connects the drain D of the 5th NMOS pipe N5, the source S earth connection VSS of the 5th NMOS pipe N5; The grid G of the 5th PMOS pipe P5 is as the selecting side frequently that shakes of the adjustable inverter SPINV1 of first threshold, the grid G parallel connection of the 3rd PMOS pipe P3, the 4th PMOS pipe P4 and the 5th NMOS pipe N5 is as the input of the adjustable inverter SPINV1 of first threshold, and the drain D of the 5th NMOS pipe N5 picks out the output as the adjustable inverter SPINV1 of first threshold;
The second adjustable threshold value inverter SPINV2 is made up of second to the 4th three NMOS pipe N2～N4 and the 6th PMOS pipe P6, it is in parallel after the 3rd NMOS manages N3 and the 4th NMOS pipe N4 connects with the 2nd NMOS pipe N2, the source S earth connection VSS of the 2nd NMOS pipe N2 and the 4th NMOS pipe N4, the source S of the 3rd NMOS pipe N3 connects the drain D of the 4th NMOS pipe N4, the drain D of the 2nd NMOS pipe N2 and the 3rd NMOS pipe N3 connects the drain D of the 6th PMOS pipe P6, and the source S of the 6th PMOS pipe P6 meets power vd D; The grid G of the 3rd NMOS pipe N3 is as the selecting side frequently that shakes of the second adjustable threshold value inverter SPINV2, the grid G parallel connection of the 2nd NMOS pipe N2, the 4th NMOS pipe N4 and the 6th PMOS pipe P6 is as the input of the second adjustable threshold value inverter SPINV2, and the drain D of the 6th PMOS pipe P6 picks out the output as the second adjustable threshold value inverter SPINV2;
Annexation between above-mentioned each logic element: the first end V1 of capacitor C is respectively with first, the second two adjustable threshold value inverter SPINV1, the input of SPINV2 connects, shake and select signal SEL one tunnel to connect the selecting side frequently that shakes of the second adjustable threshold value inverter SPINV2 frequently, another road first inverter INV1 connects the selecting side frequently that shakes of the adjustable inverter SPINV1 of first threshold, the input of the output termination first NAND gate ND1 of first threshold is adjustable inverter SPINV1, the output of the second adjustable threshold value inverter SPINV2 connects the input of the second NAND gate ND2 behind the second inverter INV2, the output of another input termination second NAND gate ND2 of the first NAND gate ND1, the output of another input termination first NAND gate ND1 of the second NAND gate ND2, the output of the second NAND gate ND2 is through the 3rd inverter INV3, the 5th inverter INV5 and the 4th inverter INV4 series connection oscillator output end V2;
Described second to the 5th four inverter INV2～INV5 and the threshold voltage vt m of first, second two NAND gate ND1～ND2 all are arranged on the same theory design load; First, second two adjustable threshold value inverter SPINV1, SPINV2 correspondences are shaken and are frequently selected signal SEL " 0 " with " 1 " two states two different threshold voltages to be arranged respectively, be that the adjustable inverter SPINV1 of first threshold has Vtp0 and Vtp1, the second adjustable threshold value inverter SPINV2 has Vtn0 and Vtn1, and Vtp0＜Vtp1, Vtn0＞Vtn1; Satisfy following relation between described Vtp0, Vtp1, Vtn0, Vtn1 and the Vtm:
Vtp1＞Vtp0＞Vtm＞Vtn0＞Vtn1。
Related content in above-mentioned first and second technical schemes is explained as follows:
1, in above-mentioned first and second scheme, in order further to improve the stability of frequency of oscillation, can be in the serial connection charge loop of outer meeting resistance R and capacitor C formation, seal in two first, second PMOS pipe P1, P2 that are connected in parallel, the drain D of first, second two PMOS pipes P1, P2 is in parallel with drain D, and source S is in parallel with source S, and string is between outer meeting resistance R and capacitor C, the grid G earth connection VSS of the one PMOS pipe P1, the grid G of the 2nd PMOS pipe P2 connects to shake selects signal SEL frequently.
2, the difference of the above-mentioned alternative plan and first scheme is: replace the 3rd NAND gate ND3 with the 5th inverter INV5, represent that respectively control has two kinds of situations to oscillator, first kind is to adopt the 3rd NAND gate ND3, and utilize vibration enable signal ENABLE to come control generator to enable and two kinds of operating states of dormancy, as shown in Figure 3; Second kind is directly to adopt the 5th inverter INV5, and in this case, oscillator is in running order always, as shown in Figure 4.In actual applications, two kinds of situations adopt one of them to get final product more than.
Operation principle of the present invention is: RC oscillator shown in Figure 3 has high and low two kinds of optional different oscillation frequency bands, can select wherein arbitrary working frequency range by the SEL signal.When needs length cycle of oscillation, then should make SEL=" 1 " (high level); Otherwise, then make SEL=" 0 " (low level).Enable signal ENABLE among the figure be used for control generator whether allow the vibration.When ENABLE=" 0 " (low level), ND3 exports high level, the INV4 output low level, and promptly V2 is a low level, and N1 turn-offs, and the RC oscillator is forbidden vibration.When ENABLE=" 1 " (high level), NAND gate ND3 is opened, and circuit allows vibration.
When ENABLE=" 1 ", during SEL=" 0 ", circuit allows vibration, the P2 conducting, and P5 and N3 turn-off, and the threshold voltage of SPINV1 is Vtp0, and the threshold voltage of SPINV2 is Vtn0.When V1 is lower than Vtn0, SPINV2 output high level, the INV2 output low level, ND2 exports high level, this moment is because the output of SPINV1 is high level, thus the ND1 output low level, thus the reliable interlocking of ND2 and ND1, and then cause INV3 to be output as low level, ND3 is output as high level, and INV4 is output as low level, and promptly V2 is a low level.At this moment, N1 turn-offs, and VDD is by outer meeting resistance R, and compensation PMOS pipe P1 and P2 charge to capacitor C, and V1 rises.When V1 rises to Vtp0 and continue to rise when making the SPINV1 output low level, ND1 exports high level.At this moment because the output of INV2 becomes high level already, so the ND2 output low level and with the reliable interlocking of ND1, INV3 exports high level, the ND3 output low level, V2 becomes high level, the N1 conducting, capacitor C is discharged by N1.Because charging current is far smaller than discharging current, so V1 descends rapidly.Below V1 reduces to Vtn0 and when making SPINV2 output high level, INV2 output low level, and then make V2 become low level, N1 turn-offs, and VDD is by outer meeting resistance R, and P1 and P2 be once more to the capacitor C charging, the V1 rising ... so constantly circulation forms the RC vibration.
When SEL=" 1 ", the operation principle of RC oscillator is the same substantially.Main difference is, when SEL=" 1 ", P2 turn-offs, P5 and N3 conducting, and the threshold voltage of SPINV1 and SPINV2 is respectively Vtp1 and Vtn1.Obviously, because the difference between Vtp1 and the Vtn1 is bigger than the difference between Vtp0 and the Vtn0, so under identical RC value and condition of work, when SEL=" 1 ", it is longer that RC discharges and recharges the time, promptly RC grows (frequency is lower) cycle of oscillation; When SEL=" 0 ", it is shorter that RC discharges and recharges the time, and promptly RC lacks (frequency is higher) cycle of oscillation.
In the RC charge circuit, according to needed cycle of oscillation and different outer meeting resistance values, seal in PMOS pipe (P1 with corresponding L/W ratio, P2), its objective is the linear work district of selecting the RC charging curve, promptly change the characteristic of charging curve, make circuit working, thereby improve the stability of RC oscillator in the zone that influenced by change in voltage.The L/W ratio of P1 is bigger, and the L/W ratio of P2 is less.When the needs charging interval is long, SEL=" 1 ", P2 disconnects, and has only P1 to work, because of P1 is weak, resistance is bigger, so charging is slower.When the needs charging interval in short-term, P2 and P1 conducting in parallel, its resistance is less, so charging comparatively fast.Therefore the present invention can in the RC charging and discharging circuit, seal in the PMOS pipe with corresponding L/W ratio, to improve the frequency of oscillation stability according to different outer meeting resistances.
Because the technique scheme utilization, the present invention and background technology relatively have following advantage: frequency of oscillation is stable, and the variation with voltage changes hardly.The frequency adjustment principle is simple, is easy to debugging.The optional wide ranges of the cycle of oscillation of oscillator, applied widely.
Simulation result shows that (ask for an interview table 1 to table 6, data adopt the HSPICE circuit simulation tools to obtain in the table; The parameter model that emulation is adopted is a SPICE model of going up the two aluminium technologies of 0.6 micron twin crystal of China): under the condition that supply voltage changes from 3.2V to 6.8V, the amplitude of variation of the cycle of oscillation of common RC oscillator is greater than 10%; The amplitude of variation of the cycle of oscillation of improved (but do not seal in voltage compensation PMOS pipe) RC oscillator was greater than 5% o'clock; After sealing in the PMOS pipe, the amplitude of variation of RC cycle of oscillation is less than 1%.
The common RC oscillator of table 1 (R=4.7M Ω)
| Operating voltage (V) | 3.2 | 3.5 | 4 | 5 | 6 | 6.5 | 6.8 | Error |
| RC cycle of oscillation (μ s) | 78.33 | 77.34 | 75.76 | 78.93 | 83.66 | 85.54 | 87.27 | 14.8％ |
The common RC oscillator of table 2 (R=820k Ω)
| Operating voltage (V) | 3.2 | 3.5 | 4 | 5 | 6 | 6.5 | 6.8 | Error |
| RC cycle of oscillation (μ s) | 19.21 | 19.14 | 20.06 | 19.11 | 18.58 | 18.33 | 17.82 | 12.57％ |
RC oscillator after table 3 improves (R=4.7M Ω, SEL=1, no P1, P2)
| Operating voltage (V) | 3.2 | 3.5 | 4 | 5 | 6 | 6.5 | 6.8 | Error |
| RC cycle of oscillation (μ s) | 77.96 | 78.49 | 79.11 | 80.31 | 81.35 | 82.10 | 82.14 | 5.36％ |
RC oscillator after table 4 improves (R=820k Ω, SEL=0, no P1, P2)
| Operating voltage (V) | 3.2 | 3.5 | 4 | 5 | 6 | 6.5 | 6.8 | Error |
| RC cycle of oscillation (μ s) | 21.01 | 20.89 | 20.66 | 20.41 | 20.12 | 19.93 | 19.84 | 5.90％ |
(R=4.7M Ω, SEL=1 seals in P1, P2) to high accuracy RC oscillator after table 5 improves
| Operating voltage (V) | 3.2 | 3.5 | 4 | 5 | 6 | 6.5 | 6.8 | Error |
| RC cycle of oscillation (μ s) | 79.52 | 79.51 | 79.64 | 80.03 | 80.15 | 80.16 | 80.16 | 0.82％ |
(R=820k Ω, SEL=0 seals in P1, P2) to high accuracy RC oscillator after table 6 improves
| Operating voltage (V) | 3.2 | 3.5 | 4 | 5 | 6 | 6.5 | 6.8 | Error |
| RC cycle of oscillation (μ s) | 19.99 | 20.02 | 20.11 | 20.17 | 20.16 | 20.16 | 20.16 | 0.90％ |
As the above analysis, advantage of the present invention is fairly obvious.
Description of drawings
Accompanying drawing 1 is existing common RC pierce circuit figure;
Accompanying drawing 2 is existing common RC oscillator wave figure;
Accompanying drawing 3 is the embodiment of the invention one circuit diagram;
Accompanying drawing 4 is the embodiment of the invention two circuit diagrams;
Accompanying drawing 5 is embodiment of the invention three-circuit figure;
Accompanying drawing 6 sends chip circuit figure for the present invention is applied to the multifunctional remote controlller coding;
Accompanying drawing 7 is the code element oscillogram (T is a chronomere, equals several clock cycle) of " 1 " sign indicating number, " 0 " sign indicating number and " F " sign indicating number.
Embodiment
Below in conjunction with drawings and Examples the present invention is further described:
Embodiment one: referring to shown in Figure 3, a kind of high accuracy RC oscillator with optional frequency is made up of outer meeting resistance R, capacitor C, discharge the one NMOS pipe N1, four inverter INV1～INV4 of first to fourth, three NAND gate ND1～ND3, first, second two adjustable threshold value inverter SPINV1, SPINV2 and first, the twoth PMOS pipe P1, P2 of first to the 3rd.
Outer meeting resistance R and capacitor C constitute the serial connection charge loop between power vd D and ground wire VSS, in the serial connection charge loop of outer meeting resistance R and capacitor C formation, seal in two first, second PMOS pipe P1, P2 that are connected in parallel, the drain D of first, second two PMOS pipes P1, P2 is in parallel with drain D, source S is in parallel with source S, and go here and there between outer meeting resistance R and capacitor C, the grid G earth connection VSS of PMOS pipe P1, the grid G of the 2nd PMOS pipe P2 connects to shake selects signal SEL frequently.The first termination power VDD of outer meeting resistance R, the source S of second termination first, second two PMOS pipes P1, P2, the drain D of first termination of capacitor C first, second two PMOS pipes P1, P2, the second termination ground wire VSS, the NMOS that discharges pipe N1 drain D meets the first end V1 of capacitor C, source S earth connection VSS, grid G meets oscillator output end V2.
First threshold is adjustable inverter SPINV1 is made up of the 3rd to the 5th three PMOS pipe P3～P5 and the 5th NMOS pipe N5, it is in parallel after the 4th PMOS manages P4 and the 5th PMOS pipe P5 connects with the 3rd PMOS pipe P3, the source S of the 3rd PMOS pipe P3 and the 4th PMOS pipe P4 meets power vd D, the drain D of the 4th PMOS pipe P4 connects the source S of the 5th PMOS pipe P5, the drain D of the 3rd PMOS pipe P3 and the 5th PMOS pipe P5 connects the drain D of the 5th NMOS pipe N5, the source S earth connection VSS of the 5th NMOS pipe N5; The grid G of the 5th PMOS pipe P5 is as the selecting side frequently that shakes of the adjustable inverter SPINV1 of first threshold, the grid G parallel connection of the 3rd PMOS pipe P3, the 4th PMOS pipe P4 and the 5th NMOS pipe N5 is as the input of the adjustable inverter SPINV1 of first threshold, and the drain D of the 5th NMOS pipe N5 picks out the output as the adjustable inverter SPINV1 of first threshold.
The second adjustable threshold value inverter SPINV2 is made up of second to the 4th three NMOS pipe N2～N4 and the 6th PMOS pipe P6, it is in parallel after the 3rd NMOS manages N3 and the 4th NMOS pipe N4 connects with the 2nd NMOS pipe N2, the source S earth connection VSS of the 2nd NMOS pipe N2 and the 4th NMOS pipe N4, the source S of the 3rd NMOS pipe N3 connects the drain D of the 4th NMOS pipe N4, the drain D of the 2nd NMOS pipe N2 and the 3rd NMOS pipe N3 connects the drain D of the 6th PMOS pipe P6, and the source S of the 6th PMOS pipe P6 meets power vd D; The grid G of the 3rd NMOS pipe N3 is as the selecting side frequently that shakes of the second adjustable threshold value inverter SPINV2, the grid G parallel connection of the 2nd NMOS pipe N2, the 4th NMOS pipe N4 and the 6th PMOS pipe P6 is as the input of the second adjustable threshold value inverter SPINV2, and the drain D of the 6th PMOS pipe P6 picks out the output as the second adjustable threshold value inverter SPINV2.
Annexation between above-mentioned each logic element: the first end V1 of capacitor C is respectively with first, the second two adjustable threshold value inverter SPINV1, the input of SPINV2 connects, shake and select signal SEL one tunnel to connect the selecting side frequently that shakes of the second adjustable threshold value inverter SPINV2 frequently, another road first inverter INV1 connects the selecting side frequently that shakes of the adjustable inverter SPINV1 of first threshold, the input of the output termination first NAND gate ND1 of first threshold is adjustable inverter SPINV1, the output of the second adjustable threshold value inverter SPINV2 connects the input of the second NAND gate ND2 behind the second inverter INV2, the output of another input termination second NAND gate ND2 of the first NAND gate ND1, the output of another input termination first NAND gate ND1 of the second NAND gate ND2, the output of the second NAND gate ND2 connects the input of the 3rd NAND gate ND3 through the 3rd inverter INV3, another input termination enable signal ENABLE of the 3rd NAND gate ND3, the output of the 3rd NAND gate ND3 meets oscillator output end V2 through the 4th inverter INV4.
The threshold voltage vt m of three inverter INV2～INV4 of above-mentioned second to the 4th and three NAND gate ND1～ND3 of first to the 3rd all is arranged on same theory design load (its error only is the technology manufacture deviation); First, second two adjustable threshold value inverter SPINV1, SPINV2 correspondences are shaken and are frequently selected signal SEL " 0 " with " 1 " two states two different threshold voltages to be arranged respectively, be that the adjustable inverter SPINV1 of first threshold has Vtp0 and Vtp1, when SEL=" 0 ", P5 turn-offs, and the threshold voltage of SPINV1 is Vtp0; When SEL=" 1 ", the P5 conducting, the threshold voltage of SPINV1 is Vtp1, obviously, Vtp0＜Vtp1.Equally, the second adjustable threshold value inverter SPINV2 has Vtn0 and Vtn1, and when SEL=" 0 ", N3 turn-offs, and the threshold voltage of the second adjustable threshold value inverter SPINV2 is Vtn0; When SEL=" 1 ", the N3 conducting, the threshold voltage of the second adjustable threshold value inverter SPINV2 is Vtn1, and Vtn0＞Vtn1; Satisfy following relation between described Vtp0, Vtp1, Vtn0, Vtn1 and the Vtm:
Vtp1＞Vtp0＞Vtm＞Vtn0＞Vtn1。
The operation principle of present embodiment is seen above summary of the invention part, no longer is repeated in this description here.
Embodiment two: referring to shown in Figure 4, a kind of high accuracy RC oscillator with optional frequency is made up of outer meeting resistance R, capacitor C, discharge the one NMOS pipe N1, five inverter INV1～INV5 of first to the 5th, two NAND gate ND1～ND2, first, second two adjustable threshold value inverter SPINV1, SPINV2 and first, second two PMOS pipes P1, P2 of first to second.
Present embodiment and embodiment one difference are: replaced the 3rd NAND gate ND3 among the embodiment one with the 5th inverter INV5.Therefore, present embodiment enables do not have controlled function with dormancy to oscillator, and oscillator is in running order always.Other structure is identical with embodiment one, no longer is repeated in this description here.
Embodiment three: referring to shown in Figure 5, a kind of RC oscillator with optional frequency is made up of outer meeting resistance R, capacitor C, discharge the one NMOS pipe N1, four inverter INV1～INV4 of first to fourth, three NAND gate ND1～ND3 and first, second two adjustable threshold value inverter SPINV1, SPINV2 of first to the 3rd.
Present embodiment and embodiment one difference are: in embodiment one, first, second two PMOS pipes P1, P2 of being serially connected between outer meeting resistance R and the capacitor C remove, and make outer meeting resistance R and capacitor C directly constitute the serial connection charge loop between power vd D and ground wire VSS.It also is feasible doing like this, and the stability of a RC oscillator is compared with embodiment one to some extent and descended, referring to above-mentioned table 3 and table 4.Other is identical with embodiment one, no longer is repeated in this description here.
Application example: the best way of the embodiment of the invention one is applied in the various integrated circuit (IC) chip that need high accuracy RC oscillator, especially for the chip of two kinds of different operating frequencies of needs.Fig. 6 is an application example of the present invention.
Circuit shown in Figure 6 is a two-in-one chip, is about to two integrated circuits with different purposes and is made on the chip.This is our company's multifunction remote-control coding transmission chip of a novelty of release soon.Before this, our company once released remote control coding transmission chip: the HS2260 and the HS2262 of two difference in functionality.Chip circuit shown in Figure 5 promptly can be used as HS2260, also can be used as HS2262.The diagram circuit has 1 function selecting end " SEL ", 1 signaling control end " TE ", 1 outer meeting resistance port, 4 data inputs (D0 to D3) and 8 address input ends (A0 to A7).
The operation principle of circuit shown in Figure 6 is as described below.
When SEL connects " 0 ", when outer meeting resistance was 820k Ω, circuit working was in the HS2260 pattern.With this understanding, the RC oscillator will be operated in the higher zone of frequency (be 20 μ s its specified cycle of oscillation) when allowing vibration; The TE control end is invalid; Circuit is by waking up by key input signal; When key is pressed, circuit will be waken up; All connected by the switching circuit of SEL control, D0 to D3 connects pull down resistor, and D0 to D3 all uses (a termination VDD of key switch, button input port of another termination) as the button input port; A0 to A7 is the geocoding input port, can or connect power supply (VDD) or unsettled by any ground connection of user (GND).
When SEL connects " 1 ", when outer meeting resistance was 4.7M Ω, circuit working was in the HS2262 pattern.With this understanding, the RC oscillator will be operated in the lower zone of frequency (be 80 μ s its specified cycle of oscillation) when allowing vibration; The TE control end works; When TE is high level, circuit will be waken up; All turn-offed by the switching circuit of SEL control; D0 to D3 does not connect pull down resistor, and D0 to D3 all as the digital coding input port with (circuit do not connect keyboard input); A0 to A7 is the geocoding input port; D0 to D3 and A0 to A7 all can or connect power supply (VDD) or unsettled by any ground connection of user (GND).
Circuit shown in Figure 6 can be waken up by signaling control end signal under HS2262 pattern condition of work by waking up by key input signal under HS2260 pattern condition of work.After circuit powered on, reset circuit resetted each data latch unit, and circuit enters power saving standby mode (resting state).When circuit working in the HS2260 pattern and there is key to press, or circuit working is when HS2262 pattern and TE low level become high level, and circuit will be waken up, and " ENABLE " signal is a high level, the present invention's " high accuracy RC oscillator " produces the required work clock signal of chip with regard to starting oscillation." branch frequency counting circuit " begins frequency division counter under the driving of clock signal.
" code element generation circuit " carries out logical combination to the signal from branch frequency counting circuit, produces " 0 " sign indicating number as shown in Figure 7, the waveform and the VF signal (cycle is the square wave of 8T, and preceding 4T is a low level, and back 4T is a high level) of " 1 " sign indicating number." address decoding circuitry " deciphered the digital signal from branch frequency counting circuit.Decode results is given " multiplexer circuit ", as selecting control signal.Multiplexer circuit is according to control signal each input port of gating one by one in order." port connection status judging circuit " is to being differentiated by the state of the port input signal V1 of gating (meet " GND ", meet " VDD " or unsettled).If met " GND " by the input port of gating, then V1 is " 0 ", and the output V2 of port connection status judging circuit also is " 0 "; Alternative circuit " MUX " is with the waveform of gating " 0 " sign indicating number, and output driver " OUTPUT-DRIVER " will outwards send one " 0 " sign indicating number in view of the above.If met " VDD " by the input port of gating, then V1 is " 1 ", and V2 also is " 1 "; MUX is with the waveform of gating " 1 " sign indicating number, and OUTPUT-DRIVER will outwards send one " 1 " sign indicating number in view of the above.Unsettled as if being connect by the input port of gating, then V1 is controlled by VF, and the waveform of V2 is identical with VF, and OUTPUT-DRIVER will outwards send one " F " sign indicating number in view of the above.Like this, chip circuit will be according to the connection situation and the key combination of each port, and outwards sending a string in order is a string encoding of code element with " 0 " sign indicating number, " 1 " sign indicating number, " F " sign indicating number, or claims frame coding.
Whenever there being key to press (HS2260 pattern), or TE is when becoming high level (HS2262 pattern) by low level, and circuit just outwards sends a frame sign indicating number or a few frame sign indicating number.If according to not putting, it is the above-mentioned coding of unit that circuit just will constantly outwards send with the frame to button, till button discharges always.After button discharges, the failure of oscillations immediately of RC oscillator, all data latch unit reset, and circuit enters power saving standby mode (resting state).
The foregoing description only is explanation technical conceive of the present invention and characteristics, and its purpose is to allow the personage who is familiar with this technology can understand content of the present invention and enforcement according to this, can not limit protection scope of the present invention with this.All equivalences that spirit is done according to the present invention change or modify, and all should be encompassed within protection scope of the present invention.
Claims (3)
1, a kind of high accuracy RC oscillator with optional frequency, comprise outer meeting resistance (R), electric capacity (C) and the NMOS that discharges pipe (N1), outer meeting resistance (R) and electric capacity (C) constitute the serial connection charge loop between power supply (VDD) and ground wire (VSS), wherein, outer meeting resistance (R) first termination power (VDD), first end of second termination capacitor (C), the second termination ground wire (VSS) of electric capacity (C); The NMOS that discharges pipe (N1) drain electrode (D) connects first end (V1) of electric capacity (C), source electrode (S) earth connection (VSS), grid (G) connects oscillator output end (V2), it is characterized in that: described oscillator also comprises four inverters of first to fourth (INV1～INV4), three NAND gate of first to the 3rd (ND1～ND3) and two adjustable threshold value inverters (SPINV1, SPINV2) of first to second;
The adjustable inverter of first threshold (SPINV1) is managed (P3～P5) form with the 5th NMOS pipe (N5) by three PMOS of the 3rd to the 5th, it is in parallel after the 4th PMOS manages (P4) and the 5th PMOS pipe (P5) is connected with the 3rd PMOS pipe (P3), the source electrode (S) of the 3rd PMOS pipe (P3) and the 4th PMOS pipe (P4) connects power supply (VDD), the drain electrode (D) of the 4th PMOS pipe (P4) connects the source electrode (S) of the 5th PMOS pipe, the drain electrode (D) of the 3rd PMOS pipe (P3) and the 5th PMOS pipe (P5) connects the drain electrode (D) of the 5th NMOS pipe (N5), source electrode (S) earth connection (VSS) of the 5th NMOS pipe (N5); The grid (G) of the 5th PMOS pipe (P5) is as the selecting side frequently that shakes of the adjustable inverter of first threshold (SPINV1), the grid (G) of the 3rd PMOS pipe (P3), the 4th PMOS pipe (P4) and the 5th NMOS pipe (N5) input as the adjustable inverter of first threshold (SPINV1) in parallel, the drain electrode (D) of the 5th NMOS pipe (N5) picks out the output as the adjustable inverter of first threshold (SPINV1);
The second adjustable threshold value inverter (SPINV2) is managed (N2～N4) form with the 6th PMOS pipe (P6) by three NMOS of second to the 4th, it is in parallel after the 3rd NMOS manages (N3) and the 4th NMOS pipe (N4) is connected with the 2nd NMOS pipe (N2), source electrode (S) earth connection (VSS) of the 2nd NMOS pipe (N2) and the 4th NMOS pipe (N4), the source electrode (S) of the 3rd NMOS pipe (N3) connects the drain electrode (D) of the 4th NMOS pipe (N4), the drain electrode (D) of the 2nd NMOS pipe (N2) and the 3rd NMOS pipe (N3) connects the drain electrode (D) of the 6th PMOS pipe (P6), and the source electrode (S) of the 6th PMOS pipe (P6) connects power supply (VDD); The grid (G) of the 3rd NMOS pipe (N3) is as the selecting side frequently that shakes of the second adjustable threshold value inverter (SPINV2), the grid (G) of the 2nd NMOS pipe (N2), the 4th NMOS pipe (N4) and the 6th PMOS pipe (P6) input as the second adjustable threshold value inverter (SPINV2) in parallel, the drain electrode (D) of the 6th PMOS pipe (P6) picks out the output as the second adjustable threshold value inverter (SPINV2);
Annexation between above-mentioned each logic element: first end (V1) of electric capacity (C) is respectively with first, the second two adjustable threshold value inverter (SPINV1, SPINV2) input connects, shake and select signal (SEL) a tunnel to connect the selecting side frequently that shakes of the second adjustable threshold value inverter (SPINV2) frequently, another road first inverter (INV1) connects the selecting side frequently that shakes of the adjustable inverter of first threshold (SPINV1), an input of output termination first NAND gate (ND1) of the adjustable inverter of first threshold (SPINV1), the output of the second adjustable threshold value inverter (SPINV2) connects an input of second NAND gate (ND2) behind second inverter (INV2), the output of another input termination second NAND gate (ND2) of first NAND gate (ND1), the output of another input termination first NAND gate (ND1) of second NAND gate (ND2), the output of second NAND gate (ND2) connects an input of the 3rd NAND gate (ND3) through the 3rd inverter (INV3), another input termination enable signal (ENABLE) of the 3rd NAND gate (ND3), the output of the 3rd NAND gate (ND3) connects oscillator output end (V2) through the 4th inverter (INV4);
((the threshold voltage vt m of ND1～ND3) all is arranged on the same theory design load to three inverters of described second to the 4th for INV2～INV4) and three NAND gate of first to the 3rd; First, second two adjustable threshold value inverters (SPINV1, SPINV2) correspondence is shaken and is frequently selected " 0 " of signal (SEL) with " 1 " two states two different threshold voltages to be arranged respectively, be that the adjustable inverter of first threshold (SPINV1) has Vtp0 and Vtp1, the second adjustable threshold value inverter (SPINV2) has Vtn0 and Vtn1, and Vtp0＜Vtp1, Vtn0＞Vtn1; Satisfy following relation between described Vtp0, Vtp1, Vtn0, Vtn1 and the Vtm:
Vtp1＞Vtp0＞Vtm＞Vtn0＞Vtn1。
2, a kind of high accuracy RC oscillator with optional frequency, comprise outer meeting resistance (R), electric capacity (C) and the NMOS that discharges pipe (N1), outer meeting resistance (R) and electric capacity (C) constitute the serial connection charge loop between power supply (VDD) and ground wire (VSS), wherein, outer meeting resistance (R) first termination power (VDD), first end of second termination capacitor (C), the second termination ground wire (VSS) of electric capacity (C); The NMOS that discharges pipe (N1) drain electrode (D) connects first end (V1) of electric capacity (C), source electrode (S) earth connection (VSS), grid (G) connects oscillator output end (V2), it is characterized in that: described oscillator also comprises five inverters of first to the 5th (INV1～INV5), two NAND gate of first to second (ND1～ND2) and two adjustable threshold value inverters (SPINV1, SPINV2) of first to second;
The adjustable inverter of first threshold (SPINV1) is managed (P3～P5) form with the 5th NMOS pipe (N5) by three PMOS of the 3rd to the 5th, it is in parallel after the 4th PMOS manages (P4) and the 5th PMOS pipe (P5) is connected with the 3rd PMOS pipe (P3), the source electrode (S) of the 3rd PMOS pipe (P3) and the 4th PMOS pipe (P4) connects power supply (VDD), the drain electrode (D) of the 4th PMOS pipe (P4) connects the source electrode (S) of the 5th PMOS pipe, the drain electrode (D) of the 3rd PMOS pipe (P3) and the 5th PMOS pipe (P5) connects the drain electrode (D) of the 5th NMOS pipe (N5), source electrode (S) earth connection (VSS) of the 5th NMOS pipe (N5); The grid (G) of the 5th PMOS pipe (P5) is as the selecting side frequently that shakes of the adjustable inverter of first threshold (SPINV1), the grid (G) of the 3rd PMOS pipe (P3), the 4th PMOS pipe (P4) and the 5th NMOS pipe (N5) input as the adjustable inverter of first threshold (SPINV1) in parallel, the drain electrode (D) of the 5th NMOS pipe (N5) picks out the output as the adjustable inverter of first threshold (SPINV1);
The second adjustable threshold value inverter (SPINV2) is managed (N2～N4) form with the 6th PMOS pipe (P6) by three NMOS of second to the 4th, it is in parallel after the 3rd NMOS manages (N3) and the 4th NMOS pipe (N4) is connected with the 2nd NMOS pipe (N2), source electrode (S) earth connection (VSS) of the 2nd NMOS pipe (N2) and the 4th NMOS pipe (N4), the source electrode (S) of the 3rd NMOS pipe (N3) connects the drain electrode (D) of the 4th NMOS pipe (N4), the drain electrode (D) of the 2nd NMOS pipe (N2) and the 3rd NMOS pipe (N3) connects the drain electrode (D) of the 6th PMOS pipe (P6), and the source electrode (S) of the 6th PMOS pipe (P6) connects power supply (VDD); The grid (G) of the 3rd NMOS pipe (N3) is as the selecting side frequently that shakes of the second adjustable threshold value inverter (SPINV2), the grid (G) of the 2nd NMOS pipe (N2), the 4th NMOS pipe (N4) and the 6th PMOS pipe (P6) input as the second adjustable threshold value inverter (SPINV2) in parallel, the drain electrode (D) of the 6th PMOS pipe (P6) picks out the output as the second adjustable threshold value inverter (SPINV2);
Annexation between above-mentioned each logic element: first end (V1) of electric capacity (C) is respectively with first, the second two adjustable threshold value inverter (SPINV1, SPINV2) input connects, shake and select signal (SEL) a tunnel to connect the selecting side frequently that shakes of the second adjustable threshold value inverter (SPINV2) frequently, another road first inverter (INV1) connects the selecting side frequently that shakes of the adjustable inverter of first threshold (SPINV1), an input of output termination first NAND gate (ND1) of the adjustable inverter of first threshold (SPINV1), the output of the second adjustable threshold value inverter (SPINV2) connects an input of second NAND gate (ND2) behind second inverter (INV2), the output of another input termination second NAND gate (ND2) of first NAND gate (ND1), the output of another input termination first NAND gate (ND1) of second NAND gate (ND2), the output of second NAND gate (ND2) is through the 3rd inverter (INV3), the 5th inverter (INV5) and the 4th inverter (INV4) series connection oscillator output end (V2);
((the threshold voltage vt m of ND1～ND2) all is arranged on the same theory design load to four inverters of described second to the 5th for INV2～INV5) and first, second two NAND gate; First, second two adjustable threshold value inverters (SPINV1, SPINV2) correspondence is shaken and is frequently selected " 0 " of signal (SEL) with " 1 " two states two different threshold voltages to be arranged respectively, be that the adjustable inverter of first threshold (SPINV1) has Vtp0 and Vtp1, the second adjustable threshold value inverter (SPINV2) has Vtn0 and Vtn1, and Vtp0＜Vtp1, Vtn0＞Vtn1; Satisfy following relation between described Vtp0, Vtp1, Vtn0, Vtn1 and the Vtm:
Vtp1＞Vtp0＞Vtm＞Vtn0＞Vtn1。
3, high accuracy RC oscillator with optional frequency according to claim 1 and 2, it is characterized in that: in the serial connection charge loop of outer meeting resistance (R) and electric capacity (C) formation, seal in two be connected in parallel first, the 2nd PMOS manages (P1, P2), first, the second two PMOS pipe (P1, P2) drain electrode (D) is in parallel with drain electrode (D), source electrode (S) is in parallel with source electrode (S), and string is between outer meeting resistance (R) and electric capacity (C), grid (G) earth connection (VSS) of the one PMOS pipe (P1), the grid (G) of the 2nd PMOS pipe (P2) connect to shake selects signal (SEL) frequently.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100385823A CN1300940C (en) | 2005-03-25 | 2005-03-25 | High accuracy RC oscillator with optional frequency |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100385823A CN1300940C (en) | 2005-03-25 | 2005-03-25 | High accuracy RC oscillator with optional frequency |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1665134A CN1665134A (en) | 2005-09-07 |
| CN1300940C true CN1300940C (en) | 2007-02-14 |
Family
ID=35036059
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005100385823A Expired - Fee Related CN1300940C (en) | 2005-03-25 | 2005-03-25 | High accuracy RC oscillator with optional frequency |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1300940C (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101127505B (en) * | 2006-08-17 | 2010-05-12 | 普诚科技股份有限公司 | Oscillator |
| CN102739197B (en) * | 2012-07-17 | 2015-08-19 | 杭州士兰微电子股份有限公司 | A kind of RC ring oscillator and voltage adjusting method thereof |
| CN103116974B (en) * | 2013-03-04 | 2015-06-17 | 中颖电子股份有限公司 | Remote control chip for reducing frequency drift of inbuilt oscillating circuit |
| CN104702216B (en) * | 2013-12-10 | 2018-04-27 | 展讯通信（上海）有限公司 | A kind of oscillating circuit |
| CN107359862B (en) * | 2017-06-07 | 2020-11-06 | 李凯林 | RC oscillation circuit for realizing hysteresis by using capacitor |
| CN110995160B (en) * | 2019-12-31 | 2023-04-07 | 广州裕芯电子科技有限公司 | High-performance oscillator |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0730382A (en) * | 1993-07-13 | 1995-01-31 | Oki Micro Design Miyazaki:Kk | Voltage-controlled oscillator |
| CN1190825A (en) * | 1997-02-14 | 1998-08-19 | 日本电气株式会社 | Oscilation circuit and delay circuit |
| US6127898A (en) * | 1997-01-13 | 2000-10-03 | Sgs-Thomson Microelectroncs S.A. | Ring oscillator using CMOS technology |
| US6184754B1 (en) * | 1998-03-03 | 2001-02-06 | Nec Corporation | Voltage-controlled oscillator circuit and voltage-controlled oscillating method |
| CN1592084A (en) * | 2003-08-13 | 2005-03-09 | 松下电器产业株式会社 | Oscillator circuit and oscillation stabilizing method |
-
2005
- 2005-03-25 CN CNB2005100385823A patent/CN1300940C/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0730382A (en) * | 1993-07-13 | 1995-01-31 | Oki Micro Design Miyazaki:Kk | Voltage-controlled oscillator |
| US6127898A (en) * | 1997-01-13 | 2000-10-03 | Sgs-Thomson Microelectroncs S.A. | Ring oscillator using CMOS technology |
| CN1190825A (en) * | 1997-02-14 | 1998-08-19 | 日本电气株式会社 | Oscilation circuit and delay circuit |
| US6184754B1 (en) * | 1998-03-03 | 2001-02-06 | Nec Corporation | Voltage-controlled oscillator circuit and voltage-controlled oscillating method |
| CN1592084A (en) * | 2003-08-13 | 2005-03-09 | 松下电器产业株式会社 | Oscillator circuit and oscillation stabilizing method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1665134A (en) | 2005-09-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1300940C (en) | High accuracy RC oscillator with optional frequency | |
| KR100744640B1 (en) | Clock driver | |
| CN102386898B (en) | Reset circuit | |
| US7928772B1 (en) | Clock input filter circuit | |
| CN108494234A (en) | Floating power supply rail suitable for GaN high speed gate drive circuits | |
| CN1347197A (en) | Semiconductor integrated circuit | |
| CN101330285B (en) | Signal time-delay integrated circuit | |
| CN104378084A (en) | Glitch filter and filtering method | |
| CN102006039B (en) | Reset circuit | |
| CN106877863A (en) | OSC circuits on a kind of high stability low-power consumption piece | |
| US8937493B2 (en) | Ternary T arithmetic circuit | |
| CN101789786B (en) | Full-difference bimodule prescalar with low power consumption | |
| CN1794577A (en) | Delay unit of pressure controlled oscillator | |
| CN1518224A (en) | Output driver with low ground jump noise | |
| CN102624378B (en) | Low-power-consumption domino three-value character arithmetic circuit | |
| CN2785260Y (en) | Low power-consuming, high reliability remote controller chip keystroke input port circuit | |
| CN201191817Y (en) | Schmitt trigger | |
| CN109039327A (en) | A kind of level shifting circuit | |
| CN1783718A (en) | Logic circuit | |
| CN208836110U (en) | A kind of level shifting circuit | |
| CN210225367U (en) | Inverter with latch function | |
| CN204068924U (en) | Low impulse output circuit and apply the equipment of low impulse output circuit | |
| Dai et al. | Adiabatic CPL circuits for sequential logic systems | |
| CN104299647A (en) | Negative pressure converting circuit | |
| CN107517045B (en) | Ring oscillator |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| EE01 | Entry into force of recordation of patent licensing contract |
Assignee: Hefei Hejing Electronic Co., Ltd. Assignor: Suzhou HuaXin Micro-electronics Co., Ltd. Contract fulfillment period: 2008.8.30 to 2013.8.30 contract change Contract record no.: 2009340000271 Denomination of invention: High accuracy RC oscillator with optional frequency Granted publication date: 20070214 License type: Exclusive license Record date: 2009.9.4 |
|
| LIC | Patent licence contract for exploitation submitted for record |
Free format text: EXCLUSIVE LICENSE; TIME LIMIT OF IMPLEMENTING CONTACT: 2008.8.30 TO 2013.8.30; CHANGE OF CONTRACT Name of requester: HEFEI HEJING ELECTRONIC CO., LTD Effective date: 20090904 |
|
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20070214 |