CN108494234A - Floating power supply rail suitable for GaN high speed gate drive circuits - Google Patents
Floating power supply rail suitable for GaN high speed gate drive circuits Download PDFInfo
- Publication number
- CN108494234A CN108494234A CN201810309410.2A CN201810309410A CN108494234A CN 108494234 A CN108494234 A CN 108494234A CN 201810309410 A CN201810309410 A CN 201810309410A CN 108494234 A CN108494234 A CN 108494234A
- Authority
- CN
- China
- Prior art keywords
- nmos tube
- power supply
- pmos tube
- tube
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
- H03K17/08104—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit in field-effect transistor switches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
Suitable for the floating power supply rail of GaN high speed gate drive circuits, belong to technical field of power management.The present invention can be realized using the design of double floating power supply rails while meet GaN device for power switching and work in safe voltage and turned the floating power supply rail that high voltage level shift circuit possesses enough dynamic ranges with low pressure；High pressure turns low voltage level shift circuit, voltage clamp circuit, logic control circuit and the first floating power supply rail generation circuit and constitutes closed loop; for generating power rails of the first power rail BST as the buffer circuit in GaN high speed gate drive circuits, GaN device for power switching gate source voltages can be protected to be operated in safe range；Second floating power supply rail generation circuit constitutes open loop, turns the power rail of high voltage level shift circuit for generating second source rail BSTA as the low pressure in GaN high speed gate drive circuits, it can be ensured with enough dynamic ranges.
Description
Technical field
The invention belongs to technical field of power management, and in particular to a kind of floating suitable for GaN high speed gate drive circuits
Power rail.
Background technology
With the development of power electronic in recent years, half-bridge drive circuit just develops towards the direction of high power, high frequency, this
The design of selection and circuit to power tube brings new requirement.Traditional half-bridge drive circuit mainly chooses silicon power tube work
For power stage, in contrast, due to GaN device for power switching (such as GaN HEMT) have it is high pressure resistant, without reverse recovery time
Good physical characteristic, therefore it is excellent to use the half-bridge gate drive circuit of GaN device for power switching to possess high speed, high power density etc.
Good characteristic.But in the work(for using enhanced GaN device for power switching to do half-bridge gate drive circuit (below by taking GaN HEMT as an example)
When rate pipe, it may appear that following phenomenon causes the conventional high rate high power gate drive circuit suitable for Si power tubes to be not used to enhance
Type GaN device for power switching.
It is as shown in Figure 1 the structural schematic diagram by enhanced GaN device for power switching applied to the driving of half-bridge grid, in figure 1.
Indicate that the pumping due to external load carries, there are power stage bias voltage VSWFor negative situation；It is 2. indicated due to enhanced GaN in figure
The grid source of device for power switching is resistance to be forced down, must be by bootstrap capacitor C in circuitbootUpper bottom crown pressure difference VBST-VSWClamper is in safety
In working range；It is 3. indicated due to bootstrap capacitor C in figurebootUpper bottom crown pressure difference VBST-VSWIt is clamped, BST in dead time
Voltage is due to CbootCapacitive coupling acts on, and can reduce as SW enters negative pressure, low pressure is caused to turn high voltage level shift circuit
(Level Up) dynamic range is inadequate；4. indicate that the power rail that low pressure turns high voltage level shift circuit (Level Up) is in figure
BST, VSS, then in dead time, drive signal passes through the amplitude V after level shiftBST-VSS=VCboot-|VSW| it can be due to
The upper bottom crown pressure difference V of CbootCbootIt is clamped, SW enters negative pressure and reduces；Above 4 kinds of situations will lead to two consequences：First,
It is inadequate that low pressure turns high voltage level shift circuit (Level Up) dynamic range so that slowing for level shift no longer meets
High speed grid drive the requirement to transmission delay, and by taking Fig. 2 mesolows turn high voltage level shift circuit (Level Up) as an example, float electricity
Source rail voltage VBSTReduction so that low pressure turns the gate source voltage V of power tube M1, M2 in high voltage level shift circuitGSBecome smaller, it is low
Pressure turns high voltage level shift circuit and dies down to the pull-up and pull-down capability of output node, leads to slowing for level shift；Its
Two, the power rail that low pressure turns high voltage level shift circuit (Level Up) level logic circuit afterwards is BST, SW, and low pressure turns high pressure
The power rail of level displacement circuit (Level Up) is BST, VSS, and the reference ground of the two is different, then drive signal passes through level position
Amplitude V after shiftingBST-VSS=VCboot-|VSW| after entering negative pressure reduction with SW, it can gradually can not touch the threshold value electricity of rear class logic
Flat VT, final to lead to the problem of drive signal loss.
In the off case, electric current flows to drain terminal to GaN HEMT (GaN high electron mobility transistor) in Fig. 1 from source
When, drain-source voltage VDSThe negative pressure of -2~-3V is had, therefore in half-bridge gate drive circuit, when GaN HEMT make lower power tube,
Since the pumping of external load carries in dead time, there are power stage bias voltage VSWFor negative situation, and load current is higher, bears
Press situation more serious；And in the traditional design scheme of bootstrap capacitor power supply module, floating power supply rail BST is by low-tension supply rail VDD
Power supply, this causes in dead time to bootstrap capacitor CbootWhen charging, bootstrap capacitor CbootTop crown is by bootstrap diode clamper
In VDDThe pressure difference of current potential, capacitance both ends reaches as high as (VDD+3)V；But due to the grid source breakdown voltage of GaN HEMT it is smaller (it is required that
VGS<6V, optimal drive voltage are no more than 5.5V), then upper power tube when opening easily due to bootstrap capacitor both ends pressure difference is excessive
Puncture.
It therefore, must addition clamper bootstrap capacitor C on charging bootstrap capacitor access in the design of some bridge crystal drive circuitsbootOn
Bottom crown voltage difference VBST-VSWClamp circuit, to avoid upper power tube that GaN pipe dielectric layers occur because gate source voltage is excessive
Breakdown.But because bootstrap capacitor CbootThe voltage difference V of upper bottom crownBST-VSWIt is clamped to ensure trouble free service within 5.5V,
And power stage bias voltage V in dead timeSWNegative value is very big, then due to bootstrap capacitor CbootCoupling, floating power supply rail
BST level can follow power stage bias voltage VSWIt is far below 5V into negative pressure, this just brings new problem：1. making bridge joint
It is inadequate that upper power tube control circuit and the low pressure of low voltage logic circuit turn high voltage level shift circuit (Level Up) dynamic range
(low pressure turns the power rail of high voltage level shift circuit with being generally floating power supply rail BST and chip), causes low pressure to turn high-voltage electricity
Prosposition shift circuit (Level Up) response speed does not meet high-speed demand, and drive signal transmission delay increases；2. rear class logic electricity
The threshold level on road can drop in dead time with floating power supply rail BST declines synchronous with low-tension supply rail SW current potentials
It is low, simultaneously because the reduction that low pressure turns high voltage level shift circuit (Level Up) dynamic range can cause drive signal to pass through electricity
Amplitude after prosposition moves reduces, the two phenomenons can cause input signal not identified by rear level logic circuit in transmission and occur
Dropout.Problem above gives the high-speed high-power half-bridge gate drive circuit design suitable for GaN device for power switching to bring
Problem so that it is difficult to realize can meet GaN device for power switching simultaneously and work in safe voltage turn high voltage level with low pressure
Shift circuit (Level Up) possesses the floating power supply rail of enough dynamic ranges.
Invention content
Place against the above deficiency, the present invention propose a kind of suitable for the floating of GaN high-speed high-power half-bridge gate drive circuits
Dynamic power rail is ensureing bootstrap capacitor CbootUnder the premise of upper and lower polar plate voltage difference is clamped in safe voltage, the present invention adopts
It is powered, is eliminated the tradition suitable for Si power tubes to GaN half-bridge gate drive circuits with double floating power supply rail generation circuits
Grid drive floating power supply rail generation circuit to be applied to upper power tube dielectric layer caused by GaN device for power switching can breakdown and drive
Dynamic signal transmission delay increases the negative issue even lost.
The technical scheme is that：
Turn low voltage level shift circuit, voltage clamp suitable for the floating power supply rail of GaN high speed gate drive circuits, including high pressure
Position circuit, logic control circuit, the first floating power supply rail generation circuit and the second floating power supply rail generation circuit,
The second floating power supply rail generation circuit includes the first diode D1, the second diode D2With bootstrap capacitor Cboot,
First diode D1Anode connection supply voltage VDD, the second diode D of cathode connection2Cathode and generate second float electricity
Source rail BSTA；Bootstrap capacitor CbootTop crown connect the second diode D2Anode and the first floating power supply rail generate
The output end of circuit, bottom crown connect the half-bridge switch node SW of the GaN high speeds gate drive circuit；
Two input terminals of the voltage clamp circuit are separately connected the bootstrap capacitor CbootTop crown and bottom crown,
For detecting the bootstrap capacitor CbootPolar plate voltage up and down difference and export first control signal Ctrl1 to the high pressure turn it is low
The input terminal of voltage level shift circuit；
The high pressure turns low voltage level shift circuit and the first control signal Ctrl1 is gone to low-tension supply rail, output
First logic control signal LV1 and the second logic control signal LV2 and two input terminals for connecting the logic control circuit；
The logic control circuit is generated according to the first logic control signal LV1 and the second logic control signal LV2
Second control signal Ctrl2 and the input terminal for connecting the first floating power supply rail generation circuit；
The first floating power supply rail generation circuit is for generating the first floating power supply rail BST.
Specifically, it is characterized in that, the GaN high speeds gate drive circuit, which includes buffer circuit and low pressure, turns high-voltage electricity prosposition
The power rail of shift circuit, the buffer circuit is the first floating power supply rail BST and half-bridge switch node power rail SW, the low pressure
The power rail for turning high voltage level shift circuit is the second floating power supply rail BSTA and half-bridge switch node power rail SW.
Specifically, the first floating power supply rail generation circuit includes low tension switch pipe PM0, bootstrap diode DBOOT,
One resistance R1, NPN type triode, Zener Zener and second resistance R2,
The grid of low tension switch pipe PM0 connects described second as the input terminal of the first floating power supply rail generation circuit
Control signal Ctrl2, source electrode connect one end of first resistor R1, NPN type triode collector and Zener Zener the moon
Pole simultaneously connects supply voltage VDD, the other end of drain electrode connection first resistor R1, the emitter of NPN type triode and bootstrapping two
Pole pipe DBOOTAnode；
The anode of the base stage connection Zener of NPN type triode simultaneously passes through connection bootstrap diode D after second resistance R2BOOT
Anode, bootstrap diode DBOOTCathode as the first floating power supply rail generation circuit output end output first float
Power rail BST.
Specifically, the logic control circuit includes latch up protection module, RS latch modules and buffer,
The latch up protection module includes the first phase inverter INV1, the second phase inverter INV2, third phase inverter INV3, the 4th
Phase inverter INV4, the 5th phase inverter INV5, hex inverter INV6, the first NAND gate NAND1 and the second NAND gate NAND2,
The input terminal of first phase inverter INV1 connects the input terminal of the second phase inverter INV2 and connects the second logic control
Signal LV2 processed, output end connect the first input end of the first NAND gate NAND1；The input terminal of third phase inverter INV3 connects
The output end of second phase inverter INV2, output end connect the first input end of the second NAND gate NAND2；
The input terminal of hex inverter INV6 connects the input terminal of the 4th phase inverter INV4 and connects the first logic control
Signal LV1 processed, output end connect the second input terminal of the second NAND gate NAND2；The input terminal of 5th phase inverter INV5 connects
The output end of 4th phase inverter INV4, output end connect the second input terminal of the first NAND gate NAND1；
The RS latch includes third NAND gate NAND3 and the 4th NAND gate NAND4, the third NAND gate NAND3
First input end connect the output end of the first NAND gate NAND1, second output terminal connects the 4th NAND gate NAND4's
Output end, output end connect the input terminal of the first input end and the buffer of the 4th NAND gate NAND4；4th NAND gate
The second input terminal of NAND4 connects the output end of the second NAND gate NAND2, and the output end of buffer is as the logic control
The output end output second control signal Ctrl2 of circuit processed.
Specifically, the voltage clamp circuit includes the 7th phase inverter INV7,3rd resistor R3, the 4th resistance R4, the 5th
Resistance R5, the 6th resistance R6, the 7th resistance R7, the first triode Q1, the second triode Q2, the first NMOS tube NM1, the 2nd NMOS
Pipe NM2, third NMOS tube NM3, the 4th NMOS tube NM4, the 5th NMOS tube NM5, the 6th NMOS tube NM6, the 7th NMOS tube NM7,
First PMOS tube PM1, the second PMOS tube PM2, third PMOS tube PM3 and the 4th PMOS tube PM4；
The input terminal of 7th phase inverter INV7 connects the 4th PMOS tube PM4, the 5th NMOS tube NM5 and the 6th NMOS tube NM6
Grid and third PMOS tube PM3 and the 4th NMOS tube NM4 drain electrode, output end connect the first PMOS tube PM1 grid；
The grid of first NMOS tube NM1 connects the grid and the collection of drain electrode and the first triode Q1 of the second NMOS tube NM2
Electrode, the grid and the grid of drain electrode and third PMOS tube PM3 of the second PMOS tube PM2 of drain electrode connection, source electrode connection the
Two NMOS tube NM2, third NMOS tube NM3, the source electrode of the 4th NMOS tube NM4 and the 6th NMOS tube NM6 and as the voltage clamp
The first input end of position circuit connects the voltage V at the half-bridge switch node of the GaN high speeds gate drive circuitSW；
3rd resistor R3 is connected between the source electrode and drain electrode of the first PMOS tube PM1, the 4th resistance R4 and the 5th resistance R5 strings
Connection is attempted by between the drain electrode of the first PMOS tube PM1 and the source electrode of the first NMOS tube NM1, and series connection point connects the first triode Q1
With the base stage of the second triode Q2；
6th resistance R6 and the 7th resistance R7 connects and connects the hair of the source electrode and the first triode Q1 of the first PMOS tube PM1
Between emitter-base bandgap grading, series connection point connects the emitter of the second triode Q2；
The grid leak short circuit of third NMOS tube NM3 and the grid of the collector and the 4th NMOS tube NM4 of the second triode Q2 of connection
Pole；
The grid of 7th NMOS tube NM7 connects the drain electrode of the 4th PMOS tube PM4 and the 5th NMOS tube NM5 and as the electricity
The output end of clamp circuit, source electrode is pressed to connect the drain electrode of the source electrode and the 6th NMOS tube NM6 of the 5th NMOS tube NM5, drain electrode
Connect the source electrode of the first PMOS tube PM1, the second PMOS tube PM2, third PMOS tube PM3 and the 4th PMOS tube PM4 and as described
Second input terminal of voltage clamp circuit connects the voltage V of the first floating power supply railBST。
Specifically, it includes the 8th phase inverter INV8, the 9th phase inverter INV9, that the high pressure, which turns low voltage level shift circuit,
Ten phase inverter INV10, the 8th NMOS tube NM8, the 9th NMOS tube NM9, the tenth NMOS tube NM10, the 11st NMOS tube NM11,
12 NMOS tube NH1, the 13rd NMOS tube NH2, the 5th PMOS tube PM5, the 6th PMOS tube PM6, the 7th PMOS tube PM7, the 8th
PMOS tube PM8, the 9th PMOS tube PH1, the tenth PMOS tube PH2, third transistor Q3 and the 4th triode Q4, the high pressure turn low
The power rail of voltage level shift circuit is the second floating power supply rail BSTA and half-bridge switch node power rail SW；
The grid of 8th NMOS tube NM8 connects the input terminal of the 8th phase inverter INV8 and turns low voltage level as the high pressure
The input terminal of shift circuit, the grid of the drain electrode and the 6th PMOS tube PM6 of the 5th PMOS tube PM5 of drain electrode connection, source electrode connect
Meet the voltage V at the source electrode of the 9th NMOS tube NM9 and the half-bridge switch node of the GaN high speeds gate drive circuitSW；
The grid of 9th NMOS tube NM9 connects the output end of the 8th phase inverter INV8, the 5th PMOS tube PM5 of drain electrode connection
Grid, the 6th PMOS tube PM6 drain electrode and the 9th phase inverter INV9 input terminal；
The grid of 7th PMOS tube PM7 connects the input of the output end and the tenth phase inverter INV10 of the 9th phase inverter INV9
End, the source electrode of the 9th PMOS tube PH1 of drain electrode connection, source electrode connect the 5th PMOS tube PM5, the 6th PMOS tube PM6 and the 8th
The source electrode of PMOS tube PM8 and the voltage V for connecting the second floating power supply railBSTA；
The grid of 8th PMOS tube PM8 connects the output end of the tenth phase inverter INV10, drain electrode the tenth PMOS tube of connection
The source electrode of PH2；
The grid of 9th PMOS tube PH1 connects the grid of the tenth PMOS tube PH2, the 12nd NMOS tube NH1 of drain electrode connection
Drain electrode；
The grid of 13rd NMOS tube NH2 connects the grid of the 12nd NMOS tube NH1, drain electrode the tenth PMOS tube of connection
The drain electrode of PH2, source electrode connect the grid and the 11st of the base stage and collector, the tenth NMOS tube NM10 of the 4th triode Q4
The drain electrode of NMOS tube NM11 simultaneously exports the second logic control signal LV2；The emitter connection power supply electricity of 4th triode Q4
Press VDD；
The emitter connection supply voltage V of third transistor Q3DD, base stage is connected with collector and connects the 12nd NMOS
The source electrode of pipe NH1, the drain electrode of the tenth NMOS tube NM10 and the 11st NMOS tube NM11 grid and export the first logic control
Signal LV1 processed；The source electrode of tenth NMOS tube NM10 and the 11st NMOS tube NM11 is grounded.
Beneficial effects of the present invention are：Power rail provided by the invention can be realized using the design of double floating power supply rails
Meet GaN device for power switching simultaneously and work in safe voltage and turns high voltage level shift circuit with low pressure and possess enough dynamics
The floating power supply rail of range；The the first floating power supply rail BST conducts protected by bootstrap capacitor Cboot voltage difference clampers generated
The power rail of buffer circuit in GaN high speed gate drive circuits can protect GaN device for power switching gate source voltages to be operated in peace
In gamut；Generate not by bootstrap capacitor CbootSecond floating power supply rail BSTA of voltage difference clamper protection is as GaN high speeds
Low pressure in gate drive circuit turns the power rail of high voltage level shift circuit, it can be ensured with enough dynamic ranges.
Description of the drawings
Fig. 1 is the structural schematic diagram that enhanced GaN device for power switching is applied to the driving of half-bridge grid in the prior art.
Fig. 2 is a kind of structural schematic diagram of floating power supply rail suitable for GaN high speed gate drive circuits in embodiment.
Fig. 3 is that voltage clamp circuit in embodiment and high pressure turn the specific reality of low voltage level shift circuit Level Down
Existing mode.
Fig. 4 is to apply the present invention to high speed grid in embodiment a kind of typical case topology of IC is driven to build mode.
Specific implementation mode
Detailed description of the present invention technical solution in the following with reference to the drawings and specific embodiments：
Floating power supply rail proposed by the present invention suitable for GaN high speed gate drive circuits is set using double floating power supply rails
Meter, high pressure turn low voltage level shift circuit, voltage clamp circuit, logic control circuit and the first floating power supply rail generation circuit structure
At closed loop, for generating the first power rail BST；Two floating power supply rail generation circuits constitute open loop, for generating second source rail
BSTA。
The power rail of buffer circuit in GaN high speed gate drive circuits is to be protected by bootstrap capacitor Cboot voltage difference clampers
The first floating power supply rail BST and half-bridge switch node power rail SW, can protect GaN device for power switching gate source voltages work
In safe range；The power rail that low pressure turns high voltage level shift circuit is not by bootstrap capacitor CbootThe protection of voltage difference clamper
Second floating power supply rail BSTA and half-bridge switch node power rail SW, can ensure it with enough dynamic ranges.
It is illustrated in figure 2 a kind of realization method of the first floating power supply rail generation circuit and logic control circuit, first is floating
Dynamic power rail generation circuit is with active clamp defencive function and the upper Electricity Functional of initialization, including low tension switch pipe PM0, bootstrapping two
Pole pipe DBOOT, first resistor R1, NPN type triode, Zener Zener and second resistance R2, wherein first resistor R1 is initial
Change unit, NPN type triode, Zener Zener and second resistance R2 constitute active clamp unit；The grid of low tension switch pipe PM0
Pole connects the second control signal Ctrl2, source electrode connection as the input terminal of the first floating power supply rail generation circuit
One end of first resistor R1, the collector of NPN type triode and Zener Zener cathode and connect supply voltage VDD, leakage
The other end of pole connection first resistor R1, the emitter and bootstrap diode D of NPN type triodeBOOTAnode；Three pole of NPN type
The anode of the base stage connection Zener of pipe simultaneously passes through connection bootstrap diode D after second resistance R2BOOTAnode, bootstrap diode
DBOOTCathode as the first floating power supply rail generation circuit output end export the first floating power supply rail BST.
Logic control circuit includes latch up protection module, RS latch modules and buffer, and the latch up protection module includes
First phase inverter INV1, the second phase inverter INV2, third phase inverter INV3, the 4th phase inverter INV4, the 5th phase inverter INV5,
The input terminal of hex inverter INV6, the first NAND gate NAND1 and the second NAND gate NAND2, the first phase inverter INV1 connection second
The input terminal of phase inverter INV2 simultaneously connects the second logic control signal LV2, and output end connects the first NAND gate NAND1's
First input end；The input terminal of third phase inverter INV3 connects the output end of the second phase inverter INV2, output end connection second
The first input end of NAND gate NAND2；The input terminal of hex inverter INV6 connects the input terminal of the 4th phase inverter INV4 and company
The first logic control signal LV1 is met, output end connects the second input terminal of the second NAND gate NAND2；5th phase inverter
The input terminal of INV5 connects the output end of the 4th phase inverter INV4, and output end connects the second input of the first NAND gate NAND1
End；The RS latch includes third NAND gate NAND3 and the 4th NAND gate NAND4, and the first of the third NAND gate NAND3
Input terminal connects the output end of the first NAND gate NAND1, and second output terminal connects the output of the 4th NAND gate NAND4
End, output end connect the input terminal of the first input end and the buffer of the 4th NAND gate NAND4；4th NAND gate
The second input terminal of NAND4 connects the output end of the second NAND gate NAND2, and the output end of buffer is as the logic control
The output end output second control signal Ctrl2 of circuit processed.
It is illustrated in figure 3 voltage clamp circuit and high pressure turns a kind of realization of low voltage level shift circuit (Level Down)
Mode, voltage clamp circuit include the 7th phase inverter INV7,3rd resistor R3, the 4th resistance R4, the 5th resistance R5, the 6th resistance
R6, the 7th resistance R7, the first triode Q1, the second triode Q2, the first NMOS tube NM1, the second NMOS tube NM2, the 3rd NMOS
Pipe NM3, the 4th NMOS tube NM4, the 5th NMOS tube NM5, the 6th NMOS tube NM6, the 7th NMOS tube NM7, the first PMOS tube PM1,
Second PMOS tube PM2, third PMOS tube PM3 and the 4th PMOS tube PM4；The input terminal of 7th phase inverter INV7 connects the 4th PMOS
The leakage of the grid and third PMOS tube PM3 and the 4th NMOS tube NM4 of pipe PM4, the 5th NMOS tube NM5 and the 6th NMOS tube NM6
Pole, output end connect the grid of the first PMOS tube PM1；The grid of first NMOS tube NM1 connects the grid of the second NMOS tube NM2
With drain electrode and the collector of the first triode Q1, the grid and drain electrode and third of the second PMOS tube PM2 of drain electrode connection
The grid of PMOS tube PM3, source electrode connect the second NMOS tube NM2, third NMOS tube NM3, the 4th NMOS tube NM4 and the 6th NMOS
The source electrode of pipe NM6 and first input end as the voltage clamp circuit connect the half-bridge of the GaN high speeds gate drive circuit
Voltage V at switching nodeSW；3rd resistor R3 is connected between the source electrode and drain electrode of the first PMOS tube PM1, the 4th resistance R4 and
Five resistance R5 series connection are attempted by between the drain electrode of the first PMOS tube PM1 and the source electrode of the first NMOS tube NM1, series connection point connection the
The base stage of one triode Q1 and the second triode Q2；6th resistance R6 and the 7th resistance R7 connects and connects the first PMOS tube PM1
Source electrode and the emitter of the first triode Q1 between, series connection point connect the second triode Q2 emitter；Third NMOS tube
The grid leak short circuit of NM3 and the grid of the collector and the 4th NMOS tube NM4 of the second triode Q2 of connection；7th NMOS tube NM7's
Grid connects the drain electrode of the 4th PMOS tube PM4 and the 5th NMOS tube NM5 and as the output end of the voltage clamp circuit, source
Pole connects the drain electrode of the source electrode and the 6th NMOS tube NM6 of the 5th NMOS tube NM5, the first PMOS tube PM1 of drain electrode connection, second
PMOS tube PM2, the source electrode of third PMOS tube PM3 and the 4th PMOS tube PM4 and the second input as the voltage clamp circuit
End connects the voltage V of the first floating power supply railBST。
Voltage clamp circuit is mainly made of band-gap reference circuit and current comparator.First triode Q1 and the two or three pole
Pipe Q2 constitutes benchmark core, is acquired certainly by 3rd resistor R3, the 4th resistance R4 and the 5th resistance the R5 divider resistance constituted
Lift capacitance CbootThe information of voltage of upper bottom crown BST-SW, the level input the base of the first triode Q1 and the second triode Q2
Area, since the mutual conductance on the first triode Q1 and the road at the second places triode Q2 is different, benchmark core passes through the first triode Q1
It is inconsistent with the size of current of the second triode Q2 mirror images to current comparator, then when the pressure difference difference of BST-SW, voltage clamping
The first control signal Ctrl1 of the output of circuit can be high or be low.
It includes the 8th phase inverter INV8, the 9th phase inverter INV9, the tenth phase inverter that high pressure, which turns low voltage level shift circuit,
INV10, the 8th NMOS tube NM8, the 9th NMOS tube NM9, the tenth NMOS tube NM10, the 11st NMOS tube NM11, the 12nd NMOS
Pipe NH1, the 13rd NMOS tube NH2, the 5th PMOS tube PM5, the 6th PMOS tube PM6, the 7th PMOS tube PM7, the 8th PMOS tube
PM8, the 9th PMOS tube PH1, the tenth PMOS tube PH2, third transistor Q3 and the 4th triode Q4, the high pressure turn low voltage level
The power rail of shift circuit is the second floating power supply rail BSTA and half-bridge switch node power rail SW；The grid of 8th NMOS tube NM8
Pole connects the input terminal of the 8th phase inverter INV8 and turns the input terminal of low voltage level shift circuit as the high pressure, and drain electrode connects
Drain electrode and the grid of the 6th PMOS tube PM6 of the 5th PMOS tube PM5 are connect, source electrode connects source electrode and the institute of the 9th NMOS tube NM9
State the voltage V at the half-bridge switch node of GaN high speed gate drive circuitsSW；The grid of 9th NMOS tube NM9 connects the 8th phase inverter
The output end of INV8, the drain electrode of the grid, the 6th PMOS tube PM6 of the 5th PMOS tube PM5 of drain electrode connection and the 9th phase inverter
The input terminal of INV9；The grid of 7th PMOS tube PM7 connects the output end and the tenth phase inverter INV10 of the 9th phase inverter INV9
Input terminal, drain electrode connection the 9th PMOS tube PH1 source electrode, source electrode connect the 5th PMOS tube PM5, the 6th PMOS tube PM6 and
The source electrode of 8th PMOS tube PM8 and the voltage V for connecting the second floating power supply railBSTA；The grid of 8th PMOS tube PM8 connects
The output end of tenth phase inverter INV10, the source electrode of the tenth PMOS tube PH2 of drain electrode connection；The grid of 9th PMOS tube PH1 connects
The grid of tenth PMOS tube PH2, the drain electrode of the 12nd NMOS tube NH1 of drain electrode connection；The grid of 13rd NMOS tube NH2 connects
The grid of 12nd NMOS tube NH1, the drain electrode of the tenth PMOS tube PH2 of drain electrode connection, source electrode connect the 4th triode Q4's
Base stage and collector, the grid of the tenth NMOS tube NM10 and the 11st NMOS tube NM11 drain electrode and export second logic
Control signal LV2；The emitter connection supply voltage V of 4th triode Q4DD；The emitter connection power supply electricity of third transistor Q3
Press VDD, base stage is connected with collector and connects the drain electrode and the tenth of the source electrode, the tenth NMOS tube NM10 of the 12nd NMOS tube NH1
The grid of one NMOS tube NM11 simultaneously exports the first logic control signal LV1；Tenth NMOS tube NM10 and the 11st NMOS tube
The source electrode of NM11 is grounded.
The operation principle of the generation of first power rail BST is：Voltage clamp circuit is used for bootstrap capacitor CbootPole up and down
The voltage difference V of plateBST-VSWIt carries out real-time voltage detection and generates first control signal Ctrl1, high pressure turns low voltage level displacement electricity
First control signal Ctrl1 is gone to low-tension supply rail and makees logic control by road (Level Down), generates the first logic control letter
Number LV1 and the second logic control signal LV2 input logic control circuits, logic control circuit generate second control signal Ctrl2
Control the bootstrap diode D in the first floating power supply rail generation circuitBOOTAnode is to low-tension supply rail VDDBetween low tension switch
Pipe PM0.
When detecting bootstrap capacitor CbootOn under-voltage when, supply voltage VDDPass through bootstrap diode DBOOTTo bootstrapping
Capacitance CbootCharging；When detecting bootstrap capacitor CbootOn electric voltage over press when, deenergization voltage VDDTo bootstrap capacitor Cboot's
Charging path.The first control signal Ctrl1 of voltage clamp circuit output turns low voltage level shift circuit (Level by high pressure
Down low-tension supply rail) is gone to, second control signal Ctrl2 control logic control circuits are exported.The true value of logic control circuit
Table is as follows, and wherein A indicates that the input signal of the first phase inverter INV1, B indicate the input signal of the second phase inverter INV2,
Set indicates that the output signal of the first NAND gate NAND1, Reset indicate that the output signal of the second NAND gate NAND2, Q indicate third
The output signal of NAND gate NAND3：
The logical design can make the RS latch in logic control circuit still can under the common mode noise effects of SW nodes
Enough normal works.
In bootstrap diode DBOOTAnode and VDDIt is inserted into low tension switch pipe PM0 between source bias, works as voltage clamp circuit
Detect bootstrap capacitor CbootWhen voltage difference BST-SW overvoltages between upper bottom crown, output first control signal Ctrl1 passes through
High pressure turns low voltage level shift circuit (Level Down) and goes to low-pressure rail, makees the input of logic control circuit；Logic control electricity
The output signal on road is controlled by first control signal Ctrl1, is generated second control signal Ctrl2 and is rapidly switched off low tension switch pipe
PM0 realizes supply voltage VDDTo bootstrap capacitor CbootCharging path disconnection；Front stage circuits detect bootstrap capacitor CbootOn
When voltage difference BST-SW between bottom crown is under-voltage, logic control circuit exports second control signal Ctrl2 and opens low tension switch
Pipe PM0, charging path are equivalent to bootstrap diode DBOOTWith bootstrap capacitor CbootCascade bootstrap charge circuit access, when GaN high speed grid
The upper tube of driving circuit turns off, half-bridge switch node SW voltage drops down to ground potential VSS and it is following after, charging paths conducting is opened
Begin to give bootstrap capacitor CbootCharging.
Above-mentioned workflow realizes bootstrap capacitor CbootThe detection of both ends level and bootstrap capacitor CbootControlled charging
Process.But due to the access of low tension switch pipe PM0, lead to low tension switch pipe PM0 when off, body diode and two poles of bootstrapping
Pipe DBOOTA pair of of back to back diode pair is formed, V is causedANode (i.e. bootstrap diode DBOOTAnode) become high resistant node, meeting
So that：1. entire driving chip powers on, bootstrap capacitor CbootTo supply voltage VDDFor high resistance path, can not normally power on；2.
After entire driving chip normal work, upper power tube is quickly switched on and off, and the dv/dt common modes of the first floating power supply rail BST are made an uproar
Sound crosstalk is very violent, high resistant node VAIt is easy to be interfered, influences circuit normal work.Therefore it is produced in the first floating power supply rail
In raw circuit, accessing big resistance i.e. first resistor R1 makes bootstrap capacitor CbootIt can initialize, BST-SW is made to reach operating voltage；Together
Receiving pipe Zener, second resistance R2 and NPN triode constitutes active clamp circuit to VANode charges, low tension switch pipe PM0's
Body diode constitutes active access of releasing to VANode discharge offsets the dv/dt common-mode noises of the first floating power supply rail BST to VA
The crosstalk of node voltage.
In first floating power supply rail generation circuit, the operation principle of active clamp circuit is as follows：When the first floating power supply rail
When level declines rapidly at BST, VANode is generated by negative dv/dt crosstalks to very low voltage, Zener Zenar reverse breakdowns
Pressure drop keep the base stage of NPN triode and collector reverse-biased；Flowing through the electric current of second resistance R2 simultaneously makes the base area of NPN triode
Pressure drop is generated between emitter region, BE ties positively biased, the conducting of NPN triode base area；Active clamp access is opened at this time, is had
In above formula, k is Boltzmann constant, and T is environment temperature, at room temperature kT=26mV, and β is the amplification of NPN triode
Coefficient, IZenarAnd IR2To flow through the electric current of Zener Zenar and second resistance R2, (IZenar-IR2) represent inflow NPN triode
The electric current of base stage, IEFor NPN triode collector current, when active clamp access is opened to VANode charges, and it is floating to offset first
The dv/dt common-mode noises of dynamic power rail BST are to VAThe crosstalk of node voltage.
It is that the second floating power supply rail provided by the invention for meeting drive signal high speed transmitting generates as shown in Figure 1
The schematic diagram of circuit, including the first diode D1, the second diode D2 and bootstrap capacitor Cboot, the anode company of the first diode D1
Meet supply voltage VDD, cathode connect the second diode D2 cathode simultaneously generate the second floating power supply rail BSTA；Bootstrap capacitor
Top crown connects the anode of the second diode D2 and the output end of the first floating power supply rail generation circuit, bottom crown connection
The half-bridge switch node SW of GaN high speed gate drive circuits.
Upper tube open stage, the second diode D2 forward conductions, the first diode D1 shutdowns, at this time
VBST-VD2=VBSTA
Wherein VD2For forward voltage drops of the second diode D2 in conducting.
And turned off in upper tube, in the dead time that down tube is opened, it can be reduced to since the level of the first power rail BST is minimum
2V, the second diode D2 shutdowns at this time, the first diode D1 unlatchings, the current potential of the second floating power supply rail BSTA of generation is by power supply
Voltage VDDIt provides
VBSTA=VDD-VD1
Wherein VD1For forward voltage drops of the first diode D1 in conducting.
The preferred implementation of first diode D1 and the second diode D2 is：D1 is high-voltage diode, and negative terminal is to just
The pressure resistance of Vin+VDD sizes need to be ensured in bootstrapping by holding；D2 is low pressure diode, and the pressure resistance of negative terminal to anode does not exceed SW
Negative pressure value | VSW|, but its negative terminal and anode ensure the need of substrate chip is most saved in the pressure resistance of Vin+VDD sizes, this mode
Area, parasitic parameter is minimum, and circuit is accordingly most fast.
Fig. 4 is that the present invention drives a kind of typical case topology of IC to build applied to GaN high speed grid.Voltage clamping therein
Circuit, high pressure turn low voltage level shift circuit (Level Down), logic control circuit and the first floating power supply rail and generate electricity
The function that road realizes bootstrap charge circuit and powers to gate drive circuit jointly.For in dead time, the first floating power supply rail BST
The current potential at place because GaN device for power switching source and drain negative pressure appearance occurs dropped to low level the problem of, the present invention devises one
Power rail of the level range from BSTA to SW turns high voltage level shift circuit (Level to the low pressure in half-bridge gate drive circuit
Up it) powers, since in dead time, the level of second source rail BSTA is not negative by GaN device for power switching source-drain voltages
The influence of situation, the dynamic range that low pressure turns high voltage level shift circuit (Level Up) are guaranteed, and traditional low pressure turns
High voltage level shift circuit (Level Up) and driving logic circuit are applicable to the driving application of GaN high speed grid.
The present invention is directed to the physical characteristic of enhanced GaN device for power switching, devises a kind of confession of double floating power supply rails
Electric scheme eliminates enhanced GaN device for power switching and is born to what half-bridge gate drive circuit worked under high-speed high-power application
Face is rung.It is worth noting that system control mode and the physical circuit design that the present invention uses can also be applied to Si power and opens
In the driving circuit for closing device and other wide bandgap semiconductor switching devices (such as SiC device for power switching), specifically, being directed to
The gate drive circuit of Si device for power switching, lower power tube body diode afterflow in dead time, SW node voltages are at dead zone
The interior negative pressure that can drop to -0.7V, the present disclosure applies equally to this kind applications.
Those skilled in the art can make various do not depart from originally according to the technical disclosures disclosed by the invention
Various other specific variations and combinations of essence are invented, these variations and combinations are still within the scope of the present invention.
Claims (6)
1. the floating power supply rail suitable for GaN high speed gate drive circuits, which is characterized in that turn low voltage level displacement electricity including high pressure
Road, voltage clamp circuit, logic control circuit, the first floating power supply rail generation circuit and the second floating power supply rail generation circuit,
The second floating power supply rail generation circuit includes the first diode (D1), the second diode (D2) and bootstrap capacitor
(Cboot), the first diode (D1) anode connection supply voltage (VDD), cathode connects the second diode (D2) cathode and production
Raw second floating power supply rail (BSTA)；Bootstrap capacitor (Cboot) top crown connect the second diode (D2) anode and described
The output end of first floating power supply rail generation circuit, bottom crown connect the half-bridge switch section of the GaN high speeds gate drive circuit
Point (SW)；
Two input terminals of the voltage clamp circuit are separately connected the bootstrap capacitor (Cboot) top crown and bottom crown, use
In the detection bootstrap capacitor (Cboot) polar plate voltage up and down difference and export first control signal (Ctrl1) to the high pressure turn
The input terminal of low voltage level shift circuit；
The high pressure turns low voltage level shift circuit and the first control signal (Ctrl1) is gone to low-tension supply rail, output the
One logic control signal (LV1) and the second logic control signal (LV2) and two input terminals for connecting the logic control circuit；
The logic control circuit is generated according to first logic control signal (LV1) and the second logic control signal (LV2)
Second control signal (Ctrl2) and the input terminal for connecting the first floating power supply rail generation circuit；
The first floating power supply rail generation circuit is for generating the first floating power supply rail (BST).
2. the floating power supply rail according to claim 1 suitable for GaN high speed gate drive circuits, which is characterized in that described
GaN high speed gate drive circuits include buffer circuit and low pressure turns high voltage level shift circuit, and the power rail of the buffer circuit is
First floating power supply rail (BST) and half-bridge switch node power rail (SW), the low pressure turn the power supply of high voltage level shift circuit
Rail is the second floating power supply rail (BSTA) and half-bridge switch node power rail (SW).
3. the floating power supply rail according to claim 1 suitable for GaN high speed gate drive circuits, which is characterized in that described
First floating power supply rail generation circuit includes low tension switch pipe (PM0), bootstrap diode (DBOOT), first resistor (R1), NPN type
Triode, Zener (Zener) and second resistance (R2),
Input terminal connection second control of the grid of low tension switch pipe (PM0) as the first floating power supply rail generation circuit
Signal (Ctrl2) processed, one end of source electrode connection first resistor (R1), the collector and Zener (Zener) of NPN type triode
Cathode and connect supply voltage (VDD), drain electrode connection first resistor (R1) the other end, NPN type triode emitter
With bootstrap diode (DBOOT) anode；
The anode of the base stage connection Zener of NPN type triode simultaneously connects bootstrap diode (D afterwards by second resistance (R2)BOOT)
Anode, bootstrap diode (DBOOT) cathode it is floating as the output end output first of the first floating power supply rail generation circuit
Dynamic power rail (BST).
4. the floating power supply rail according to claim 1 suitable for GaN high speed gate drive circuits, which is characterized in that described
Logic control circuit includes latch up protection module, RS latch modules and buffer,
The latch up protection module includes the first phase inverter (INV1), the second phase inverter (INV2), third phase inverter (INV3), the
Four phase inverters (INV4), the 5th phase inverter (INV5), hex inverter (INV6), the first NAND gate (NAND1) and second with it is non-
Door (NAND2),
The input terminal of first phase inverter (INV1) connects the input terminal of the second phase inverter (INV2) and connects the second logic control
Signal (LV2) processed, output end connect the first input end of the first NAND gate (NAND1)；The input of third phase inverter (INV3)
The output end of end the second phase inverter of connection (INV2), output end connect the first input end of the second NAND gate (NAND2)；
The input terminal of hex inverter (INV6) connects the input terminal of the 4th phase inverter (INV4) and connects the first logic control
Signal (LV1) processed, output end connect the second input terminal of the second NAND gate (NAND2)；The input of 5th phase inverter (INV5)
The output end of the 4th phase inverter (INV4) of end connection, output end connect the second input terminal of the first NAND gate (NAND1)；
The RS latch includes third NAND gate (NAND3) and the 4th NAND gate (NAND4), the third NAND gate
(NAND3) first input end connects the output end of first NAND gate (NAND1), second output terminal connection the 4th with it is non-
The output end of door (NAND4), output end connect the input of the first input end and the buffer of the 4th NAND gate (NAND4)
End；Second input terminal of the 4th NAND gate (NAND4) connects the output end of second NAND gate (NAND2), buffer it is defeated
Output end output second control signal (Ctrl2) of the outlet as the logic control circuit.
5. the floating power supply rail according to claim 1 suitable for GaN high speed gate drive circuits, which is characterized in that described
Voltage clamp circuit includes the 7th phase inverter (INV7), 3rd resistor (R3), the 4th resistance (R4), the 5th resistance (R5), the 6th
Resistance (R6), the 7th resistance (R7), the first triode (Q1), the second triode (Q2), the first NMOS tube (NM1), the 2nd NMOS
Manage (NM2), third NMOS tube (NM3), the 4th NMOS tube (NM4), the 5th NMOS tube (NM5), the 6th NMOS tube (NM6), the 7th
NMOS tube (NM7), the first PMOS tube (PM1), the second PMOS tube (PM2), third PMOS tube (PM3) and the 4th PMOS tube (PM4)；
The input terminal of 7th phase inverter (INV7) connects the 4th PMOS tube (PM4), the 5th NMOS tube (NM5) and the 6th NMOS tube
(NM6) drain electrode of grid and third PMOS tube (PM3) and the 4th NMOS tube (NM4), output end connect the first PMOS tube
(PM1) grid；
The grid of first NMOS tube (NM1) connects the grid and drain electrode and the first triode (Q1) of the second NMOS tube (NM2)
Collector, the grid and the grid of drain electrode and third PMOS tube (PM3) of drain electrode the second PMOS tube of connection (PM2), source electrode
Connect the source electrode of the second NMOS tube (NM2), third NMOS tube (NM3), the 4th NMOS tube (NM4) and the 6th NMOS tube (NM6) simultaneously
First input end as the voltage clamp circuit connects the electricity at the half-bridge switch node of the GaN high speeds gate drive circuit
Press (VSW)；
3rd resistor (R3) is connected between the source electrode and drain electrode of the first PMOS tube (PM1), the 4th resistance (R4) and the 5th resistance
(R5) series connection is attempted by between the drain electrode of the first PMOS tube (PM1) and the source electrode of the first NMOS tube (NM1), series connection point connection the
The base stage of one triode (Q1) and the second triode (Q2)；
6th resistance (R6) and the 7th resistance (R7) connect and connect the source electrode and the first triode (Q1) of the first PMOS tube (PM1)
Emitter between, series connection point connect the second triode (Q2) emitter；
The grid leak short circuit of third NMOS tube (NM3) and the collector and the 4th NMOS tube (NM4) for connecting the second triode (Q2)
Grid；
The grid of 7th NMOS tube (NM7) connects the drain electrode of the 4th PMOS tube (PM4) and the 5th NMOS tube (NM5) and as described
The output end of voltage clamp circuit, source electrode connect the drain electrode of the source electrode and the 6th NMOS tube (NM6) of the 5th NMOS tube (NM5),
Its drain the first PMOS tube of connection (PM1), the second PMOS tube (PM2), third PMOS tube (PM3) and the 4th PMOS tube (PM4)
Source electrode and the second input terminal as the voltage clamp circuit connect the voltage (V of the first floating power supply railBST)。
6. the floating power supply rail according to claim 1 suitable for GaN high speed gate drive circuits, which is characterized in that described
It includes the 8th phase inverter (INV8), the 9th phase inverter (INV9), the tenth phase inverter that high pressure, which turns low voltage level shift circuit,
(INV10), the 8th NMOS tube (NM8), the 9th NMOS tube (NM9), the tenth NMOS tube (NM10), the 11st NMOS tube (NM11),
12nd NMOS tube (NH1), the 13rd NMOS tube (NH2), the 5th PMOS tube (PM5), the 6th PMOS tube (PM6), the 7th PMOS
Manage (PM7), the 8th PMOS tube (PM8), the 9th PMOS tube (PH1), the tenth PMOS tube (PH2), third transistor (Q3) and the 4th
Triode (Q4), the power rail that the high pressure turns low voltage level shift circuit are the second floating power supply rail (BSTA) and half-bridge switch
Node power rail (SW)；
The grid of 8th NMOS tube (NM8) connects the input terminal of the 8th phase inverter (INV8) and turns low voltage level as the high pressure
The input terminal of shift circuit, the grid of the drain electrode and the 6th PMOS tube (PM6) of drain electrode the 5th PMOS tube (PM5) of connection, source
Pole connects the voltage (V at the source electrode of the 9th NMOS tube (NM9) and the half-bridge switch node of the GaN high speeds gate drive circuitSW)；
The grid of 9th NMOS tube (NM9) connects the output end of the 8th phase inverter (INV8), drain electrode the 5th PMOS tube of connection
(PM5) input terminal of the drain electrode and the 9th phase inverter (INV9) of grid, the 6th PMOS tube (PM6)；
The grid of 7th PMOS tube (PM7) connect the 9th phase inverter (INV9) output end and the tenth phase inverter (INV10) it is defeated
Enter end, the source electrode of drain electrode the 9th PMOS tube (PH1) of connection, source electrode connects the 5th PMOS tube (PM5), the 6th PMOS tube
(PM6) and the source electrode of the 8th PMOS tube (PM8) and the voltage (V for connecting the second floating power supply railBSTA)；
The grid of 8th PMOS tube (PM8) connects the output end of the tenth phase inverter (INV10), drain electrode the tenth PMOS tube of connection
(PH2) source electrode；
The grid of 9th PMOS tube (PH1) connects the grid of the tenth PMOS tube (PH2), drain electrode the 12nd NMOS tube of connection
(NH1) drain electrode；
The grid of 13rd NMOS tube (NH2) connects the grid of the 12nd NMOS tube (NH1), drain electrode the tenth PMOS tube of connection
(PH2) drain electrode, source electrode connect the 4th triode (Q4) base stage and collector, the tenth NMOS tube (NM10) grid and
The drain electrode of 11st NMOS tube (NM11) simultaneously exports second logic control signal (LV2)；The transmitting of 4th triode (Q4)
Pole connects supply voltage (VDD)；
The emitter connection supply voltage (V of third transistor (Q3)DD), base stage is connected with collector and connects the 12nd NMOS
It manages source electrode, the drain electrode of the tenth NMOS tube (NM10) and the grid of the 11st NMOS tube (NM11) of (NH1) and exports described first
Logic control signal (LV1)；The source electrode of tenth NMOS tube (NM10) and the 11st NMOS tube (NM11) is grounded.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810309410.2A CN108494234B (en) | 2018-04-09 | 2018-04-09 | Floating power rail suitable for GaN high-speed gate drive circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810309410.2A CN108494234B (en) | 2018-04-09 | 2018-04-09 | Floating power rail suitable for GaN high-speed gate drive circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108494234A true CN108494234A (en) | 2018-09-04 |
| CN108494234B CN108494234B (en) | 2020-05-01 |
Family
ID=63315294
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810309410.2A Active CN108494234B (en) | 2018-04-09 | 2018-04-09 | Floating power rail suitable for GaN high-speed gate drive circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108494234B (en) |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109245535A (en) * | 2018-11-20 | 2019-01-18 | 广州市力驰微电子科技有限公司 | Level switch module suitable for power management |
| CN109462388A (en) * | 2018-10-22 | 2019-03-12 | 京信通信系统（中国）有限公司 | GaN HEMT control circuit |
| CN109495095A (en) * | 2018-11-27 | 2019-03-19 | 黄山市祁门新飞电子科技发展有限公司 | Enhanced GaN power device gate drive circuit with defencive function |
| CN109742946A (en) * | 2019-01-22 | 2019-05-10 | 电子科技大学 | A kind of DCR sample circuit applied to wide output voltage range Buck converter |
| CN109818608A (en) * | 2019-01-28 | 2019-05-28 | 电子科技大学 | A kind of level displacement circuit of the high common-mode noise anti-interference of high speed |
| CN110994996A (en) * | 2019-12-31 | 2020-04-10 | 思瑞浦微电子科技（苏州）股份有限公司 | Asynchronous step-down DCDC chip and bootstrap circuit based on asynchronous step-down DCDC chip |
| CN111049100A (en) * | 2019-12-10 | 2020-04-21 | 中国电子科技集团公司第五十八研究所 | Bootstrap circuit with clamping function |
| CN112311211A (en) * | 2020-10-22 | 2021-02-02 | 浙江大学 | Drive control chip for GaN HEMT power device |
| CN113595389A (en) * | 2020-04-30 | 2021-11-02 | 圣邦微电子（北京）股份有限公司 | High-side tube control signal potential translation improved circuit for preventing electric penetration on Buck circuit |
| CN113849025A (en) * | 2021-09-27 | 2021-12-28 | 电子科技大学 | Power rail generating circuit |
| CN113949268A (en) * | 2021-10-22 | 2022-01-18 | 中国电子科技集团公司第五十八研究所 | Low-voltage-to-high-voltage level shift circuit with high-voltage power supply domain ground capable of floating |
| CN115268543A (en) * | 2022-06-27 | 2022-11-01 | 西安电子科技大学 | Mutual bias double-voltage-rail generation circuit |
| CN116841342A (en) * | 2023-07-27 | 2023-10-03 | 电子科技大学 | Anti-noise band gap reference source suitable for GaN half-bridge gate driving system |
| CN117318689A (en) * | 2023-11-28 | 2023-12-29 | 成都市硅海武林科技有限公司 | Bootstrap driving circuit of full-bridge and half-bridge circuit high-side power tube |
| CN117477918A (en) * | 2023-12-27 | 2024-01-30 | 成都氮矽科技有限公司 | Drive signal input detection circuit, gaN gate driver, and MOSFET gate driver |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102868295A (en) * | 2012-09-10 | 2013-01-09 | 西安启芯微电子有限公司 | Bootstrap type charging circuit applied to high-voltage DC-DC (Direct Current-Direct Current) convertor |
| CN104170254A (en) * | 2012-03-16 | 2014-11-26 | 德克萨斯仪器股份有限公司 | System and apparatus for driver circuit for protection of gates of GaN FETs |
| CN105048776A (en) * | 2014-04-28 | 2015-11-11 | 三菱电机株式会社 | Gate drive circuit |
| WO2017100657A1 (en) * | 2015-12-11 | 2017-06-15 | Freebird Semiconductor Corporation | A voltage detection circuit |
| CN107078736A (en) * | 2014-10-10 | 2017-08-18 | 宜普电源转换公司 | The QRR of high voltage zero bootstrapping supply |
-
2018
- 2018-04-09 CN CN201810309410.2A patent/CN108494234B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104170254A (en) * | 2012-03-16 | 2014-11-26 | 德克萨斯仪器股份有限公司 | System and apparatus for driver circuit for protection of gates of GaN FETs |
| CN102868295A (en) * | 2012-09-10 | 2013-01-09 | 西安启芯微电子有限公司 | Bootstrap type charging circuit applied to high-voltage DC-DC (Direct Current-Direct Current) convertor |
| CN105048776A (en) * | 2014-04-28 | 2015-11-11 | 三菱电机株式会社 | Gate drive circuit |
| CN107078736A (en) * | 2014-10-10 | 2017-08-18 | 宜普电源转换公司 | The QRR of high voltage zero bootstrapping supply |
| WO2017100657A1 (en) * | 2015-12-11 | 2017-06-15 | Freebird Semiconductor Corporation | A voltage detection circuit |
Non-Patent Citations (1)
| Title |
|---|
| RENHUI YAN等: ""A GaN HEMTs half-bridge driver with bandgap reference comparator clamping for high-frequency DC-DC converter"", 《IECON 2017-43RD ANNUAL CONFERENCE OF THE IEEE INDUSTRIAL ELECTRONICS SOCIETY》 * |
Cited By (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109462388A (en) * | 2018-10-22 | 2019-03-12 | 京信通信系统（中国）有限公司 | GaN HEMT control circuit |
| CN109245535A (en) * | 2018-11-20 | 2019-01-18 | 广州市力驰微电子科技有限公司 | Level switch module suitable for power management |
| CN109495095A (en) * | 2018-11-27 | 2019-03-19 | 黄山市祁门新飞电子科技发展有限公司 | Enhanced GaN power device gate drive circuit with defencive function |
| CN109742946A (en) * | 2019-01-22 | 2019-05-10 | 电子科技大学 | A kind of DCR sample circuit applied to wide output voltage range Buck converter |
| CN109818608A (en) * | 2019-01-28 | 2019-05-28 | 电子科技大学 | A kind of level displacement circuit of the high common-mode noise anti-interference of high speed |
| CN111049100A (en) * | 2019-12-10 | 2020-04-21 | 中国电子科技集团公司第五十八研究所 | Bootstrap circuit with clamping function |
| CN111049100B (en) * | 2019-12-10 | 2021-09-03 | 中国电子科技集团公司第五十八研究所 | Bootstrap circuit with clamping function |
| CN110994996B (en) * | 2019-12-31 | 2021-03-23 | 思瑞浦微电子科技（苏州）股份有限公司 | Asynchronous step-down DCDC chip and bootstrap circuit based on asynchronous step-down DCDC chip |
| CN110994996A (en) * | 2019-12-31 | 2020-04-10 | 思瑞浦微电子科技（苏州）股份有限公司 | Asynchronous step-down DCDC chip and bootstrap circuit based on asynchronous step-down DCDC chip |
| CN113595389B (en) * | 2020-04-30 | 2023-04-11 | 圣邦微电子（北京）股份有限公司 | High-side tube control signal potential translation improved circuit for preventing electric penetration on Buck circuit |
| CN113595389A (en) * | 2020-04-30 | 2021-11-02 | 圣邦微电子（北京）股份有限公司 | High-side tube control signal potential translation improved circuit for preventing electric penetration on Buck circuit |
| CN112311211A (en) * | 2020-10-22 | 2021-02-02 | 浙江大学 | Drive control chip for GaN HEMT power device |
| CN112311211B (en) * | 2020-10-22 | 2021-10-15 | 浙江大学 | Drive control chip for GaN HEMT power device |
| CN113849025A (en) * | 2021-09-27 | 2021-12-28 | 电子科技大学 | Power rail generating circuit |
| CN113849025B (en) * | 2021-09-27 | 2022-10-04 | 电子科技大学 | Power rail generating circuit |
| CN113949268A (en) * | 2021-10-22 | 2022-01-18 | 中国电子科技集团公司第五十八研究所 | Low-voltage-to-high-voltage level shift circuit with high-voltage power supply domain ground capable of floating |
| CN113949268B (en) * | 2021-10-22 | 2023-09-08 | 中国电子科技集团公司第五十八研究所 | High-voltage power domain ground floatable low-voltage to high-voltage level shift circuit |
| CN115268543A (en) * | 2022-06-27 | 2022-11-01 | 西安电子科技大学 | Mutual bias double-voltage-rail generation circuit |
| CN115268543B (en) * | 2022-06-27 | 2024-04-16 | 西安电子科技大学 | Mutual bias dual-voltage rail generating circuit |
| CN116841342A (en) * | 2023-07-27 | 2023-10-03 | 电子科技大学 | Anti-noise band gap reference source suitable for GaN half-bridge gate driving system |
| CN116841342B (en) * | 2023-07-27 | 2024-03-26 | 电子科技大学 | Anti-noise band gap reference source suitable for GaN half-bridge gate driving system |
| CN117318689A (en) * | 2023-11-28 | 2023-12-29 | 成都市硅海武林科技有限公司 | Bootstrap driving circuit of full-bridge and half-bridge circuit high-side power tube |
| CN117318689B (en) * | 2023-11-28 | 2024-03-22 | 成都市硅海武林科技有限公司 | Bootstrap driving circuit of full-bridge and half-bridge circuit high-side power tube |
| CN117477918A (en) * | 2023-12-27 | 2024-01-30 | 成都氮矽科技有限公司 | Drive signal input detection circuit, gaN gate driver, and MOSFET gate driver |
| CN117477918B (en) * | 2023-12-27 | 2024-03-29 | 成都氮矽科技有限公司 | Drive signal input detection circuit, gaN gate driver, and MOSFET gate driver |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108494234B (en) | 2020-05-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108494234A (en) | Floating power supply rail suitable for GaN high speed gate drive circuits | |
| KR101582721B1 (en) | Level shifter for high density integrated circuits | |
| CN109088532A (en) | A kind of current mode segmentation gate driving circuit with active clamp | |
| CN204465489U (en) | A kind of New Low Voltage electrify restoration circuit | |
| JPS63112893A (en) | Semiconductor integrated circuit | |
| CN102208909A (en) | Level shift circuit | |
| CN106411300A (en) | Power-on reset circuit | |
| CN112688539A (en) | High-side switch driving circuit with short circuit detection function | |
| CN206672033U (en) | A kind of reset circuit | |
| CN101951246B (en) | Quiescent voltage level restorer | |
| CN107786191A (en) | A kind of electrification reset automatic shutoff circuit | |
| CN106571796B (en) | Electrification reset circuit and method | |
| CN104158388B (en) | High-end MOSFET driving circuit | |
| CN109245535A (en) | Level switch module suitable for power management | |
| US9209808B2 (en) | Asymmetrical bus keeper | |
| CN103051325B (en) | Pull-up resistance circuit for preventing reverse current filling | |
| CN104270142A (en) | Input/output buffer for multiple voltage domains | |
| CN108322208A (en) | Signaling interface and its signal interface circuit for positive/negative voltage signal input | |
| KR920009708B1 (en) | Semiconductor logic circuit | |
| CN104716938B (en) | A kind of grid follow imput output circuit | |
| CN104579308A (en) | Restoring circuit for lowering negative bias temperature instability of level switching circuit | |
| NL2034089B1 (en) | A CMOS Process Compatible Interface Chip power-failure Protection Circuit and The Method Thereof | |
| CN210168022U (en) | Multi-input open-drain output circuit | |
| CN104202024A (en) | Open drain circuit suitable of high-voltage floating ground | |
| CN109213253A (en) | A kind of quick High Precision Low Temperature drift strong pull-down current generating circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |