CN109088532A - A kind of current mode segmentation gate driving circuit with active clamp - Google Patents
A kind of current mode segmentation gate driving circuit with active clamp Download PDFInfo
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- CN109088532A CN109088532A CN201811072014.9A CN201811072014A CN109088532A CN 109088532 A CN109088532 A CN 109088532A CN 201811072014 A CN201811072014 A CN 201811072014A CN 109088532 A CN109088532 A CN 109088532A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
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Abstract
A kind of current mode segmentation gate driving circuit with active clamp, belongs to electronic circuit technology field.Including power stage, low side drive module, high side logic module, high side drive module, middle side biasing module and active clamp module, low side drive module is used for the driving capability of intensifier pulse bandwidth modulation signals and as the grid control signal of lower power tube；The power rail of pulse width modulating signal is transformed into after floating power supply rail as high side driving control signal by high side logic module, high side drive module generates the grid control signal of power tube under the control of high side driving control signal, and high side drive module and upper power tube constitute current mirror and do constant-current charge to grid driving signal；Middle side biasing module guarantees during upper power tube works for guaranteeing that upper power tube is not breakdown in saturation region.Present invention saves chip layout areas, reduce peripheral circuit cost, have smaller driving stage noise under conditions of meeting driving capability.
Description
Technical field
The invention belongs to electronic circuit technology fields, are related to a kind of current mode segmentation gate driving electricity with active clamp
Road.
Background technique
Reduce the conduction loss of power tube in power management chip, it usually needs grid current potential as high as possible.For
For the AC-DC power supply chip such as flyback transformer Flyback, it usually needs high drive.And in order to enable grid letter driving
Number sufficiently high breakdown external power pipe of voltage, chip usually require to provide using additional low pressure difference linear voltage regulator LDO independent
Suitable higher pressure power rail is entire drive circuitry, typical to realize block diagram as shown in Figure 1, first with LDO by core
It is drive circuitry that piece supply voltage VDD, which provides a suitable high voltage power supply rail Vcc, and pulse width modulating signal PWM exists
It is divided into logical power signal, lower power tube logical signal under the action of up/down power tube control signal generation unit, wherein on
1. power tube logical signal branch, that is, dotted line frame needs the high pressure floating power supply rail of Vcc and Vcc-5V, wherein 5V is power supply pipe
The output voltage of chip interior LDO is managed, 2. lower power tube logical signal branch such as dotted line frame needs the power rail of 5V-0V, then
Under the action of driving enhancement unit, the interior of driving signal HS_G, the LS_G driving afterbody of driving capability enhancing is produced
The grid driving signal DRV of portion's pressure resistance lower power tube HP1, HN1, the high pressure finally exported drive external high pressure power tube M3.
However this traditional gate drive circuit is there are 4 kinds of power rails such as 5V, 0V, Vcc and Vcc-5V, wherein 5V power rail
It is provided by the LDO of system itself, Vcc power rail needs additional LDO to provide, and Vcc-5V power rail then needs floating circuit to produce
It is raw.Due to needing enough driving capabilities, it usually needs biggish electric capacity of voltage regulation and cannot achieve Embedded, it is necessary to use
Plug-in bulky capacitor, which increase the costs of peripheral circuit；Vcc-5V power rail needs for driving enhancement unit power supply, electric capacity of voltage regulation
It can integrate but need to consume biggish chip area and increase chip cost.
Summary of the invention
For needed existing for above-mentioned traditional gate drive circuit additional LDO and plug-in bulky capacitor cause peripheral circuit at
The problems such as this increase and chip area increase, the invention proposes a kind of, and the current mode segmentation gate driving with active clamp is electric
Road is driven using segmented current, and driving stage noise is smaller under conditions of meeting driving capability；Additional LDO is not needed to provide
The power rail of driving circuit, does not need plug-in capacitor yet, saves chip layout area, reduces peripheral circuit cost.
The technical scheme is that
A kind of current mode segmentation gate driving circuit with active clamp, is suitable for power management chip, the power supply pipe
Managing chip includes low pressure difference linear voltage regulator, and the current mode segmentation gate driving circuit includes power stage and low side drive mould
Block, the power stage include upper power tube MP0, lower power tube HN2 and the 13rd PMOS tube HP2, and the low side drive module will
The lower power tube HN2 is used as after the driving capability enhancing for the pulse width modulating signal PWM that the power management chip generates
Grid control signal LDRV, the lower power tube HN2 drain electrode connection the 13rd PMOS tube HP2 drain electrode and as the electricity
The output end that flow pattern is segmented gate driving circuit exports grid driving signal DRV, and source electrode meets Power Groud PGND；
The current mode segmentation gate driving circuit further includes high side logic module, high side drive module, middle side biasing mould
Block and active clamp module,
The high side logic module is used to the power rail of the pulse width modulating signal PWM being transformed into floating power supply rail
It is used as high side driving control signal HDRV_Ctrl afterwards, the floating power supply rail is that subtract the low pressure difference linearity steady by supply voltage VDD
The output voltage of depressor is to supply voltage VDD；
The high side drive module includes the first PMOS tube MP1, the second PMOS tube MP2, third PMOS tube MP3, the 4th
PMOS tube MP4, the 14th PMOS tube HP3, the first NMOS tube MN1, the second NMOS tube MN2, third NMOS tube MN3, the 4th NMOS
Pipe HN3, the 5th NMOS tube HN4,3rd resistor R3, the 7th resistance RST and the first current source I1,
The grid of first NMOS tube MN1 connects the sampled signal DRV_Sense of the grid driving signal DRV, and drain electrode connects
The source electrode of the 4th NMOS tube HN3 is connect, source electrode connects the source electrode of the second NMOS tube MN2 and by being grounded after the first current source I1
GND；
The grid of 4th NMOS tube HN3 connects the output voltage of the low pressure difference linear voltage regulator, drain electrode connection first
The grid of the grid of PMOS tube MP1 and drain electrode and the second PMOS tube MP2；
The grid of second NMOS tube MN2 connects the first reference voltage REF1, the source of drain electrode connection third NMOS tube MN3
Pole；
The grid of third NMOS tube MN3 connects the pulse width modulating signal PWM, drain electrode the 5th NMOS tube of connection
The source electrode of HN4；
The grid of 5th NMOS tube HN4 connects the output voltage of the low pressure difference linear voltage regulator, drain electrode connection second
The grid of the drain electrode of PMOS tube MP2, third PMOS tube MP3 and the 4th PMOS tube MP4 and the 14th PMOS tube HP3 simultaneously pass through the
Supply voltage VDD is connected after seven resistance RST；
The grid of third PMOS tube MP3 connects the inversion signal of the high side driving control signal HDRV_Ctrl, source electrode
Connect the first PMOS tube MP1, the second PMOS tube MP2 and the 4th PMOS tube MP4 source electrode and connect supply voltage VDD；
The source electrode of 14th PMOS tube HP3 connect the 4th PMOS tube MP4 grid and the upper power tube MP0 grid simultaneously
By connecting supply voltage VDD, grounded drain GND after 3rd resistor R3；
The source electrode of upper power tube MP0 connects supply voltage VDD, the source electrode of the 13rd PMOS tube HP2 of drain electrode connection；
The middle side biasing module includes the 5th PMOS tube MP5, the 6th PMOS tube MP6, the 7th PMOS tube MP7, the 8th
PMOS tube MP8, the 15th PMOS tube HP4, the 6th NMOS tube HN5, the 7th NMOS tube HN6, the 4th resistance R4, first capacitor C1,
Second current source I2 and third current source I3,
The grid of 6th NMOS tube HN5 connects the output voltage of the low pressure difference linear voltage regulator, and source electrode passes through second
GND, the grid of the 5th PMOS tube MP5 of drain electrode connection and drain electrode and the 6th PMOS tube MP6 and the 8th are grounded after current source I2
The grid of PMOS tube MP8；
The grid of 7th PMOS tube MP7 connects the drain electrode of the 6th PMOS tube MP6, the source electrode of the 13rd PMOS tube HP2 and the
One end of four resistance R4, source electrode connect source electrode and the company of the 5th PMOS tube MP5, the 6th PMOS tube MP6 and the 8th PMOS tube MP8
Supply voltage VDD is met, the drain electrode of the grid and the 7th NMOS tube HN6 of the 15th PMOS tube HP4 of drain electrode connection simultaneously passes through first
The other end of the 4th resistance R4 is connected after capacitor C1；
The grid of 7th NMOS tube HN6 connects the output voltage of the low pressure difference linear voltage regulator, and source electrode passes through third
GND is grounded after current source I3；
The source electrode of 15th PMOS tube HP4 connects drain electrode and the grid of the 13rd PMOS tube HP2 of the 8th PMOS tube MP8,
Its grounded drain GND；
The active clamp module is for grid driving signal DRV described in clamper.
Specifically, the active clamp module includes the 8th NMOS tube HN7, the 9th PMOS tube MP9, the tenth PMOS tube
MP10, the 11st PMOS tube MP11, the 12nd PMOS tube MP12, the 5th resistance R5, the 6th resistance R6, the 4th current source I4 and neat
Receive pipe Z,
After the grid of tenth PMOS tube MP10 connects the grid of the 9th PMOS tube MP9 and drains and pass through the 4th current source I4
It is grounded GND, source electrode connects the source electrode of the 9th PMOS tube MP9 and connects the output voltage of the low pressure difference linear voltage regulator,
The grid of the 12nd PMOS tube MP12 of drain electrode connection and the source electrode of the 11st PMOS tube MP11；
The grid of 11st PMOS tube MP11 connects the second reference voltage REF2, the 8th NMOS tube HN7's of drain electrode connection
Source electrode is simultaneously grounded GND；
On the one hand the grid of 8th NMOS tube HN7 passes through the drain electrode of the 12nd PMOS tube MP12 of connection after the 5th resistance R5,
On the other hand by being grounded GND, the cathode and the grid driving signal DRV of drain electrode connection Zener Z after the 6th resistance R6；
The anode of Zener Z connects the source electrode of the 12nd PMOS tube MP12.
Specifically, the current mode segmentation gate driving circuit further includes connecing to be segmented gate driving circuit in the current mode
Output end and Power Groud PGND between the cascaded structure being made of first resistor R1 and second resistance R2, series connection point output
The sampled signal DRV_Sense.
The invention has the benefit that
1, power rail is provided without additional LDO, simplifies circuit system, saves chip layout area, do not need volume
Outer electric capacity of voltage regulation reduces peripheral circuit cost.
2, only to simple gate level circuit power supply is contained, electric capacity of voltage regulation area is reduced floating power supply rail, saves core
Piece chip area.
3, the driving circuit is segmented current driving, and under conditions of meeting driving capability, driving stage noise is smaller.
Detailed description of the invention
Fig. 1 is that conventional high-tension gate driving circuit realizes topology diagram.
Fig. 2 is the topology diagram that a kind of current mode with active clamp proposed by the present invention is segmented gate driving circuit.
Fig. 3 is the structural schematic diagram of the high side drive module in the present invention.
Fig. 4 is the structural schematic diagram of the middle side biasing module in the present invention.
Fig. 5 is that a kind of circuit of the active clamp module in the present invention realizes structural schematic diagram.
Fig. 6 is the basic sequential logic figure in the present invention.
Specific embodiment
Present invention is further described in detail with specific embodiment with reference to the accompanying drawing.
It is a kind of current mode segmentation gate driving circuit with active clamp proposed by the present invention as shown in Figure 2, for producing
The grid driving signal DRV of raw driving external power pipe, is suitable for power management chip, the present invention includes power stage, low side drive
Module, high side logic module, high side drive module, middle side biasing module and active clamp module, wherein power stage includes upper function
Rate pipe MP0, lower power tube HN2 and the 13rd PMOS tube HP2, wherein upper power tube MP0 and lower power tube HN2 is power management core
Piece internal power pipe, since power stage has big current spike, under the influence of didt effect, ground potential can shake, because
This power stage connects Power Groud PGND；Low side drive module is used to enhance the pulse width modulating signal of power management chip generation
The driving capability of PWM, and as the grid control signal LDRV of lower power tube HN2, the lower function of low side drive module output
The same phase of grid control signal LDRV and pulse width modulating signal PWM of rate pipe HN2, power rail are 0V into power management chip
The output voltage of low pressure difference linear voltage regulator LDO；High side logic module, which is modulated pulse width using floating power supply rail circuit, to be believed
The power rail of number PWM is transformed into after floating power supply rail as high side driving control signal HDRV_Ctrl, pulse width modulating signal
The power rail of PWM is the output voltage of 0V to power management chip mesolow difference linear constant voltage regulator LDO, and floating power supply rail is power supply
Voltage VDD subtracts the output voltage of LDO in power management chip to supply voltage VDD, below with power management chip mesolow
For the output voltage of difference linear constant voltage regulator LDO is 5V, then the effect of high side logic module is by pulse width modulating signal PWM
Power rail VDD-5V to VDD is converted to from 0V to 5V, will transition to the digital signal of floating power supply rail and driven as high side and controlled
Signal HDRV_Ctrl processed, high side driving control signal HDRV_Ctrl and the number letter that pulse width modulating signal PWM is with phase
Number；High side drive module generates the grid control letter of power tube MP0 under the control of high side driving control signal HDRV_Ctrl
Number HDRV, high side drive module, which with upper power tube MP0 constitutes current mirror, to be done constant current to the grid driving signal DRV of external power tube and fills
Electricity, middle side biasing module guarantees that upper power tube MP0 drain-source voltage is unlikely to excessive and breakdown, while guaranteeing in upper power tube
MP0 is in saturation region during working；The power rail of low side drive module is the power supply of 0-5V power rail；High side drive module and middle side
Biasing module is directly powered by supply voltage, that is, supply voltage VDD of power management chip, is not needed additional LDO and is established newly
Power rail；Power drive grade is responsible for generating grid driving signal DRV, and active clamp module works as grid for detecting grid driving signal DRV
When the voltage of driving signal DRV rises to preset voltage value, stable preset value is reached under the action of loop, therefore having
Grid driving signal DRV is finally stabilized under preset high voltage under the action of the clamp circuit of source.
Below with reference to the specific control mode of physical circuit detailed analysis.
High side drive module proposed by the present invention is used to provide step grate driving current: the schematic diagram of circuit as shown in figure 3,
Including the first PMOS tube MP1, the second PMOS tube MP2, third PMOS tube MP3, the 4th PMOS tube MP4, the 14th PMOS tube HP3,
First NMOS tube MN1, the second NMOS tube MN2, third NMOS tube MN3, the 4th NMOS tube HN3, the 5th NMOS tube HN4, third electricity
R3, the 7th resistance RST and the first current source I1 are hindered, wherein the 7th resistance RST is big resistance, the grid of the first NMOS tube MN1 connects
Meet the sampled signal DRV_Sense of grid driving signal DRV, the source electrode of the 4th NMOS tube HN3 of drain electrode connection, source electrode connection the
The source electrode of two NMOS tube MN2 and by being grounded after the first current source I1；The grid connection low pressure difference linearity of 4th NMOS tube HN3 is steady
The grid of the output voltage of depressor, the grid of the first PMOS tube MP1 of drain electrode connection and drain electrode and the second PMOS tube MP2；The
The grid of two NMOS tube MN2 connects the first reference voltage REF1, the source electrode of drain electrode connection third NMOS tube MN3；3rd NMOS
The grid of pipe MN3 connects pulse width modulating signal PWM, the source electrode of the 5th NMOS tube HN4 of drain electrode connection；5th NMOS tube
The output voltage of the grid connection low pressure difference linear voltage regulator of HN4, drain electrode connection the second PMOS tube MP2, third PMOS tube MP3
The grid of drain electrode and the 14th PMOS tube HP3 with the 4th PMOS tube MP4 and by connecting supply voltage after the 7th resistance RST
VDD；Inversion signal, that is, NHDRV_Ctrl of the grid connection high side driving control signal HDRV_Ctrl of third PMOS tube MP3,
Source electrode connects the source electrode of the first PMOS tube MP1, the second PMOS tube MP2 and the 4th PMOS tube MP4 and connects supply voltage VDD；The
The source electrode of 14 PMOS tube HP3 connects the grid of the 4th PMOS tube MP4 and the grid of upper power tube MP0 and passes through 3rd resistor R3
Supply voltage VDD, grounded drain are connected afterwards；The source electrode of upper power tube MP0 connects supply voltage VDD, drain electrode connection the tenth
The source electrode of three PMOS tube HP2.
The string that the sampled signal DRV_Sense of grid driving signal DRV can be made of first resistor R1 and second resistance R2
It is coupled structure to obtain, first resistor R1 and second resistance R2 series connection are attempted by output end and function that current mode is segmented gate driving circuit
Rate between PGND, series connection point exports sampled signal DRV_Sense, in pulse width modulating signal PWM between high period,
The voltage value for the partial pressure detection unit detection output grid driving signal DRV that first resistor R1 and second resistance R2 is constituted.
It samples obtained sampled signal DRV_Sense and passes through the difference that is made of the first NMOS tube MN1 and the second NMOS tube MN2
Divide the electric current that the 4th PMOS tube MP4 is flowed through to control.After pulse width modulating signal PWM is high, grid driving signal DRV is originally
It is 0, the voltage of sampled signal DRV_Sense is much smaller than the first reference voltage REF1 at this time, and electric current all flows through the 7th resistance RST
With the 4th PMOS tube MP4.4th PMOS tube MP4, the 14th PMOS tube HP3,3rd resistor R3 and upper power tube MP0 actually structure
At β-helper current mirror.Since the 7th resistance RST is larger, tail current i.e. the first current source I1 all flows through the 4th PMOS tube
MP4.At this point, Source electric current (i.e. sink current or outflow electric current) ability of driving circuit, then the electric current of upper power tube MP0 can be with
It indicates are as follows:
Wherein (W/L)MP0(W/L)MP4For the breadth length ratio of upper power tube MP0 and the 4th PMOS tube MP4, upper power tube MP0
The electric current I flowed throughMP0It charges to the grid of external power tube, the voltage of grid driving signal DRV is linearly climbed according to constant-current charge
It rises, sampled signal DRV_Sense also linear rise.When sampled signal DRV_Sense rises near the first reference voltage REF1
When, under the differential pair effect that the first NMOS tube MN1 and the second NMOS tube MN2 is formed, the first PMOS tube MP1 and the second PMOS tube
MP2 also begins with electric current and flows through, and the electric current for flowing through the 4th PMOS tube MP4 is also gradually reduced, the Source electric current energy of driving circuit
Power reduces.Until flowing through the 4th PMOS tube MP4 when sampled signal DRV_Sense is equal with the voltage of the first reference voltage REF1
Electric current be 0, upper power tube MP0 no longer provides driving capability to external power tube.High side drive module passes through detection grid driving
The voltage dynamic of signal DRV has adjusted driving current, thereby realizes current segmenting driving.
Fig. 4 is the circuit structure diagram of middle side biasing module, including the 5th PMOS tube MP5, the 6th PMOS tube MP6, the 7th
PMOS tube MP7, the 8th PMOS tube MP8, the 15th PMOS tube HP4, the 6th NMOS tube HN5, the 7th NMOS tube HN6, the 4th resistance
R4, first capacitor C1, the grid connection low pressure difference linearity of the second current source I2 and third current source I3, the 6th NMOS tube HN5 are steady
The output voltage of depressor, source electrode are grounded after passing through the second current source I2, the grid of the 5th PMOS tube MP5 of drain electrode connection and leakage
The grid of pole and the 6th PMOS tube MP6 and the 8th PMOS tube MP8；The grid of 7th PMOS tube MP7 connects the 6th PMOS tube MP6
Drain electrode, the source electrode of the 13rd PMOS tube HP2 and one end of the 4th resistance R4, source electrode connect the 5th PMOS tube MP5, the 6th
The source electrode of PMOS tube MP6 and the 8th PMOS tube MP8 simultaneously connect supply voltage VDD, the grid of the 15th PMOS tube HP4 of drain electrode connection
The drain electrode of pole and the 7th NMOS tube HN6 and the other end by connecting the 4th resistance R4 after first capacitor C1；7th NMOS tube HN6
Grid connection low pressure difference linear voltage regulator output voltage, source electrode pass through third current source I3 after be grounded；15th PMOS
The source electrode of pipe HP4 connects drain electrode and the grid of the 13rd PMOS tube HP2 of the 8th PMOS tube MP8, grounded drain.
To guarantee the β-being made of the 4th PMOS tube MP4, the 14th PMOS tube HP3,3rd resistor R3 and upper power tube MP0
Helper current mirror can normal mirror, grid driving signal DRV when rising upper power tube MP0 should be at saturation region.A in Fig. 4
Point is that the grid end voltage of the 7th PMOS tube MP7 is VA=VDD-VGS,MP7, wherein VGS,MP7For the grid source electricity of the 7th PMOS tube MP7
Pressure.And the 7th PMOS tube MP7 is by the 4th PMOS tube MP4, lower power tube HN2, default pull down resistor, that is, first resistor R1 and the
Two resistance R2, the gate capacitance of external power pipe, the 7th PMOS tube MP7, the 7th NMOS tube HN6, third current source I3, the 8th PMOS
Saturation region, the drain terminal voltage of the 7th PMOS tube MP7 are biased under the loop effect that pipe MP8 and the 15th PMOS tube HP4 is constituted
It can indicate are as follows:
VSD,MP7=VGS,HP4+VGS,HP2+VGS,MP7
Wherein VGS,HP4And VGS,HP2It is the gate source voltage of the 15th PMOS tube HP4 and the 13rd PMOS tube HP2 respectively, the 7th
The drain terminal voltage V of PMOS tube MP7SD,MP7Higher than its grid end voltage, therefore, the 7th PMOS tube MP7 is constantly in saturation region.Upper
State by the 4th PMOS tube MP4, lower power tube HN2, default pull down resistor i.e. first resistor R1 and second resistance R2, external power
The gate capacitance of pipe, the 7th PMOS tube MP7, the 7th NMOS tube HN6, third current source I3, the 8th PMOS tube MP8 and the 15th PMOS
In the loop that pipe HP4 is constituted, loop stability must be thought over.Wherein, the electric current of the 13rd PMOS tube HP2 is upper power tube
The electric current of the sum of the electric current of MP0 and the 6th PMOS tube MP6, upper power tube MP0 is not identical in the different phase electric current of driving, loop
Stability condition also changes therewith.Compensating electric capacity i.e. first capacitor C1 has been concatenated between the grid leak of the 7th PMOS tube MP7 and has been mended
Resistance i.e. the 4th resistance R4 is repaid, improves loop stability using miller-compensated.The middle A point of loop is dominant pole, the 7th PMOS
The drain terminal node of pipe MP7 is time pole, and secondary pole remains stationary, and dominant pole is with the increase of the 13rd PMOS tube HP2 electric current
And increase.Therefore it may only be necessary to guarantee that loop can be stablized when the 13rd PMOS tube HP2 electric current maximum, then loop is any other
When can stablize.In fact, the electric current that the 6th PMOS tube MP6 flows through is gone back simultaneously other than it can guarantee that loop works normally
It can be with low current to default pull down resistor (the i.e. first resistor R1 at the end output end DRV of current mode segmentation gate driving circuit
With second resistance R2) and other leakage path (parasitisms of the drain terminal including the 8th NMOS tube HN7 in active clamp module to substrate
Diode) electric current is provided, guarantee that the grid driving signal DRV of output maintains to stablize in the case where being charged to preset driving voltage.
Active clamp module is used for a kind of circuit realization figure that clamper grid driving signal DRV, Fig. 5 are active clamp modules,
Including the 8th NMOS tube HN7, the 9th PMOS tube MP9, the tenth PMOS tube MP10, the 11st PMOS tube MP11, the 12nd PMOS tube
MP12, the 5th resistance R5, the 6th resistance R6, the 4th current source I4 and Zener Z, the grid connection the 9th of the tenth PMOS tube MP10
For the grid of PMOS tube MP9 with drain electrode and by being grounded after the 4th current source I4, source electrode connects the source electrode of the 9th PMOS tube MP9 simultaneously
Connect the output voltage of low pressure difference linear voltage regulator, the grid and the 11st PMOS tube of the 12nd PMOS tube MP12 of drain electrode connection
The source electrode of MP11；The grid of 11st PMOS tube MP11 connects the second reference voltage REF2, the 8th NMOS tube HN7 of drain electrode connection
Source electrode and ground connection；The grid of 8th NMOS tube HN7 connects the 12nd PMOS tube MP12's after on the one hand passing through the 5th resistance R5
Drain electrode, on the other hand by being grounded after the 6th resistance R6, the cathode and grid driving signal DRV of drain electrode connection Zener Z；Zener
The anode of pipe Z connects the source electrode of the 12nd PMOS tube MP12.
After upper power tube MP0 is exited, the electric current for leaving behind the 6th PMOS tube MP6 charges to grid driving signal DRV, works as grid
Driving signal DRV voltage slowly rises, and the 12nd PMOS tube MP12 and the 8th NMOS tube HN7 are remained turned-off, until grid driving letter
Number DRV voltage rises to preset driving voltage VDRV=VREF2+VGS,MP11+Vth,MP12+VZWhen, Zener Z is breakdown, and the 12nd
PMOS tube MP12 and the 8th NMOS tube HN7 are begun to turn on, and the 8th NMOS tube HN7 is balanced by the unwanted currents of the 6th PMOS tube MP6
Fall, wherein VGS,MP11、Vth,MP12And VZIt is the threshold of the gate source voltage of the 11st PMOS tube MP11, the 12nd PMOS tube MP12 respectively
Threshold voltage and Zener Z both end voltage.
Fig. 6 is basic logic timing diagram of the invention.It should be apparent that pulse width is modulated from logic control chart
The sequential relationship of signal PWM and grid driving signal DRV, neglect the transmission delay of pulse width modulating signal PWM.When pulse is wide
When spending modulated signal PWM rising, the Source current capacity of gate driving circuit of the invention is in 0~t1 periodGrid driving signal DRV rises very fast；T1~t2 period is Miller platform, at this time grid driving signal
DRV is remained unchanged, and external power pipe drain terminal voltage is gradually increasing；T2~t3 period gate driving circuit of the invention
Source current capacity is identical as the 0-t1 period；In the t3-t4 period, the driving current of gate driving circuit of the invention by
Gradually decline, grid driving signal DRV slope slowly reduces；In the t4-t5 period, grid driving signal DRV voltage is remained unchanged, pressure stabilizing
Value is Vy=VREF2+VGS,MP11+Vth,MP12+VZ；At the t5 moment, pulse width modulating signal PWM failing edge arrives, the t5-t6 time
In section, gate driving circuit drop-down grid driving signal DRV of the invention turns off external power pipe.
It is of the invention it is critical that high side drive module in the voltage control present invention for passing through sampling grid driving signal DRV
Driving current so that high side drive module generate segmentation current driving ability, reduce gate drive circuit dv/dt effect
It answers.Entire driving circuit of the invention simultaneously is all powered by chip supply voltage, that is, supply voltage VDD, is mentioned without additional LDO
Power supply source rail, simplifies circuit system, saves chip layout area, does not need additional electric capacity of voltage regulation, reduces peripheral electricity
Road cost.
Those skilled in the art disclosed the technical disclosures can make various do not depart from originally according to the present invention
Various other specific variations and combinations of essence are invented, these variations and combinations are still within the scope of the present invention.
Claims (3)
1. a kind of current mode with active clamp is segmented gate driving circuit, it is suitable for power management chip, the power management
Chip includes low pressure difference linear voltage regulator, and current mode segmentation gate driving circuit includes power stage and low side drive module,
The power stage includes upper power tube (MP0), lower power tube (HN2) and the 13rd PMOS tube (HP2), the low side drive module
The lower power tube is used as after the driving capability enhancing for the pulse width modulating signal (PWM) that the power management chip is generated
(HN2) grid control signal (LDRV), the drain electrode of the lower power tube (HN2) connect the drain electrode of the 13rd PMOS tube (HP2)
And the output end as current mode segmentation gate driving circuit exports grid driving signal (DRV), source electrode connects Power Groud
(PGND)；
It is characterized in that, the current mode segmentation gate driving circuit further includes high side logic module, high side drive module, middle side
Biasing module and active clamp module,
The high side logic module is for after being transformed into floating power supply rail for the power rail of the pulse width modulating signal (PWM)
As high side driving control signal (HDRV_Ctrl), the floating power supply rail is that supply voltage (VDD) subtracts the low pressure difference linearity
The output voltage of voltage-stablizer is to supply voltage (VDD)；
The high side drive module includes the first PMOS tube (MP1), the second PMOS tube (MP2), third PMOS tube (MP3), the 4th
PMOS tube (MP4), the 14th PMOS tube (HP3), the first NMOS tube (MN1), the second NMOS tube (MN2), third NMOS tube
(MN3), the 4th NMOS tube (HN3), the 5th NMOS tube (HN4), 3rd resistor (R3), the 7th resistance (RST) and the first current source
(I1),
The grid of first NMOS tube (MN1) connects the sampled signal (DRV_Sense) of the grid driving signal (DRV), drain electrode
The source electrode of the 4th NMOS tube (HN3) is connected, source electrode connects the source electrode of the second NMOS tube (MN2) and passes through the first current source (I1)
It is grounded (GND) afterwards；
The grid of 4th NMOS tube (HN3) connects the output voltage of the low pressure difference linear voltage regulator, drain electrode connection first
The grid of the grid of PMOS tube (MP1) and drain electrode and the second PMOS tube (MP2)；
The grid of second NMOS tube (MN2) connects the first reference voltage (REF1), the source of drain electrode connection third NMOS tube (MN3)
Pole；
The grid of third NMOS tube (MN3) connects the pulse width modulating signal (PWM), drain electrode the 5th NMOS tube of connection
(HN4) source electrode；
The grid of 5th NMOS tube (HN4) connects the output voltage of the low pressure difference linear voltage regulator, drain electrode connection second
The grid of PMOS tube (MP2), the drain electrode of third PMOS tube (MP3) and the 4th PMOS tube (MP4) and the 14th PMOS tube (HP3)
And supply voltage (VDD) is connected by the 7th resistance (RST) afterwards；
The grid of third PMOS tube (MP3) connects the inversion signal of the high side driving control signal (HDRV_Ctrl), source electrode
Connect the first PMOS tube (MP1), the second PMOS tube (MP2) and the 4th PMOS tube (MP4) source electrode and connect supply voltage
(VDD)；
The source electrode of 14th PMOS tube (HP3) connects the grid of the 4th PMOS tube (MP4) and the grid of the upper power tube (MP0)
And supply voltage (VDD) is connected afterwards by 3rd resistor (R3), grounded drain (GND)；
The source electrode of upper power tube (MP0) connects supply voltage (VDD), the source electrode of drain electrode the 13rd PMOS tube (HP2) of connection；
The middle side biasing module includes the 5th PMOS tube (MP5), the 6th PMOS tube (MP6), the 7th PMOS tube (MP7), the 8th
PMOS tube (MP8), the 15th PMOS tube (HP4), the 6th NMOS tube (HN5), the 7th NMOS tube (HN6), the 4th resistance (R4),
One capacitor (C1), the second current source (I2) and third current source (I3),
The grid of 6th NMOS tube (HN5) connects the output voltage of the low pressure difference linear voltage regulator, and source electrode passes through the second electricity
Stream source (I2) is grounded (GND) afterwards, the grid and drain electrode and the 6th PMOS tube (MP6) of drain electrode the 5th PMOS tube (MP5) of connection
With the grid of the 8th PMOS tube (MP8)；
The grid of 7th PMOS tube (MP7) connect the drain electrode of the 6th PMOS tube (MP6), the 13rd PMOS tube (HP2) source electrode and
One end of 4th resistance (R4), source electrode connect the 5th PMOS tube (MP5), the 6th PMOS tube (MP6) and the 8th PMOS tube (MP8)
Source electrode and connect supply voltage (VDD), drain electrode connection the 15th PMOS tube (HP4) grid and the 7th NMOS tube (HN6)
Drain electrode and by first capacitor (C1) afterwards connect the 4th resistance (R4) the other end；
The grid of 7th NMOS tube (HN6) connects the output voltage of the low pressure difference linear voltage regulator, and source electrode passes through third electricity
Stream source (I3) is grounded (GND) afterwards；
The source electrode of 15th PMOS tube (HP4) connects the drain electrode of the 8th PMOS tube (MP8) and the grid of the 13rd PMOS tube (HP2)
Pole, grounded drain (GND)；
The active clamp module is for grid driving signal (DRV) described in clamper.
2. the current mode according to claim 1 with active clamp is segmented gate driving circuit, which is characterized in that described to have
Source clamper module includes the 8th NMOS tube (HN7), the 9th PMOS tube (MP9), the tenth PMOS tube (MP10), the 11st PMOS tube
(MP11), the 12nd PMOS tube (MP12), the 5th resistance (R5), the 6th resistance (R6), the 4th current source (I4) and Zener
(Z),
The grid of tenth PMOS tube (MP10) connects the grid of the 9th PMOS tube (MP9) and drains and pass through the 4th current source (I4)
It is grounded (GND) afterwards, source electrode connects the source electrode of the 9th PMOS tube (MP9) and connects the output electricity of the low pressure difference linear voltage regulator
Pressure, the grid of drain electrode the 12nd PMOS tube (MP12) of connection and the source electrode of the 11st PMOS tube (MP11)；
The grid of 11st PMOS tube (MP11) connects the second reference voltage (REF2), drain electrode the 8th NMOS tube (HN7) of connection
Source electrode and ground connection (GND)；
The grid of 8th NMOS tube (HN7) on the one hand passes through the leakage that the 5th resistance (R5) connects the 12nd PMOS tube (MP12) afterwards
On the other hand pole is grounded (GND) afterwards by the 6th resistance (R6), the cathode of drain electrode connection Zener (Z) and grid driving
Signal (DRV)；
The anode of Zener (Z) connects the source electrode of the 12nd PMOS tube (MP12).
3. the current mode according to claim 1 with active clamp is segmented gate driving circuit, which is characterized in that the electricity
Flow pattern segmentation gate driving circuit further includes the output end and Power Groud connect in current mode segmentation gate driving circuit
(PGND) cascaded structure being made of first resistor (R1) and second resistance (R2) between, series connection point export the sampling letter
Number (DRV_Sense).
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| CN201811072014.9A CN109088532B (en) | 2018-09-14 | 2018-09-14 | Current type segmented gate drive circuit with active clamp |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811072014.9A CN109088532B (en) | 2018-09-14 | 2018-09-14 | Current type segmented gate drive circuit with active clamp |
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| CN109088532B CN109088532B (en) | 2020-02-18 |
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|---|---|---|---|
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