CN116073656B - Current regulating circuit and chip - Google Patents
Current regulating circuit and chip Download PDFInfo
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- CN116073656B CN116073656B CN202310132641.1A CN202310132641A CN116073656B CN 116073656 B CN116073656 B CN 116073656B CN 202310132641 A CN202310132641 A CN 202310132641A CN 116073656 B CN116073656 B CN 116073656B
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Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Control Of Voltage And Current In General (AREA)
Abstract
The invention provides a current regulating circuit and a chip, which are used for regulating the current of an inductor in a DCDC voltage reducing circuit, wherein a regulating module is used for regulating the current of the inductor by sampling a first driving signal and a second driving signal and comparing the current of the inductor with a current threshold value and outputting a corresponding regulating signal; the modulation module obtains a modulation signal based on the starting current of the PMOS tube; the control module outputs a first control signal in phase with the modulation signal and a second control signal in phase with the clock signal; when the current of the inductor is greater than or equal to a current threshold, the adjusting signal competes with the modulating signal, and the first control signal is adjusted based on the competition result; the first control signal is regulated by the modulation signal when the current of the inductor is less than a current threshold. The configuration attribute is improved through the adjusting module, the complexity of an operation mode for adjusting the peak current of the inductor is reduced, the circuit area is greatly saved, and the wide applicability is realized.
Description
Technical Field
The present invention relates to the field of power management and application technologies, and in particular, to a current regulation circuit and a chip.
Background
The existing DCDC voltage reduction circuit and chip can realize the purpose of limiting the peak current of the inductor in the DCDC voltage reduction circuit and the chip by limiting the voltage of a signal output by an error amplification module in a modulation device and adding an overcurrent protection device, and the width-to-length ratio of a power tube in the overcurrent protection device is usually required to be set to be a fixed value, or the power tube is connected in series or in parallel to be set to be the width-to-length ratio in a fuse aluminum burning mode, so that different use scenes can be dealt with. Therefore, the conventional mode of limiting the peak inductance current is complex in operation process, more power tubes are used, and readjustment is difficult to achieve after the setting of the width-to-length ratio is completed, so that the circuit area is large, the configuration attribute is lacked, and the applicability is lacked.
It should be noted that the foregoing description of the background art is only for the purpose of facilitating a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. The above-described solutions are not considered to be known to the person skilled in the art simply because they are set forth in the background section of the present application.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a current adjusting circuit and a chip for solving the problems of complicated operation process, large circuit area and lack of configuration property in the prior art for adjusting peak inductor current.
To achieve the above and other related objects, the present invention provides a current adjusting circuit for adjusting a current of an inductor in a DCDC voltage reducing circuit, the current adjusting circuit comprising at least: the device comprises an adjusting module, a modulating module and a control module, wherein:
the adjusting module is connected with a first control signal, a first driving signal and a second driving signal, and outputs a corresponding adjusting signal by sampling the first driving signal and the second driving signal and comparing the current of the inductor with a current threshold value, wherein the adjusting signal adjusts the current of the inductor, and the first driving signal is connected with a source electrode of a PMOS tube in the DCDC voltage reduction circuit; the second driving signal is connected with the drain electrode of the PMOS tube;
the modulation module obtains the modulation signal based on the starting current of the PMOS tube;
the control module is connected with the adjusting signal, the modulating signal, the first driving signal and the clock signal, and outputs the first control signal in phase with the modulating signal and the second control signal in phase with the clock signal, wherein the first control signal is used for controlling the on and off of the PMOS tube; the second control signal is used for controlling the on and off of an NMOS tube in the DCDC voltage reduction circuit; when the current of the inductor is greater than or equal to the current threshold, the adjusting signal competes with the modulating signal, and the first control signal is adjusted based on the competition result; the first control signal is regulated by the modulation signal when the current of the inductor is less than the current threshold.
Optionally, the adjusting module includes a first adjusting unit and a second adjusting unit, wherein: the first adjusting unit is connected with the first control signal, the first driving signal, the second driving signal and the reference signal and outputs the adjusting signal; the second adjusting unit is connected between the reference ground and the first adjusting unit.
Optionally, the first adjusting unit includes a power adjusting subunit and a timing adjusting subunit, wherein: the input end of the power regulation subunit is connected with the first driving signal, the second driving signal and the reference signal; and the input end of the time sequence adjusting subunit is connected with the first control signal and the output end of the power adjusting subunit to generate the adjusting signal.
Optionally, the power conditioning subunit includes: the first NMOS power tube, the second NMOS power tube, the third NMOS power tube, the fourth NMOS power tube, the fifth NMOS power tube, the sixth NMOS power tube, the seventh NMOS power tube, the first PMOS power tube, the second PMOS power tube, the third PMOS power tube, the fourth PMOS power tube, the fifth PMOS power tube, the sixth PMOS power tube, the seventh PMOS power tube, the eighth PMOS power tube, the ninth PMOS power tube, the tenth PMOS power tube, the eleventh PMOS power tube, the twelfth PMOS power tube, the first resistor, the second resistor, the third resistor, the fourth resistor and the current source, wherein:
The first end of the third resistor is connected with the first driving signal; the source electrode of the first PMOS power tube is connected with the second end of the third resistor, the grid electrode of the first PMOS power tube is connected with the power ground, and the power ground is connected with the source electrode of the NMOS tube in the DCDC voltage reduction circuit; the source electrode of the third PMOS power tube is connected with the drain electrode of the first PMOS power tube, and the grid electrode of the third PMOS power tube is connected with the grid electrode of the first PMOS power tube; the source electrode of the fourth PMOS power tube is connected with the drain electrode of the third PMOS power tube; the first resistor is connected between the drain electrode of the fourth PMOS power tube and the reference ground;
the first end of the fourth resistor is connected with the second driving signal; the source electrode of the second PMOS power tube is connected with the second end of the fourth resistor, and the grid electrode of the second PMOS power tube is connected with power ground; the source electrode of the fifth PMOS power tube is connected with the drain electrode of the second PMOS power tube, and the grid electrode of the fifth PMOS power tube is connected with the grid electrode of the fourth PMOS power tube; the second resistor is connected between the drain electrode of the fifth PMOS power tube and the reference ground;
The first end of the current source is connected with the working voltage; the drain electrode of the first NMOS power tube is connected with the second end of the current source, the grid electrode of the first NMOS power tube is connected with the drain electrode of the first NMOS power tube, and the source electrode of the first NMOS power tube is connected with the reference ground; the source electrode of the sixth PMOS power tube is connected with the drain electrode of the third PMOS power tube, the grid electrode of the sixth PMOS power tube is connected with the grid electrode of the fourth PMOS power tube, and the drain electrode of the sixth PMOS power tube is connected with the grid electrode; the drain electrode of the second NMOS power tube is connected with the drain electrode of the sixth PMOS power tube, the grid electrode of the second NMOS power tube is connected with the grid electrode of the first NMOS power tube, and the source electrode of the second NMOS power tube is connected with the reference ground;
the source electrode of the seventh PMOS power tube is connected with the working voltage, and the grid electrode of the seventh PMOS power tube is connected with the drain electrode; the drain electrode of the third NMOS power tube is connected with the drain electrode of the seventh PMOS power tube, the grid electrode of the third NMOS power tube is connected with the grid electrode of the second NMOS power tube, and the source electrode of the third NMOS power tube is connected with the reference ground; the source electrode of the eighth PMOS power tube is connected with the working voltage, and the grid electrode of the eighth PMOS power tube is connected with the grid electrode of the seventh PMOS power tube; the source electrode of the ninth PMOS power tube is connected with the drain electrode of the eighth PMOS power tube, and the grid electrode of the ninth PMOS power tube is connected with the reference signal; the drain electrode of the fourth NMOS power tube is connected with the grid electrode, and the source electrode of the fourth NMOS power tube is connected with the reference ground; the source electrode of the tenth PMOS power tube is connected with the drain electrode of the eighth PMOS power tube, and the grid electrode of the tenth PMOS power tube is connected with the second regulating unit; the drain electrode of the fifth NMOS power tube is connected with the drain electrode of the tenth PMOS power tube, the grid electrode of the fifth NMOS power tube is connected with the grid electrode of the fourth NMOS power tube, and the source electrode of the fifth NMOS power tube is connected with the reference ground;
The source electrode of the eleventh PMOS power tube is connected with the working voltage, and the grid electrode of the eleventh PMOS power tube is connected with the drain electrode; the drain electrode of the sixth NMOS power tube is connected with the drain electrode of the eleventh PMOS power tube, the grid electrode of the sixth NMOS power tube is connected with the drain electrode of the fifth NMOS power tube, and the source electrode of the sixth NMOS power tube is connected with the second regulating unit; the source electrode of the twelfth PMOS power tube is connected with the working voltage, the grid electrode of the twelfth PMOS power tube is connected with the grid electrode of the eleventh PMOS power tube, and the drain electrode of the twelfth PMOS power tube is connected with the drain electrode of the fourth PMOS power tube; and the drain electrode of the seventh NMOS power tube is connected with the drain electrode of the twelfth PMOS power tube, and the source electrode of the seventh NMOS power tube is connected with the reference ground.
Optionally, the first resistor and the second resistor have the same parameters; the parameters of the third resistor and the fourth resistor are the same; the parameters of the first PMOS power tube and the second PMOS power tube are the same; the parameters of the fourth PMOS power tube, the fifth PMOS power tube and the sixth PMOS power tube are the same; the parameters of the seventh PMOS power tube and the eighth PMOS power tube are the same; the parameters of the ninth PMOS power tube and the tenth PMOS power tube are the same; the eleventh PMOS power tube and the twelfth PMOS power tube have the same parameters; the parameters of the first NMOS power tube, the second NMOS power tube and the third NMOS power tube are the same; and the parameters of the fourth NMOS power tube and the fifth NMOS power tube are the same.
Optionally, the timing adjustment subunit includes: a first not gate, a second not gate, a third not gate, a fourth not gate, a fifth not gate, a sixth not gate, a first nand gate, a second nand gate, a first nor gate, a delay component, an eighth NMOS power transistor, and a first comparator, wherein: the input end of the first NOT gate is connected with the first control signal; the input end of the delay component is connected with the output end of the first NOT gate; the input end of the second NOT gate is connected with the output end of the delay component; the input end of the third NOT gate is connected with the output end of the second NOT gate; the input end of the first NAND gate is connected with the output end of the first NAND gate and the output end of the third NAND gate; the input end of the fourth NAND gate is connected with the output end of the first NAND gate; the input end of the first NOR gate is connected with the output end of the fourth NOR gate and the output end of the first NOR gate; the drain electrode of the eighth NMOS power tube is connected with the output end of the delay component, the grid electrode of the eighth NMOS power tube is connected with the output end of the first NOR gate, and the source electrode of the eighth NMOS power tube is connected with the reference ground; the input end of the fifth NOT gate is connected with the output end of the fourth NOT gate, and the output end of the fifth NOT gate is connected with the grid electrode of the seventh NMOS power tube; the non-inverting input end of the first comparator is connected with the drain electrode of the fourth PMOS power tube, the inverting input end of the first comparator is connected with the drain electrode of the fifth PMOS power tube, and the enabling end of the first comparator is connected with the output end of the fourth NOT gate; the input end of the second NAND gate is connected with the output end of the first comparator and the output end of the fourth NAND gate; and the input end of the sixth NOT gate is connected with the output end of the second NOT gate, and the adjusting signal is output.
Optionally, the delay component includes a fifth resistor and a first capacitor, wherein: the first end of the fifth resistor is connected with the output end of the first NOT gate; the first capacitor is connected between the second end of the fifth resistor and the reference ground.
Optionally, the second adjusting unit includes a sixth resistor.
Optionally, the sixth resistor comprises an adjustable resistor.
Optionally, the modulation mode of the modulation module includes pulse width modulation.
To achieve the above and other related objects, the present invention provides a chip comprising: and the current regulating circuit is used for regulating the current of the inductor in the DCDC voltage reducing circuit, wherein the number of the DCDC voltage reducing circuits is equal to that of the current regulating circuits, and the DCDC voltage reducing circuits are in one-to-one correspondence with the current regulating circuits.
As described above, the current regulating circuit and the chip have the following beneficial effects:
according to the current regulating circuit and the chip, the configuration attribute is improved through the regulating module, the complexity of an operation mode for regulating the peak current of the inductor is reduced, the circuit area is greatly saved, and the current regulating circuit and the chip have wide applicability.
Drawings
Fig. 1 shows a schematic diagram of a current regulation circuit according to the present invention.
Fig. 2 shows a schematic circuit diagram of the conditioning module of the present invention.
Description of the reference numerals
1. Current regulating circuit
11. Adjusting module
111. First adjusting unit
1111. Power conditioning subunit
1112. Timing adjustment subunit
1113. Delay assembly
112. Second adjusting unit
12. Modulation module
13. Control module
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 1-2. It should be noted that the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.
As shown in fig. 1, the present embodiment provides a current adjusting circuit 1 for adjusting a current of an inductance L1 in a DCDC voltage reducing circuit, the current adjusting circuit 1 including: a regulating module 11, a modulating module 13 and a control module 12, wherein:
as shown in fig. 1, the adjusting module 11 is connected to the first control signal HSG, the first driving signal PVIN and the second driving signal SW, and outputs a corresponding adjusting signal cl_out by sampling the first driving signal PVIN and the second driving signal SW and comparing the current of the inductor L1 with a current threshold value, where the adjusting signal cl_out adjusts the current of the inductor L1, and the first driving signal PVIN is connected to the source of the PMOS transistor P1 in the DCDC voltage reducing circuit; the second driving signal SW is connected to the drain of the PMOS transistor P1.
Specifically, as an example, as shown in fig. 1, the adjustment module 11 includes a first adjustment unit 111 and a second adjustment unit 112, in which: the first adjusting unit 111 is connected to the first control signal HSG, the first driving signal PVIN, the second driving signal SW, and the reference signal VREF, and outputs an adjusting signal cl_out; the second regulating unit 112 is connected between the ground GND and the first regulating unit 111.
More specifically, as shown in fig. 2, the first adjusting unit 111 includes a power adjusting subunit 1111 and a timing adjusting subunit 1112, wherein: the input end of the power adjustment subunit 1111 is connected to the first driving signal PVIN, the second driving signal SW and the reference signal VREF; an input terminal of the timing adjustment subunit 1112 is connected to the first control signal HSG and an output terminal of the power adjustment subunit 1111, and generates an adjustment signal cl_out.
Further, as shown in fig. 2, the power adjustment subunit 1111 includes: first NMOS power tube MN1, second NMOS power tube MN2, third NMOS power tube MN3, fourth NMOS power tube MN4, fifth NMOS power tube MN5, sixth NMOS power tube MN6, seventh NMOS power tube MN7, first PMOS power tube MP1, second PMOS power tube MP2, third PMOS power tube MP3, fourth PMOS power tube MP4, fifth PMOS power tube MP5, sixth PMOS power tube MP6, seventh PMOS power tube MP7, eighth PMOS power tube MP8, ninth PMOS power tube MP9, tenth PMOS power tube MP10, eleventh PMOS power tube MP11, twelfth PMOS power tube MP12, first resistor R1, second resistor R2, third resistor R3, fourth resistor R4 and current source I S Wherein:
the first end of the third resistor R3 and the first driving signal PVIN; the source electrode of the first PMOS power tube MP1 is connected with the second end of the third resistor R3, the grid electrode of the first PMOS power tube MP1 is connected with the power ground PGND, and the power ground PGND is connected with the source electrode of the NMOS tube N1 in the DCDC voltage reduction circuit; the source electrode of the third PMOS power tube MP3 is connected with the drain electrode of the first PMOS power tube MP1, and the grid electrode of the third PMOS power tube MP3 is connected with the grid electrode of the first PMOS power tube MP 1; the source electrode of the fourth PMOS power tube MP4 is connected with the drain electrode of the third PMOS power tube MP 3; the first resistor R1 is connected between the drain of the fourth PMOS power transistor MP4 and the ground GND. Note that, the power ground PGND is a reference ground applied to a high-power circuit. High power circuits, as their name implies, are relatively high current circuits, such as motor drive circuits, solenoid drive circuits, etc., which require a separate reference ground, because high currents tend to cause ground offset between different functional circuits, and once there is ground offset in the circuit, the original 5 volt voltage may not be 5 volts. Because 5 volts is 0 volts with respect to ground, if the ground is offset such that the ground is raised from 0 volts, for example, by 1 volt, the previous 5 volts will become 4 volts, thereby increasing the interference between the signals.
The first end of the fourth resistor R4 is connected with the second driving signal SW; the source electrode of the second PMOS power tube MP2 is connected with the second end of the fourth resistor R4, and the grid electrode of the second PMOS power tube MP2 is connected with the power ground PGND; the source electrode of the fifth PMOS power tube MP5 is connected with the drain electrode of the second PMOS power tube MP2, and the grid electrode of the fifth PMOS power tube MP5 is connected with the grid electrode of the fourth PMOS power tube MP 4; the second resistor R2 is connected between the drain of the fifth PMOS power transistor MP5 and the ground GND.
Current source I S Is connected with the working voltage VCC; drain electrode of first NMOS power tube MN1 and current source I S The gate of the first NMOS power tube MN1 is connected with the drain of the first NMOS power tube MN1, and the source of the first NMOS power tube MN1 is connected with the ground GND; the source electrode of the sixth PMOS power tube MP6 is connected with the drain electrode of the third PMOS power tube MP3, the grid electrode of the sixth PMOS power tube MP6 is connected with the grid electrode of the fourth PMOS power tube MP4, and the drain electrode of the sixth PMOS power tube MP6 is connected with the grid electrode; the drain electrode of the second NMOS power tube MN2 is connected with the drain electrode of the sixth PMOS power tube MP6, the grid electrode of the second NMOS power tube MN2 is connected with the grid electrode of the first NMOS power tube MN1, and the source electrode of the second NMOS power tube MN2 is connected with the ground GND.
The source electrode of the seventh PMOS power tube MP7 is connected with the working voltage VCC, and the grid electrode of the seventh PMOS power tube MP7 is connected with the drain electrode; the drain electrode of the third NMOS power tube MN3 is connected with the drain electrode of the seventh PMOS power tube MP7, the grid electrode of the third NMOS power tube MN3 is connected with the grid electrode of the second NMOS power tube MN2, and the source electrode of the third NMOS power tube MN3 is connected with the reference ground GND; the source electrode of the eighth PMOS power tube MP8 is connected with the working voltage VCC, and the grid electrode of the eighth PMOS power tube MP8 is connected with the grid electrode of the seventh PMOS power tube MP 7; the source electrode of the ninth PMOS power tube MP9 is connected with the drain electrode of the eighth PMOS power tube MP8, and the grid electrode of the ninth PMOS power tube MP9 is connected with the reference signal VREF; the drain electrode of the fourth NMOS power tube MN4 is connected with the grid electrode, and the source electrode of the fourth NMOS power tube MN4 is connected with the ground GND; the source electrode of the tenth PMOS power tube MP10 is connected with the drain electrode of the eighth PMOS power tube MP8, and the grid electrode of the tenth PMOS power tube MP10 is connected with the second regulating unit 112; the drain electrode of the fifth NMOS power tube MN5 is connected with the drain electrode of the tenth PMOS power tube MP10, the grid electrode of the fifth NMOS power tube MN5 is connected with the grid electrode of the fourth NMOS power tube MN4, and the source electrode of the fifth NMOS power tube MN5 is connected with the ground GND.
The source electrode of the eleventh PMOS power tube MP11 is connected with the working voltage VCC, and the grid electrode of the eleventh PMOS power tube MP11 is connected with the drain electrode; the drain electrode of the sixth NMOS power tube MN6 is connected with the drain electrode of the eleventh PMOS power tube MP11, the grid electrode of the sixth NMOS power tube MN6 is connected with the drain electrode of the fifth NMOS power tube MN5, and the source electrode of the sixth NMOS power tube MN6 is connected with the second regulating unit 112; the source electrode of the twelfth PMOS power tube MP12 is connected with the working voltage VCC, the grid electrode of the twelfth PMOS power tube MP12 is connected with the grid electrode of the eleventh PMOS power tube MP11, and the drain electrode of the twelfth PMOS power tube MP12 is connected with the drain electrode of the fourth PMOS power tube MP 4; the drain of the seventh NMOS power transistor MN7 is connected to the drain of the twelfth PMOS power transistor MP12, and the source of the seventh NMOS power transistor MN7 is connected to the ground GND.
Further, as shown in fig. 2, the parameters of the first resistor R1 and the second resistor R2 are the same; the parameters of the third resistor R3 and the fourth resistor R4 are the same; the parameters of the first PMOS power tube MP1 and the second PMOS power tube MP2 are the same; the parameters of the fourth PMOS power tube MP4, the fifth PMOS power tube MP5 and the sixth PMOS power tube MP6 are the same; parameters of the seventh PMOS power tube MP7 and the eighth PMOS power tube MP8 are the same; parameters of the ninth PMOS power tube MP9 and the tenth PMOS power tube MP10 are the same; the eleventh PMOS power tube MP11 and the twelfth PMOS power tube MP12 have the same parameters; parameters of the first NMOS power tube MN1, the second NMOS power tube MN2 and the third NMOS power tube MN3 are the same; the parameters of the fourth NMOS power tube MN4 and the fifth NMOS power tube MN5 are the same.
As an example, the voltage of the reference signal VREF may be set according to actual requirements, and when the sixth NMOS power transistor MN6 is turned on, the drain current inn6=vref/R112 of the sixth NMOS power transistor MN6, where R112 is represented as the impedance of the second adjusting unit 112; in general, the drain current Imp4 of the fourth PMOS power transistor MP4 is a fixed value, and the current superimposed on the first resistor R1 is inn5+imp4, so the drain voltage of the fourth PMOS power transistor MP4 is r1× (inn6+imp4), that is, the voltage VX of the node x=r1× (inn6+imp4). The width-to-length ratio of the third PMOS power transistor MP3 is set according to the actual requirement, because the third PMOS power transistor MP3 has a voltage division, when the current of the inductor L1 in the DCDC voltage-reducing circuit is low, the voltage difference between the first driving signal PVI and the second driving signal SW is relatively small, and the source voltage of the fourth PMOS power transistor MP4 is lower than the source voltage of the fifth PMOS power transistor MP5, so that the drain current Imp5 of the fifth PMOS power transistor MP5 is greater than the drain current Imp4 of the fourth PMOS power transistor MP4, i.e., imp5 > Imp4, and the current superimposed on the second resistor R2 is Imp5, so that the drain voltage of the fifth PMOS power transistor MP5 is R2 x Imp5, i.e., the voltage vy=r2 x Imp5 of the node Y. When the current of the inductor L1 is low and the voltage difference between the first driving signal PVI and the second driving signal SW is relatively small, VY > VX.
When the current of the inductor L1 is higher and the voltage difference between the first driving signal PVI and the second driving signal SW is relatively larger, the source voltage of the fifth PMOS power transistor MP5 is relatively reduced, so that the drain current Imp5 of the fifth PMOS power transistor MP5 is smaller than the drain current Imp4 of the fourth PMOS power transistor MP4, the voltage VY of the node Y is reduced, so that VY is smaller than VX, and the primary detection of the current of the inductor L1 is realized by comparing the voltage VX of the node X with the voltage VY of the node Y through the reference signal VREF. It should be noted that, the reference signal VREF and the second adjusting unit 112 are adjusted to set the current threshold, and the current of the inductor L1 is detected based on the voltage VX of the comparison node X and the voltage VY of the node Y.
Further, as shown in fig. 2, the timing adjustment subunit 1112 includes: a first NOT gate NOT1, a second NOT gate NOT2, a third NOT gate NOT3, a fourth NOT gate NOT4, a fifth NOT gate NOT5, a sixth NOT gate NOT6, a first NAND gate NAND1, a second NAND gate NAND2, a first NOR gate NOR1, a delay component 1113, an eighth NMOS power transistor MN8, and a first comparator COM1, wherein: the input end of the first NOT gate NOT1 is connected with a first control signal HSG; an input terminal of the delay component 1113 is connected to an output terminal of the first NOT gate NOT 1; the input of the second NOT gate NOT2 is connected with the output of the delay component 1113; the input end of the third NOT gate NOT3 is connected with the output end of the second NOT gate NOT 2; the input end of the first NAND gate NAND1 is connected with the output end of the first NOT gate NOT1 and the output end of the third NOT gate NOT 3; the input end of the fourth NOT4 is connected with the output end of the first NAND gate NAND 1; the input end of the first NOR gate NOR1 is connected with the output end of the fourth NOT gate NOT4 and the output end of the first NOT gate NOT 1; the drain electrode of the eighth NMOS power tube MN8 is connected with the output end of the delay component 1113, the grid electrode of the eighth NMOS power tube MN8 is connected with the output end of the first NOR gate NOR1, and the source electrode of the eighth NMOS power tube MN8 is connected with the ground GND; the input end of the fifth NOT5 is connected with the output end of the fourth NOT4, and the output end of the fifth NOT5 is connected with the grid electrode of the seventh NMOS power tube MN 7; the non-inverting input end of the first comparator COM1 is connected to the drain electrode of the fourth PMOS power transistor MP4 (i.e., the non-inverting input end is connected to the node X), the inverting input end of the first comparator COM1 is connected to the drain electrode of the fifth PMOS power transistor MP5 (i.e., the inverting input end is connected to the node Y), and the enable end of the first comparator COM1 is connected to the output end of the fourth NOT gate NOT4 (i.e., the enable end is connected to the signal delay_en_h); the input end of the second NAND gate NAND2 is connected with the output end of the first comparator COM1 and the output end of the fourth NOT gate NOT 4; the input terminal of the sixth NOT gate NOT6 is connected to the output terminal of the second NAND gate NAND2, and outputs the adjustment signal cl_out. Further, the delay component 1113 includes a fifth resistor R5 and a first capacitor C1, wherein: the first end of the fifth resistor R5 is connected with the output end of the first NOT 1; the first capacitor C1 is connected between the second end of the fifth resistor R5 and the ground GND. It should be noted that, when the first control signal HSG is at a high level, the fifth resistor R5 and the first capacitor C1 form an RC delay network, so that the power adjustment subunit 1111 performs power adjustment after a certain delay, to avoid false detection of the inductor L1 or false triggering of the adjustment signal cl_out, and the generated delay time should set parameters of the fifth resistor R5 and the first capacitor C1 according to the requirement, which will not be described herein in detail. It should be noted that, the delay component 1113 includes, but is not limited to, an RC delay network formed by the fifth resistor R5 and the first capacitor C1, and a 555 timer delay circuit, a single op-amp delay circuit, a transistor delay circuit, etc. may be also used, so long as the false detection of the inductor L1 or the false triggering of the adjusting signal cl_out can be avoided, the setting form of any delay component 1113 is not limited to this embodiment.
As an example, as shown in fig. 2, when the current of the inductor L1 is low and the voltage difference between the first driving signal PVI and the second driving signal SW is relatively small, VY > VX is then determined by the first comparator COM1 to be output as a low level, and further, the adjustment signal cl_out is low level; when the current of the inductor L1 is high and the voltage difference between the first driving signal PVI and the second driving signal SW is relatively large, VY < VX is then smaller than VX, and the first comparator COM1 outputs a high level after judging, and further, the adjusting signal cl_out is a high level, so that the detection of the current of the inductor L1 is completed. It should be noted that, when the PMOS transistor P1 is turned on and off based on the first control signal HSG, the first control signal HSG is at a low level, and after the first control signal HSG is delayed by the Delay component 1113, the signal delay_en_l output by the fifth NOT5 is at a low level, and the signal delay_en_l is connected to the gate of the seventh NMOS power transistor MN7, at this time, the signal delay_en_l turns off the seventh NMOS power transistor MN7, so that the voltage of the voltage VX of the node X is pulled low, and equivalently "turns off" the power regulator sub-unit 1111, because the state of the power regulator sub-unit 1111 is ensured from the logic closed loop when the seventh NMOS power transistor MN7 is in the off state, thereby ensuring the current limiting of the inductor L1.
More specifically, as shown in fig. 1 and 2, the second adjusting unit 112 includes a sixth resistor R6. Further, the sixth resistor R6 includes an adjustable resistor, when the sixth NMOS power transistor MN6 is turned on, the drain current inn6=vref/R6 of the sixth NMOS power transistor MN6, so as to detect the current of the inductor L1 by comparing the voltage VX of the node X with the voltage VY of the node Y. It should be noted that the second adjusting unit 112 includes, but is not limited to, a sixth resistor, a silicon high-speed switch diode, an impedance network composed of a capacitor, a resistor and an inductor, etc., and any configuration of the second adjusting unit 112 is applicable as long as the drain current of the sixth NMOS MN6 can be adjusted, and is not limited to the embodiment.
It should be noted that, the adjusting module 11 includes, but is not limited to, an application specific integrated circuit (ASIC, application Specific Integrated Circuit) or an IP core (IP core, intellectual Property core is a hardware description language program with specific circuit functions, which is irrelevant to the integrated circuit process and can be transplanted into different semiconductor processes to produce an integrated circuit chip.
As shown in fig. 1, the modulation module 13 obtains a modulation signal based on the on current i_p1 of the PMOS transistor P1. Specifically, as an example, the modulation mode of the modulation module 13 includes pulse width modulation, and when the modulation mode of the modulation module 13 is pulse width modulation, the modulation module 13 generates the modulation signal PWM, where the modulation module 13 includes a second comparator COM2, the non-inverting input terminal of the second comparator COM2 is connected to the signal COMP (the signal COMP is generated by error amplification, and the specific process is not described in detail herein), and the inverting input terminal is connected to the on current i_p1 and the ramp current I SLOPE The signal COMP is compared with the superimposed signal VRAMP to generate the modulated signal PWM by the second comparator COM 2. It should be noted that, the modulation method of the modulation module 13 includes, but is not limited to, pulse width modulation, pulse frequency modulation, pulse span period modulation, and the like, and any modulation method of the modulation module 13 is applicable as long as the peak value of the on current i_p1 of the PMOS transistor P1 can be detected to obtain the modulation signal, and is not limited to the embodiment.
As shown in fig. 1, the control module 12 is connected to the adjusting signal cl_out, the modulating signal, the first driving signal PVIN and the clock signal OSC, and outputs a first control signal HSG in phase with the modulating signal and a second control signal LSG in phase with the clock signal OSC, wherein the first control signal HSG is used for controlling the PMOS transistor P1 to be turned on and off; the second control signal LSG is used for controlling the on and off of the NMOS tube N1 in the DCDC voltage reduction circuit; when the current of the inductor L1 is greater than or equal to the current threshold, the adjusting signal cl_out competes with the modulating signal, and the first control signal HSG is adjusted based on the result of the competition; when the current of the inductor L1 is smaller than the current threshold, the first control signal HSG is regulated by the modulation signal. It should be noted that, when the first control signal HSG is at a high level, the PMOS transistor P1 is turned off, the control module 12 turns the second control signal LSG to a high level, so that the NMOS transistor N1 is turned on, and when the falling edge of the clock signal OSC arrives, the second control signal LSG is turned to a low level through internal processing of the control module 12, so that the NMOS transistor N1 is turned off, thereby completing a working cycle.
While the process of adjusting the signal cl_out to compete with the modulated signal includes: as shown in fig. 1, when the VOUT end of the inductor L1 is lightly loaded, the voltage of the signal COMP in the modulation module 13 is relatively low, and at this time, the current of the inductor L1 is hard to reach the current threshold (the current threshold is determined by the reference signal VREF and the second adjusting unit 112), the modulation signal will reach the control module 12 in advance of the adjusting signal cl_out, and an in-phase first control signal HSG is generated based on the modulation signal to control the PMOS transistor P1; when the VOUT terminal of the inductor L1 is overloaded, the signal COMP is relatively high, and once the set current threshold is greater than the peak current required by the signal COMP, the adjusting signal cl_out will reach the control module 12 in advance of the modulating signal, and an in-phase first control signal HSG is generated based on the adjusting signal cl_out, so as to control the PMOS transistor P1, where the modulating signal and the adjusting signal cl_out perform an or operation in the control module 12.
It should be noted that, the modulation module 13 and the control module 12 may also be configured in an application specific integrated circuit, an IP core, or the like, so long as the modulation module 13 can generate a modulation signal and the control module 12 can control the PMOS transistor P1 and the NMOS transistor N1, the configuration of any modulation module 13 and control module 12 is not limited to this embodiment.
The embodiment also provides a chip, which comprises at least one current regulating circuit provided by the embodiment, and is used for regulating the current of the inductor in the DCDC voltage reducing circuits, wherein the number of the DCDC voltage reducing circuits is equal to that of the current regulating circuits, and the DCDC voltage reducing circuits are in one-to-one correspondence with the current regulating circuits.
In summary, the current adjusting circuit and the chip according to the present invention are used for adjusting the current of the inductor in the DCDC voltage reducing circuit, and the peak current adjusting circuit at least includes: the device comprises an adjusting module, a modulating module and a control module, wherein: the adjusting module is connected with a first control signal, a first driving signal and a second driving signal, and outputs a corresponding adjusting signal by sampling the first driving signal and the second driving signal and comparing the current of the inductor with a current threshold value, wherein the adjusting signal adjusts the current of the inductor, and the first driving signal is connected with a source electrode of a PMOS tube in the DCDC voltage reduction circuit; the second driving signal is connected with the drain electrode of the PMOS tube; the modulation module obtains the modulation signal based on the starting current of the PMOS tube; the control module is connected with the adjusting signal, the modulating signal, the first driving signal and the clock signal, and outputs the first control signal in phase with the modulating signal and the second control signal in phase with the clock signal, wherein the first control signal is used for controlling the on and off of the PMOS tube; the second control signal is used for controlling the on and off of an NMOS tube in the DCDC voltage reduction circuit; when the current of the inductor is greater than or equal to the current threshold, the adjusting signal competes with the modulating signal, and the first control signal is adjusted based on the competition result; the first control signal is regulated by the modulation signal when the current of the inductor is less than the current threshold. According to the current regulating circuit and the chip, the configuration attribute is improved through the regulating module, the complexity of an operation mode for regulating the peak current of the inductor is reduced, the circuit area is greatly saved, and the current regulating circuit and the chip have wide applicability. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (8)
1. A current regulation circuit for regulating the current of an inductor in a DCDC buck circuit, the current regulation circuit comprising at least: the device comprises an adjusting module, a modulating module and a control module, wherein:
the adjusting module is connected with a first control signal, a first driving signal and a second driving signal, and outputs a corresponding adjusting signal by sampling the first driving signal and the second driving signal and comparing the current of the inductor with a current threshold value, wherein the adjusting signal adjusts the current of the inductor, and the first driving signal is connected with a source electrode of a PMOS tube in the DCDC voltage reduction circuit; the second driving signal is connected with the drain electrode of the PMOS tube;
the modulation module obtains a modulation signal based on the starting current of the PMOS tube;
The control module is connected with the adjusting signal, the modulating signal, the first driving signal and the clock signal, and outputs the first control signal in phase with the modulating signal and the second control signal in phase with the clock signal, wherein the first control signal is used for controlling the on and off of the PMOS tube; the second control signal is used for controlling the on and off of an NMOS tube in the DCDC voltage reduction circuit; when the current of the inductor is greater than or equal to the current threshold, the adjusting signal competes with the modulating signal, and the first control signal is adjusted based on the competition result; when the current of the inductor is smaller than the current threshold value, the first control signal is regulated by the modulation signal;
the adjusting module comprises a first adjusting unit and a second adjusting unit, wherein: the first adjusting unit is connected with the first control signal, the first driving signal, the second driving signal and the reference signal and outputs the adjusting signal; the second adjusting unit is connected between the reference ground and the first adjusting unit;
the first adjusting unit comprises a power adjusting subunit and a time sequence adjusting subunit, wherein: the input end of the power regulation subunit is connected with the first driving signal, the second driving signal and the reference signal; the input end of the time sequence adjusting subunit is connected with the first control signal and the output end of the power adjusting subunit to generate the adjusting signal;
The first NMOS power tube, the second NMOS power tube, the third NMOS power tube, the fourth NMOS power tube, the fifth NMOS power tube, the sixth NMOS power tube, the seventh NMOS power tube, the first PMOS power tube, the second PMOS power tube, the third PMOS power tube, the fourth PMOS power tube, the fifth PMOS power tube, the sixth PMOS power tube, the seventh PMOS power tube, the eighth PMOS power tube, the ninth PMOS power tube, the tenth PMOS power tube, the eleventh PMOS power tube, the twelfth PMOS power tube, the first resistor, the second resistor, the third resistor, the fourth resistor and the current source, wherein:
the first end of the third resistor is connected with the first driving signal; the source electrode of the first PMOS power tube is connected with the second end of the third resistor, the grid electrode of the first PMOS power tube is connected with the power ground, and the power ground is connected with the source electrode of the NMOS tube in the DCDC voltage reduction circuit; the source electrode of the third PMOS power tube is connected with the drain electrode of the first PMOS power tube, and the grid electrode of the third PMOS power tube is connected with the grid electrode of the first PMOS power tube; the source electrode of the fourth PMOS power tube is connected with the drain electrode of the third PMOS power tube; the first resistor is connected between the drain electrode of the fourth PMOS power tube and the reference ground;
The first end of the fourth resistor is connected with the second driving signal; the source electrode of the second PMOS power tube is connected with the second end of the fourth resistor, and the grid electrode of the second PMOS power tube is connected with power ground; the source electrode of the fifth PMOS power tube is connected with the drain electrode of the second PMOS power tube, and the grid electrode of the fifth PMOS power tube is connected with the grid electrode of the fourth PMOS power tube; the second resistor is connected between the drain electrode of the fifth PMOS power tube and the reference ground;
the first end of the current source is connected with the working voltage; the drain electrode of the first NMOS power tube is connected with the second end of the current source, the grid electrode of the first NMOS power tube is connected with the drain electrode of the first NMOS power tube, and the source electrode of the first NMOS power tube is connected with the reference ground; the source electrode of the sixth PMOS power tube is connected with the drain electrode of the third PMOS power tube, the grid electrode of the sixth PMOS power tube is connected with the grid electrode of the fourth PMOS power tube, and the drain electrode of the sixth PMOS power tube is connected with the grid electrode; the drain electrode of the second NMOS power tube is connected with the drain electrode of the sixth PMOS power tube, the grid electrode of the second NMOS power tube is connected with the grid electrode of the first NMOS power tube, and the source electrode of the second NMOS power tube is connected with the reference ground;
The source electrode of the seventh PMOS power tube is connected with the working voltage, and the grid electrode of the seventh PMOS power tube is connected with the drain electrode; the drain electrode of the third NMOS power tube is connected with the drain electrode of the seventh PMOS power tube, the grid electrode of the third NMOS power tube is connected with the grid electrode of the second NMOS power tube, and the source electrode of the third NMOS power tube is connected with the reference ground; the source electrode of the eighth PMOS power tube is connected with the working voltage, and the grid electrode of the eighth PMOS power tube is connected with the grid electrode of the seventh PMOS power tube; the source electrode of the ninth PMOS power tube is connected with the drain electrode of the eighth PMOS power tube, and the grid electrode of the ninth PMOS power tube is connected with the reference signal; the drain electrode of the fourth NMOS power tube is connected with the grid electrode, and the source electrode of the fourth NMOS power tube is connected with the reference ground; the source electrode of the tenth PMOS power tube is connected with the drain electrode of the eighth PMOS power tube, and the grid electrode of the tenth PMOS power tube is connected with the second regulating unit; the drain electrode of the fifth NMOS power tube is connected with the drain electrode of the tenth PMOS power tube, the grid electrode of the fifth NMOS power tube is connected with the grid electrode of the fourth NMOS power tube, and the source electrode of the fifth NMOS power tube is connected with the reference ground;
The source electrode of the eleventh PMOS power tube is connected with the working voltage, and the grid electrode of the eleventh PMOS power tube is connected with the drain electrode; the drain electrode of the sixth NMOS power tube is connected with the drain electrode of the eleventh PMOS power tube, the grid electrode of the sixth NMOS power tube is connected with the drain electrode of the fifth NMOS power tube, and the source electrode of the sixth NMOS power tube is connected with the second regulating unit; the source electrode of the twelfth PMOS power tube is connected with the working voltage, the grid electrode of the twelfth PMOS power tube is connected with the grid electrode of the eleventh PMOS power tube, and the drain electrode of the twelfth PMOS power tube is connected with the drain electrode of the fourth PMOS power tube; and the drain electrode of the seventh NMOS power tube is connected with the drain electrode of the twelfth PMOS power tube, and the source electrode of the seventh NMOS power tube is connected with the reference ground.
2. The current regulation circuit of claim 1, wherein: the parameters of the first resistor and the second resistor are the same; the parameters of the third resistor and the fourth resistor are the same; the parameters of the first PMOS power tube and the second PMOS power tube are the same; the parameters of the fourth PMOS power tube, the fifth PMOS power tube and the sixth PMOS power tube are the same; the parameters of the seventh PMOS power tube and the eighth PMOS power tube are the same; the parameters of the ninth PMOS power tube and the tenth PMOS power tube are the same; the eleventh PMOS power tube and the twelfth PMOS power tube have the same parameters; the parameters of the first NMOS power tube, the second NMOS power tube and the third NMOS power tube are the same; and the parameters of the fourth NMOS power tube and the fifth NMOS power tube are the same.
3. The current regulation circuit of claim 1, wherein: the timing adjustment subunit includes: a first not gate, a second not gate, a third not gate, a fourth not gate, a fifth not gate, a sixth not gate, a first nand gate, a second nand gate, a first nor gate, a delay component, an eighth NMOS power transistor, and a first comparator, wherein: the input end of the first NOT gate is connected with the first control signal; the input end of the delay component is connected with the output end of the first NOT gate; the input end of the second NOT gate is connected with the output end of the delay component; the input end of the third NOT gate is connected with the output end of the second NOT gate; the input end of the first NAND gate is connected with the output end of the first NAND gate and the output end of the third NAND gate; the input end of the fourth NAND gate is connected with the output end of the first NAND gate; the input end of the first NOR gate is connected with the output end of the fourth NOR gate and the output end of the first NOR gate; the drain electrode of the eighth NMOS power tube is connected with the output end of the delay component, the grid electrode of the eighth NMOS power tube is connected with the output end of the first NOR gate, and the source electrode of the eighth NMOS power tube is connected with the reference ground; the input end of the fifth NOT gate is connected with the output end of the fourth NOT gate, and the output end of the fifth NOT gate is connected with the grid electrode of the seventh NMOS power tube; the non-inverting input end of the first comparator is connected with the drain electrode of the fourth PMOS power tube, the inverting input end of the first comparator is connected with the drain electrode of the fifth PMOS power tube, and the enabling end of the first comparator is connected with the output end of the fourth NOT gate; the input end of the second NAND gate is connected with the output end of the first comparator and the output end of the fourth NAND gate; and the input end of the sixth NOT gate is connected with the output end of the second NOT gate, and the adjusting signal is output.
4. A current regulating circuit according to claim 3, wherein: the delay component comprises a fifth resistor and a first capacitor, wherein: the first end of the fifth resistor is connected with the output end of the first NOT gate; the first capacitor is connected between the second end of the fifth resistor and the reference ground.
5. The current regulation circuit of claim 1, wherein: the second adjustment unit includes a sixth resistor.
6. The current regulation circuit of claim 5, wherein: the sixth resistor comprises an adjustable resistor.
7. The current regulation circuit of claim 1, wherein: the modulation mode of the modulation module comprises pulse width modulation.
8. A chip, characterized in that: the chip comprises: the current regulating circuit according to any one of claims 1-7, for regulating the current of the inductor in the DCDC voltage reducing circuit, wherein the number of DCDC voltage reducing circuits is equal to the number of the current regulating circuits, and the DCDC voltage reducing circuits are in one-to-one correspondence with the current regulating circuits.
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