CN116964937A - Electromagnetic interference mitigation for switching regulators - Google Patents

Abstract

In a switching regulator driver (400), a sense circuit (402) has a transistor current input and a sense circuit output. The logic circuit (404) has a logic circuit input, a first output, and a second output. The logic circuit input is coupled to the sense circuit output. The counter (406) has a counter clock input, a counter control input, and a counter output. The counter clock input is coupled to the first output. The counter control input is coupled to the second output. The counter (406) is configured to provide a count value at a counter output. A programmable drive strength circuit (408) has a drive strength circuit input and a transistor control output. The drive strength circuit input is coupled to the counter output. The programmable drive strength circuit (408) is configured to adjust the drive current at the transistor control output based on the count value.

Description

Electromagnetic interference mitigation for switching regulators

Background

Switching regulators are electronic circuits that convert an input Direct Current (DC) voltage to a DC output voltage that is higher or lower in magnitude than the input DC voltage. Various types of switching regulators are available. Examples include buck converters, boost converters, buck-boost converters, and the like.

For example, a buck converter includes a high-side transistor (also operating as a switch) coupled to a low-side transistor (operating as a switch) at a switching node. The controller asserts the control signal to reciprocally turn on and off the high-side transistor and the low-side transistor to alternately turn on (a) a current path from the input voltage through the high-side transistor and through the switching node to the inductor and the capacitor and (b) a current path from ground through the low-side transistor and through the switching node to the inductor and the capacitor. By reciprocally turning on and off the high side transistor and the low side transistor, a square wave voltage is generated on the switching node (switching between approximately the input voltage and ground). The duty cycle of the square wave is a function of the applied input voltage and the target output voltage and is implemented by the controller of the high-low side transistor. The inductor and capacitor then filter the square wave to generate a DC output voltage that can be used to power an electrical load.

Disclosure of Invention

In a switching regulator driver, a sense circuit has a transistor current input and a sense circuit output. The logic circuit has a logic circuit input, a first output and a second output. The logic circuit input is coupled to the sense circuit output. The counter has a counter clock input, a counter control input, and a counter output. The counter clock input is coupled to the first output. The counter control input is coupled to the second output. The counter is configured to provide a count value at a counter output. The programmable drive strength circuit has a drive strength circuit input and a transistor control output. The drive strength circuit input is coupled to the counter output. The programmable drive strength circuit is configured to adjust the drive current at the transistor control output based on the count value.

Drawings

Fig. 1 illustrates a portion of a buck converter according to an example.

Fig. 2 is a timing diagram illustrating the ringing of the switching node voltage of a buck converter according to an example.

Fig. 3 is a timing diagram illustrating operation of a driver for reducing switching node voltage ringing according to an example.

Fig. 4 is a schematic diagram illustrating a transistor driver for reducing switching node voltage ringing according to an example.

Detailed Description

As described above, the switching regulator converts an input voltage into an output voltage having a different (higher or lower) amplitude than the input voltage. In a switching regulator, one or more transistors are turned on and off so that a waveform with a particular duty cycle is generated at a switching node. Fig. 1 illustrates a portion of a buck converter in which a high-side (HS) transistor is coupled to a low-side (LS) transistor at a switching node 110. In this example, the HS switch and the LS switch are both n-channel field effect transistors (NFETs), but in other examples they may be implemented as other types of transistors. The drain of the HS transistor is coupled to the input voltage (Vin) and the source of the LS transistor is coupled to ground. The voltage on the switch node 110 is designated as Vsw. The inductor L1 is coupled to a switch and a capacitor Cout. The connection between the inductor L1 and the capacitor Cout is the output (Vout) of the voltage regulator. The driver 102 has an input receiving a digital input signal hs_en from the controller 101. The driver 102 has an output coupled to the gate of the HS transistor. When hs_en is asserted (e.g., logic high) by controller 101, driver 102 responds by generating a voltage on its output to turn on the HS transistor, and current i_hs flows from Vin through the HS transistor and through switching node 110 to inductor L1. Similarly, driver 104 has an input that receives a digital input signal LS_EN from the controller, and also has an output coupled to the gate of the LS transistor. When LS_EN becomes active (e.g., logic high), driver 104 responds by generating a voltage on its output to turn on the LS transistor. When the LS transistor is turned on, a current I_ls flows from ground through the LS transistor and through the switch node 110 to the inductor L1.

Fig. 1 also shows the parasitic inductance lp_hs between the input voltage Vin and the drain of the HS transistor. There is also another parasitic inductance Lp-LS between the source of the LS transistor and ground. These parasitic inductances are caused, for example, by connections to and traces within the circuit board on which the switching regulator is mounted.

To avoid shoot-through current, controller 101 does not command drivers 102 and 104 to turn on both the HS and LS transistors simultaneously. Instead, the controller 101 implements "dead time" between on/off state switching of the HS transistor and the LS transistor. For example, if the HS transistor is on (and the LS transistor is off), the controller 101 first disables hs_en (e.g., logic low) to turn off the HS transistor. After a short period of time (dead time) has elapsed to ensure that the HS transistor is off, the controller then causes ls_en to become active so that driver 104 turns on the LS transistor. Dead time is also imposed after the LS transistor is turned off and before the HS transistor is turned on.

The switching regulator switches the on/off states of the HS and LS transistors at an application specific frequency. In one example, the switching frequency is in the range of 100KHz to 1 MHz. During each switching cycle, both the HS transistor and the LS transistor are turned on (although not simultaneously). Fig. 2 is a timing diagram illustrating a portion of one such switching cycle. At 201, the LS transistor is turned on and the HS transistor is turned off. The LS_EN signal goes inactive (falling edge 202) and then a dead time 203 occurs during which none of the transistors is turned on. The controller 101 makes hs_en active high (rising edge 204).

Waveform 211 is the current (i_ls) flowing through the LS transistor. Waveform 213 is the current (i_hs) flowing through the HS transistor. A finite amount of time is required to cause the LS transistor to turn off completely after the next edge 202 of ls_en and stop conducting current, and to cause HS to turn on completely after the rising edge 204 of hs_en. The current i_ls drops rapidly (as shown at 205) and the current i_hs increases rapidly (as shown at 206). Waveforms 211 and 214 illustrate that ringing may occur on current i_hs and current i_ls when the respective transistors switch states (HS transistor on and LS transistor off). Ringing occurs because a resonant circuit is formed that includes lp_hs, the channel resistance of the HS transistor, and the parasitic capacitance of the switching node 110. Waveform 214 shows the switch node voltage Vsw. Vsw is initially low when LS transistor is on, then during dead time 203 as shown at 221, it drops slightly to a negative value as the body diode of LS transistor is forced forward biased to maintain continuous flow of inductor current, then rises as HS transistor is on and ringing also occurs.

Ringing on the switching node 110 may create conductive and radiative high frequency electromagnetic interference (EMI) that may, unfortunately, be received by other components in the system that share the same voltage domain Vin, for example. For example, in an automobile where Vin is battery voltage, other circuits in the automobile may receive EMI signals from the voltage regulator. The technique described herein for reducing ringing in a switching regulator is to reduce the drive current to the gate of the HS transistor during a portion of the process of turning on the HS transistor during which a higher level of ringing would otherwise occur.

According to various examples, an adaptive high-side gate driver is described herein that divides the drive current into the gates of HS transistors into three phases. In the first stage, a relatively large magnitude but short duration drive current is supplied to the gate of the HS transistor. The high current pulse causes the gate-to-source voltage (Vgs) to quickly reach the threshold voltage of the transistor. When Vgs of the HS transistor increases toward the threshold voltage, the HS transistor is still in an off state and cannot conduct any drain current, and thus no switch node ringing can occur during this period. In a second, subsequent phase, the drive current is reduced to a lower level to suppress the switching node ringing. When the switch node voltage begins to rise, the adaptive high-side gate driver increases the magnitude of the drive current into the gate of the HS transistor to complete the transistor turn-on process. As described herein, the magnitude of the drive current during the second phase is programmable so that the drive current is as large as possible to turn on the transistor quickly, but not so large as to cause excessive ringing on the switch node.

Embodiments described herein relate to adaptive drivers for HS transistors. A similar adaptive driver for the LS transistor may not be included because the body diode of the LS transistor is already on before the LS transistor is "on" and by the time the transistor is on, the effect on the lp_ls parasitic inductance due to the rate of change of current through the LS transistor has subsided.

Fig. 3 is a timing diagram illustrating a comparison between a switching regulator including an adaptive high-side gate driver as described herein and a switching regulator including a conventional high-side gate driver. Conventional high-side gate drivers cause a large drive current to flow into the gate of the HS transistor to turn on the transistor. The dashed waveform is for a conventional high-side gate driver and the solid curve is for an adaptive high-side gate driver. At time t0, the controller asserts the hs_en signal (not shown in fig. 3) to cause the gate driver to begin turning on the HS transistor.

For a conventional high-side gate driver, the driver rapidly increases the drive current to the gate of the HS transistor (as indicated at 301) and maintains this high level of drive current (as indicated at 302) until the HS transistor is fully on. When the channel of the HS transistor starts to conduct, the drain current (Id (HS)) increases very rapidly as shown at 303 and then stabilizes at steady state current (304). As indicated at 305, a high degree of ringing occurs on the switching node.

For the adaptive high-side gate driver described herein, the drive current into the gate is also high during the initial phase 311, so that the Vgs of the transistor reaches the threshold voltage. However, instead of maintaining the drive current at a high level (as in conventional high-side gate drivers), the adaptive high-side gate driver reduces the drive current, as indicated at 306. In one embodiment, the initial phase 311 occurs for a fixed period of time (e.g., 2 ns). The gate current during the second stage 312 is adaptively configured high as described herein to complete the on process of the HS transistor, but at the same time the rate of change of the drain current is reduced as indicated at 307 (compared to the higher rate of change at 303 for conventional high-side gate drivers). By forcing the drain current to increase at a lower rate, the ringing that occurs on the switching node is much smaller, as indicated at 308. The third stage 313 begins in response to the adaptive high-side gate driver detecting that the switching node voltage Vsw begins to rise (as indicated at 309). When Vsw is determined to rise, then the drive current to the HS transistor may be increased again (310) without further exacerbating any switch node ringing.

Referring again to fig. 1, a rapid increase in drain current i_hs through the HS transistor will result in a voltage drop across parasitic inductance lp_hs. The magnitude of the voltage drop across parasitic inductance lp_hs is the product of the rate of change of i_hs and the inductance of lp_hs. Therefore, as the rate of change of i_hs increases, the voltage drop across parasitic inductance lp_hs also increases. The upper terminal of lp_hs is coupled to Vin (which is a fixed voltage). Thus, the voltage drop across the parasitic inductance lp_hs will necessarily result in a voltage drop across the lower terminal of the inductance. The lower terminal of the parasitic inductance lp_hs is the voltage on the drain of the HS transistor. By monitoring the voltage on the drain of the HS transistor, it can be determined how fast i_hs increases when the HS transistor is turned on, as described below. The adaptive high-side gate driver compares the voltage on the drain of the HS transistor with a threshold. If the drain voltage of the HS transistor exceeds the threshold, which indicates that excessive ringing may occur on I_hs and switch node 110, then in the next switching cycle the adaptive high-side gate driver reduces the drive current to the gate of the HS transistor during second phase 312 (FIG. 3). In each subsequent switching cycle, the adaptive high-side gate driver continues to reduce the drive current to the gate of the HS transistor until the voltage on the drain of the HS transistor no longer exceeds the threshold.

Fig. 4 is a schematic diagram illustrating an embodiment of an adaptive high-side gate driver that may be used to implement gate driver 102 of fig. 1. The right side of the schematic shows the HS transistor coupled to the LS transistor at switch node 110. The adaptive high-side gate driver 400 includes a sensing circuit 402, a logic circuit 404, a counter 406, a programmable drive strength circuit 408, a switching node transition detection circuit 410, an or gate 412, nand gates 441-444, a one-shot (one-shot) 430, and a decoder 432. The description of driver 400 is described below for three phases of the on process of the HS transistor.

As described above, the initial phase is a fixed (but short) period of time during which a relatively high level of drive current is provided to the gate of the HS transistor. The hs_en signal is coupled to an input of a monostable flip-flop 430. Monostable flip-flop 430 has an output coupled to an input of or gate 412. The output of OR gate 412 (and signal 415 on the output of OR gate) is coupled to the "full select" input of decoder 432. Decoder 432 has a plurality of outputs, each of which is coupled to an input of a respective nand gate 441-444. The other inputs of NAND gates 441 through 444 receive the HS_EN signal. The programmable drive strength circuit 408 includes a plurality of PFETs 451 through 454. The outputs of NAND gates 441 through 444 are coupled to the gates of respective PFETs 451 through 454. In response to both inputs of nand gates 441 through 444 being at a logic high level, the output signal of the gate will be at a logic low level. Thus, with hs_en at a logic high level (such that the adaptive high-side gate driver 400 begins turning on the HS transistor), the output of the nand gates 441-444 will go to a logic low level in response to the output of the corresponding decoder effectively going high, turning on that particular PFET 451-454. With a given PFET 451-454 on, the drive current flows through the PFET to the gate of the HS transistor. Decoder 432 thus turns on one or more of PFETs 451 through 454, thereby controlling the amount of drive current into the gate of the HS transistor.

In response to the rising edge on hs_en, which initiates the on process of the HS transistor, the monostable 430 generates an output pulse (logic high) for the duration implemented by the monostable. In one example, the width of the output pulse of the monostable flip-flop is 2ns, but may be other than 2ns as desired. The width of the output pulse of the monostable is an amount of time that approximates the time required to cause the Vgs of the HS transistor to increase from 0V to its threshold voltage. The short duration of the positive output pulse of the monostable 430 results in a similar output pulse for signal 415 on the output of or gate 412 (in which period the other input of or gate 412 is at a logic low level). Decoder 432 receives a short duration pulse on signal 415 on its "full select" input, which in response causes all of the decoder's output signals to nand gates 441 through 444 to go effectively high. At this point, both inputs of nand gates 441 through 444 are at a logic high level, which causes the output signals from nand gates 441 through 444 to the gates of all PFETs 451 through 454 within programmable driver strength circuit 408 to be at a logic low level, turning on all PFETs 451 through 454 to provide a large drive current (maximum current that programmable driver strength circuit 408 can produce) to the gates of the HS transistors.

The high level of drive current supplied by the programmable driver strength circuit 408 to the gate of the HS transistor during this initial phase causes the Vgs of the HS transistor to rapidly rise toward the threshold voltage of the HS transistor. Then, the output pulse of the monostable flip-flop is again shifted to the low level, which causes the output signal 415 of the or gate 414 to become a logic low level. The signal 415 goes to a logic low level coincident with the end of the first phase 311 and the beginning of the second phase 312.

The second stage 312 begins with decoder 432 switching on all PFETs 451 through 454 to only a subset of the PFETs on based on count value CNT1 from counter 406. By turning on some, but not all, of PFETs 451 through 454, the magnitude of the drive current to the gate of the HS transistor may be reduced (as indicated at 306 in fig. 3). During the second phase 312, vgs of the HS transistor has reached the threshold voltage and drain current begins to flow through the HS transistor. The sensing circuit 402 includes a capacitor C1 and resistors R1 and R2. C1 is coupled between VIN (and thus the drain 427 of the HS transistor) and R1. Node a is the connection point between C1 and R1. The combination of C1 and R1 forms a high pass filter to high pass filter the voltage on the drain of the HS transistor. As described above, due to the parasitic inductance lp_hs (fig. 1), a sudden inrush of drain current into the gate of the HS transistor may cause a voltage drop on the drain of the HS transistor (whose magnitude is proportional to the rate of change of the current flowing through the HS transistor).

Logic circuit 404 includes comparators 421 and 422, a double latch 424, a common gate 426, and a flip-flop 428. In this example, comparators 421 and 422 are current comparators, but they may also be implemented as voltage comparators in other embodiments. In this example, the positive inputs (+) of comparators 421 and 422 are coupled together and to resistor R2. The voltage on the positive input comparator is approximately constant. The current i_r2 flowing through R2 is thus a function of the voltage on node a, and the voltage on node a is the filtered output of the high pass filter comprising C1 and R1. As the voltage on the drain of HS drops sharply, the voltage on node a also drops. The current i_r2 increases due to the drop in voltage on node a.

Comparator 421 compares current I_R2 with reference current IREF 1. Comparator 422 compares current i_r2 with reference current IREF 2. In one embodiment, IREF2 is a greater current than IREF 1. COMP1 is the output signal of the comparator 421, and COMP2 is the output signal of the comparator 422. In response to I_R2 being greater than IREF2, comparator 422 effectively changes COMP2 to a logic high state. In response to I_R2 being less than IREF2, comparator 422 forces COMP2 to a logic low state. Similarly, in response to I_R2 being greater than IREF1, comparator 421 effectively changes COMP1 to a logic high state. In response to I_R2 being less than IREF1, comparator 421 forces COMP1 to a logic low state. Thus, COMP1 and COMP2 indicate whether i_r2 is higher than two reference currents, lower than two reference currents, or between these reference currents.

A larger i_r2 than two reference currents indicates that the drain current through the HS transistor is increasing at a sufficiently high rate that excessive ringing may occur on the switch node 110 and thus the drive current to the gate of the HS transistor should be reduced. I_R2 is less than IREF2 but greater than IREF1 (i.e., I_R2 is in the range between these reference currents) indicates that the rate of change of the drain current (I_hs) of the HS transistor is not so great as to produce deleterious switch node voltage ringing and that the drive current should not be changed. I_R2 below two reference currents indicates: although detrimental switch node voltage ringing is unlikely, the magnitude of the drive current to the gate of the HS transistor can be increased to speed up the HS transistor turn-on process without generating excessive switch node voltage ringing.

COMP1 and COMP2 are latched by the double latch 424. The signal to the clock input of the double latch 424 is L2H, which is the output signal of the comparator 461 within the switching node transition detection circuit 410 (described below). The comparator 461 compares the switching node voltage Vsw with a reference voltage (substantially 0V) to detect when Vsw rises. The signal L2H is the output signal of the comparator 461, and thus it effectively goes high in response to the Vsw beginning to increase (at point 309 in fig. 3).

The latched COMP2 signal is coupled to the up/down control input of the counter 406. The latched COMP2 signal to the up/down control input is at a logic low level causing counter 406 to count up (i.e., increment its output count value CNT 1). Alternatively, the latched COMP2 signal to the up/down control input is a logic high level causing counter 406 to count down (decrement CNT 1). Counter 406 is clocked in response to a rising edge on the counter's clock input, and the clock signal to the counter is provided by the Q output of flip-flop 428. The data (D) input of flip-flop 428 is coupled to the output of the same gate 426. The latched COMP1 and COMP2 signals are coupled to the input of the same gate 426. When the inputs of the same gate 426 have opposite polarities (one input is 0 and the other input is 1), the output signal UPDATE of the same gate is logic 0. Otherwise (when both inputs are 0 or both inputs are 1), UPDATE is a logic 1.UPDATE is a logic 1 indicating that: (a) I_r2 is too large, which means that during the second phase of the subsequent cycle of the on-process of the HS transistor the drive current to the HS transistor should be reduced, or (b) i_r2 is too small that the drive current to the gate of the HS transistor should be increased. An UPDATE of logic 0 indicates that the drive current to the gate of the HS transistor should not be changed.

The flip-flop 428 is clocked by a signal labeled hs_on. In response to HS transistor fully turning ON (e.g., when the gate-source voltage of the transistor has reached its maximum value, indicating that the switching node voltage Vsw has reached and stabilized at a value close to the input voltage Vin), hs_on effectively goes high. Hs_en is connected to an active low CLR input which when active goes low causes the Q output (the clock input provided to counter 406) to be reset. In some embodiments, flip-flop 428 is replaced with an AND gate having UPDATE and HS_ON ON inputs. When I_R2 is greater than two reference currents IREF1 and IREF2 or when I_R2 is less than the two reference currents, UPDATE is a logic 1 and is clocked by flip-flop 428 to clock counter 406 to increment or decrement the output count value CNT1 of the counter. In one example, counter 406 is a 3-bit counter, and thus CNT1 is a 3-bit binary value. However, in other embodiments, the counter 406 may be a 2-bit or more than 3-bit counter.

The counting direction of the counter 406 is controlled by the latched COMP2 signal on the up/down control input of the counter. COMP2 is high in response to i_r2 being greater than iref2. IREF2 is greater than IREF1, and thus COMP2 is a logic high indicating that I_R2 is greater than two reference currents. In response to COMP2 being a logic high level, counter 406 is configured to count down, decrementing CNT1 the next time the counter is clocked. In response to COMP2 being a logic low level, counter 406 is configured to count up, incrementing CNT1 the next time the counter is clocked.

In the example of fig. 4, decoder 432 converts the binary CNT1 count value on its select input to a thermometric code and provides the thermometric code to nand gates 441-444. In one example, the programmable drive strength circuit 408 includes eight PFETs, and each of the eight PFETs has one nand gate 441-444. In this example, the 3-bit CNT1 value is converted by decoder 432 into an 8-bit thermometric code (minimum 1) for eight nand gates, turning on or off the eight PFETs individually. For example, if CNT1 is decimal 6 (binary 110), then the gate signals for seven of the eight PFETs (6 plus a minimum of 1) will be pulled low (the remaining gate signals are logic high), turning on the seven PFETs. If CNT1 is decimal 2 (binary 010), then the gate signals for three of the eight PFETs (2 plus a minimum of 1) will be pulled low (the remaining five gate signals are logic high), turning on only three of the eight PFETs.

COMP1 and COMP2 are latched by the double latch 424 when L2H from the comparator 461 goes active high when the HS transistor is fully on. The latched COMP1 and COMP2 signals are then used to control the counter 406 to cause a change in CNT1 (in the case where i_r2 is greater than two reference currents or less than two reference currents) to increase the drive current of the HS transistor (in the case where i_r2 is less than two reference currents) or decrease the drive current (in the case where i_r2 is greater than two reference currents). If I_R2 is between IREF1 reference current and IREF2 reference current, then UPDATE from the same gate is a logic 0, the output of flip-flop 428 is a logic 0 and counter 406 is not clocked, whereas if counter 406 is not clocked, CNT1 will not be updated and the drive current strength remains unchanged.

During the second phase 312 of the on-process of the HS transistor, the programmable drive strength circuit 408 is configured to adjust the magnitude of the drive current to the gate of the HS transistor based on the count value CNT1 from the counter 406. The example of fig. 4 includes a decoder 432 for converting the binary count value CNT1 into a thermometric code for turning PFETs 451 through 454 on and off. The PFETs are approximately equal in size and, therefore, the amount of current flowing through each PFET (when "on") to the gate of the HS transistor is approximately the same. In another embodiment, PFETs 451 through 454 may be binary weighted and thus drive current through one PFET is 1 times, drive current through the other PFET is 2 times, drive current through the other PFET is 4 times, and so on. In embodiments where PFETs 451 through 454 are binary weighted, the decoder may be omitted and binary count value CNT1 may be provided to nand gates 441 through 444.

In response to the switch node transition detection circuit 410 detecting a rise in the switch node voltage Vsw, the second phase 312 ends and the third phase 313 begins. The switching node transition detection circuit 410 generates an output signal 467 to the input of the or gate 412. When active high, the output signal 467 causes the signal 415 (through the or gate 412 and the nand gate 414) to go to logic high again (the signal 415 is logic high during the first stage 311 and then low during the second stage 312). With the signal 415 at a logic high level, the decoder 432 responds (as it did during the first stage 311) by causing all PFETs 451-454 within the programmable drive strength circuit 408 to turn on, thereby causing a larger drive current (310 in FIG. 3) to flow into the gate of the HS transistor.

The switching node transition detection circuit 410 includes a comparator 461, a driver delay compensation circuit 462, a flip-flop 463, a counter 464, a delay line 465, and a multiplexer 466. As described above, the comparator 461 makes the L2H signal effectively change to the logic high state, thereby indicating that Vsw is increasing. The L2H signal from comparator 461 is coupled to the D input of flip-flop 463. The driver delay compensation circuit 462 is a delay element (e.g., one or more serially connected buffers, inverters, etc.) that drives the clock input of the flip-flop 463. The trigger 463 determines the counting direction (up or down) of the counter 464. Counter 464 is clocked by hs_on every switching cycle and its output CNT2 determines the length of delay line 465 through multiplexer 466. The output 467 of multiplexer 466 is hs_en delayed by delay line 465 and is coupled to an input of or gate 412 (external to switching node transition detection circuit 410) and to an input of driver delay compensation circuit 462. The output 467 of multiplexer 466 effectively goes to a logic high level to initiate stage 313. The elements of the switching node transition detection circuit 410 together implement a time loop.

The purpose of the time loop created by the switch node transition detection circuit 410 is to align the intervention of all PFETs 451 through 454 within the programmable drive strength circuit 408 with the rising voltage of the switch node 110 and perform a comparison. However, it is often not sufficient to simply compare the output 467 of multiplexer 466 with the output (L2H) of comparator 461, as output 467 would cause, and thus always result in, L2H becoming active. Thus, the time correction is performed by the driver delay compensation circuit 462. The amount of delay added to signal 467 by driver delay compensation circuit 462 takes into account the total propagation delay of signal 467 through OR gate 412, decoder 432, NAND gates 441 through 444, the total propagation delay of the gate signal of programmable drive strength circuit 408 to the HS FET, and the delay of comparator 461. The drive delay compensation circuit 462 may be implemented using a series of logic gates connected in series to match the delays of the elements described above. In view of the extremely small variability of the total propagation delay of signal 467, when the third stage 313 should be started, the driver delay compensation circuit 462 generates a corresponding rising edge on the clock input of flip-flop 463.

Flip-flop 463 has an output Q and Qbar output. In this example, the Qbar output of flip-flop 463 is used. When the output signal from the driver delay compensation circuit 462 clocks the flip-flop 463, the Qbar output of the flip-flop will be either 0 or 1. If Vsw has begun to rise (L2H is 1) while flip-flop 463 is clocked, the Qbar output will be 0. Otherwise, if Vsw has not yet begun to rise (L2H is 0) while the flip-flop is clocked, the Qbar output will be 1. Thus, the flip-flop 463 acts as a time comparator and the logic state of the Qbar output indicates whether Vsw has begun to rise when the third phase 313 is expected to begin.

The Qbar output of flip-flop 463 is coupled to the up/down control input of counter 464. Counter 464 is an up/down counter that increments its output count value CNT2 in response to the logic state of the up/down control input being 1 and decrements CNT2 in response to the logic state of the up/down control input being 0.

The delay line 465 includes a plurality of delay elements 465a to 465d connected in series. Any number of delay elements may be present. In one example, each delay element 465 a-465 d implements a delay of 250 picoseconds (ps). The input to delay line 465 is hs_en. The output signal of the delay element 465a is hs_en delayed by 250 ps. Delay element 465b adds an additional 250ps delay and thus the output signal of delay element 465b is hs_en delayed by 500ps, and so on.

The connection points between adjacent delay elements within delay line 465 are tapped and provided to the inputs of multiplexer 466. The output count value CNT2 of the counter is a selection signal of the multiplexer 366. As CNT2 increases, the output signals of the latter delay (greater delay) elements 465a to 465d are selected as the output signals of the multiplexer. With the decrementing of CNT2, the output signals of the previous delay (smaller delay) elements 465a to 465d are selected as the output signals of the multiplexer.

The clock input to counter 464 is hs_on (described above). When the HS transistor is fully ON, hs_on goes active high and clocks counter 464 to increment or decrement CNT2. If Vsw has not yet begun to rise (L2H is 0) while flip-flop 463 is clocked, the up/down control input of counter 464 will be 1, which causes counter 464 to count up. If Vsw has begun to rise (L2H is 1) while trigger 463 is clocked, the up/down control input of counter 464 will be 0, which causes counter 464 to count down. The amount of time delay between the rising edge of hs_en and the rising edge of the multiplexer output signal 467 is incrementally adjusted until the time delay equals the duration of the second stage 312. When this occurs, the positive assertion of signal 467 from multiplexer 466 will cause decoder 432 to turn on all PFETs 451 through 454 in the programmable drive strength circuit during third stage 313.

As counter 464 counts up to increase the time delay, eventually the flip-flop will clock at the point where Vsw has begun to rise, which means that the D input of the flip-flop will be 1, the qbar output will be 0, and the up/down control input of the counter will be 0. In the case where the up/down control input is 0, the counter will be configured to count down at this point. In each subsequent switching cycle, the counter 464 may switch between being configured as an up counter and being configured as a down counter. However, the amount of time delay (e.g., 250 ps) of the delay elements 465 a-465 d is small enough that repeatedly changing the starting point of the third stage 313 is insufficient to substantially increase ringing on the switch node 110.

The term "coupled," as used herein, may encompass a connection, communication, or signal path that enables a functional relationship consistent with the disclosure. For example, if device a generates a signal to control device B to perform an action, then: (a) In a first example, device a is coupled to device B through a direct connection; or (B) in a second example, device a is coupled to device B through intermediate component C, provided that intermediate component C does not change the functional relationship between device a and device B, and device B is therefore controlled by device a via the control signals generated by device a.

A device "configured to" perform a task or function may be configured (e.g., programmed and/or hardwired) by a manufacturer at the time of manufacture to perform the function, and/or may be configured (or reconfigurable) by a user after manufacture to perform the function and/or other additional or alternative functions. The configuration may be performed by firmware and/or software programming the device, by constructing and/or laying out hardware components and interconnections of the device, or a combination thereof.

As used herein, the terms "terminal," "node," "interconnect," "pin," and "lead" are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to refer to the endpoints of, or the interconnections between, device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components.

Circuits or devices described herein as including certain components may alternatively be adapted to couple with those components to form the described circuitry or devices. For example, structures described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and/or inductors), and/or one or more power sources (e.g., voltage and/or current sources) may instead include only semiconductor elements within a single physical device (e.g., a semiconductor die and/or Integrated Circuit (IC) package), and may be adapted to couple with at least some of the passive elements and/or power sources at the time of manufacture or after manufacture (e.g., by an end user and/or a third party) to form the described structures.

Although the use of specific transistors is described herein, other transistors (or equivalent devices) may alternatively be used. For example, a p-channel field effect transistor ("PFET") may be replaced by an NFET with little or no change to the circuit. In addition, other types of transistors (e.g., bipolar Junction Transistors (BJTs)) may also be used.

Reference herein to a Field Effect Transistor (FET) being "on" means that the conductive channel of the FET is present and that drain current flows through the FET. Reference herein to a FET being "off" means that the conductive channel is not present and that drain current does not flow through the FET. However, an "off" FET may have a current flowing through the body diode of the transistor.

The circuits described herein may be reconfigured to include additional or different components to provide functions at least partially similar to those available prior to component replacement. Unless otherwise indicated, components shown as resistors generally represent any one or more elements coupled in series and/or parallel to provide an amount of impedance represented by the illustrated resistors. For example, the resistors or capacitors shown and described herein as a single component may alternatively be a plurality of resistors or capacitors, respectively, coupled in parallel between the same nodes. For example, the resistors or capacitors shown and described herein as a single component may alternatively be a plurality of resistors or capacitors, respectively, coupled in series between the same two nodes as the single resistor or capacitor.

The term "ground" as used in the above description includes chassis ground, floating ground, virtual ground, digital ground, common ground, and/or any other form of ground connection that may be suitable or adapted for the teachings herein. Unless otherwise indicated, herein, "about," "approximately," or "substantially" preceding a parameter means within +/-10% of the parameter.

Modifications to the described embodiments are possible within the scope of the claims, and other embodiments are also possible.

Claims (20)

1. A switching regulator driver, comprising:

a sense circuit having a transistor current input and a sense circuit output;

a logic circuit having a logic circuit input coupled to the sense circuit output, and a first output and a second output;

a counter having a counter clock input, a counter control input and a counter output, the counter clock input coupled to the first output, the counter control input coupled to the second output, and the counter configured to provide a count value at the counter output; and

A programmable drive strength circuit having a drive strength circuit input and a transistor control output, the programmable drive strength circuit configured to adjust a drive current at the transistor control output based on the count value.

2. The switching regulator driver of claim 1 further comprising a decoder coupled between the counter output and the drive strength circuit input.

3. The switching regulator driver of claim 1, wherein the logic circuit is configured to: detecting whether a rate of change of a drive current at a control output of the transistor is above a threshold; and in response to the rate of change of the drive current being above the threshold, adjusting the first output or the second output to change the count value.

4. The switching regulator driver of claim 1, wherein the logic circuit is configured to:

detecting whether a signal indicative of a rate of change of drive current at the transistor control output is above a first threshold and a second threshold;

responsive to the signal being above the first and second thresholds, adjusting the first or second output to increment the count value; and is also provided with

In response to the signal being below the first threshold and the second threshold, the first output or the second output is adjusted to decrement the count value.

5. The switching regulator driver of claim 4, wherein the logic circuit is configured to: in response to the signal being between the first threshold and the second threshold, the first output or the second output is adjusted to prevent the counter from incrementing or decrementing the count value.

6. The switching regulator driver of claim 1 wherein the sensing circuit comprises a high pass filter.

7. The switching regulator driver of claim 1, wherein the logic circuit comprises:

a first comparator having a comparator output and first and second comparator inputs, wherein the comparator output is the second output;

a second comparator having a second comparator output and third and fourth comparator inputs;

an exclusive or gate having a gate output and first and second gate inputs, the first gate input coupled to the first comparator output and the second gate input coupled to the second comparator output; and

A flip-flop having a flip-flop input and a flip-flop output, wherein the flip-flop output is the first output and the flip-flop input is coupled to the gate output.

8. The switching regulator driver of claim 1, wherein:

the logic circuit is configured to: detecting whether a rate of change of a drive current at a control output of the transistor is above a threshold; and responsive to the rate of change of the drive current being above the threshold, adjusting the first output or the second output to change the count value;

the programmable drive strength circuit is configured to reduce the drive current in response to the changed count value;

the switching regulator driver further includes a transistor turn-on detection circuit configured to: detecting whether the transistor is turned on; and in response to detecting that the transistor has turned on, providing a signal to the logic circuit; and is also provided with

The programmable drive strength circuit is configured to increase the drive current at the transistor in response to a provided signal.

9. The switching regulator driver of claim 1, wherein the transistor current input is a first transistor current input, and further comprising:

A comparator having a second transistor current input and a comparator output;

a delay circuit having a delay circuit output; and

a flip-flop having a flip-flop clock input, a data input and a flip-flop output, the flip-flop clock input coupled to the delay circuit output and the data input coupled to the comparator output.

10. The switching regulator driver of claim 9, wherein the counter is a first counter and the switching regulator driver further comprises a second counter having a second control input coupled to the trigger output.

11. A switching regulator driver, comprising:

a sense circuit having a transistor current input and a sense circuit output;

a first comparator having a first comparator output and first and second comparator inputs, the first comparator input coupled to the sense circuit output and the second comparator input coupled to a first reference terminal;

a second comparator having a second comparator output and third and fourth comparator inputs, the third comparator input coupled to the sense circuit output and the fourth comparator input coupled to a second reference terminal;

A logic gate having a logic gate output and first and second logic gate inputs, the first logic gate input coupled to the first comparator output and the second logic gate input coupled to the second comparator output;

a counter having a counter clock input, a counter control input and a counter output, the counter clock input coupled to the logic gate output, the counter control input coupled to the second comparator output, and the counter configured to provide a count value at the counter output; and

a programmable drive strength circuit having a drive strength circuit input and a transistor control output, the programmable drive strength circuit configured to adjust a drive current at the transistor control output based on the count value.

12. The switching regulator driver of claim 11 wherein the logic gate is an exclusive or gate.

13. The switching regulator driver of claim 11, further comprising a flip-flop coupled between the logic gate output and the counter clock input.

14. The switching regulator driver of claim 11 wherein the sensing circuit comprises a high pass filter.

15. The switching regulator driver of claim 11, wherein the transistor current input is a first transistor current input, and further comprising:

a third comparator having a second transistor current input and a third comparator output;

a delay circuit having a delay circuit output; and

a flip-flop having a flip-flop clock input, a data input and a flip-flop output, the flip-flop clock input being coupled to the delay circuit output and the data input being coupled to the third comparator output.

16. A switching regulator driver, comprising:

a sense circuit having a transistor current input and a sense circuit output;

a logic circuit having a logic circuit input coupled to the sense circuit output, and a first output and a second output;

a programmable drive strength circuit having a drive strength circuit input and a transistor control output; and

A counter having a counter clock input, a counter control input, and a counter output, the counter clock input coupled to the first output, the counter control input coupled to the second output, and the counter configured to:

providing a first count value at the counter output during a phase of a turn-on process, wherein the programmable drive strength circuit is configured to provide a first level of drive current at the transistor control output in response to the first count value; and is also provided with

Providing a second count value at the counter output after providing the first count value, wherein the programmable drive strength circuit is configured to provide a second level of drive current at the transistor control output in response to the second count value, wherein the second level of drive current is greater than the first level of drive current.

17. The switching regulator driver of claim 16, further comprising a decoder coupled between the counter output and the drive strength circuit input, wherein the decoder is configured to convert the first count value and the second count value into signals, and the programmable drive strength circuit is configured to receive the signals at the drive strength circuit input.

18. The switching regulator driver of claim 16, wherein the logic circuit is configured to: detecting whether a rate of change of a drive current at a control output of the transistor is above a threshold; and in response to the rate of change of the drive current being above the threshold, adjusting the first output or the second output to change the count value.

19. The switching regulator driver of claim 16, wherein the logic circuit is configured to:

detecting whether a signal indicative of a rate of change of drive current at the transistor control output is above a first threshold and a second threshold;

responsive to the signal being above the first and second thresholds, adjusting the first or second output to increment the count value; and

in response to the signal being below the first threshold and the second threshold, the first output or the second output is adjusted to decrement the count value.

20. The switching regulator driver of claim 16, wherein the transistor current input is a first transistor current input, and further comprising:

a comparator having a second transistor current input and a comparator output;

A delay circuit having a delay circuit output; and

a flip-flop having a flip-flop clock input, a data input and a flip-flop output, the flip-flop clock input coupled to the delay circuit output and the data input coupled to the comparator output.