CN107546982B - PWM/PFM dual-mode control circuit - Google Patents
PWM/PFM dual-mode control circuit Download PDFInfo
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Abstract
The invention discloses a PWM/PFM dual-mode control circuit, which comprises a mode selection module, a PWM control module, a PFM control module and an oscillation module; the input end of the mode selection module is connected with the input end of the dual-mode control circuit, and the output end of the mode selection module is simultaneously connected with the control end of the PWM control module and the control end of the PFM control module; the output end of the PWM control module is connected with the control end of the oscillation module; the input end of the PFM control module is connected with the input end of the dual-mode control circuit, and the output end of the PFM control module is connected with the control end of the oscillation module; and the output end of the oscillation module is connected with the output end of the dual-mode control circuit and is used for generating and outputting an oscillation voltage. The loss of the functional module can be effectively reduced, and the efficiency of the system under the full load current is improved.
Description
Technical Field
The present invention relates to a DC-DC converter control circuit, and more particularly, to a PWM/PFM dual mode control circuit.
Background
For a Pulse Width Modulation (PWM) type DC-DC converter, the advantages of small output ripple, simple compensation structure, good stability, low noise and the like are commonly adopted in a power management chip, but in practical application, it is found that as the load is gradually reduced, the total power consumption proportion occupied by the on loss and the switching loss in the system is improved, that is, the system conversion efficiency is reduced, so that the efficiency required by a light load condition system cannot be met by a simple PWM control mode. Therefore, a Pulse Frequency Modulation (PFM) method is proposed, which can reduce the switching frequency of the system during light load and effectively improve the light load efficiency of the system.
There are various specific implementation manners of PFM control, namely, the earliest hysteresis voltage type PFM is used for controlling the stability of the output voltage according to the upper and lower limit thresholds of the set output voltage, but the magnitude of the inductor current cannot be controlled, so that people invent a hysteresis current type PFM control mode, and the mode can set the upper limit threshold of the sampling current to limit the peak value of the inductor current, so that the system is ensured not to be in an overcurrent state. In order to achieve both output voltage ripple and peak inductor current limitation, a peak current limiting PFM has been proposed, but one of the biggest drawbacks of this mode is that the maximum value of the set inductor sampling voltage is fixed, which results in the output ripple varying with the load current, and a large output ripple results in the conversion efficiency decreasing. Aiming at the problem, the self-adaptive current-limiting PFM and the dynamic inductance energy storage technology are generated, and the two technologies can obtain the self-adaptive adjustment of the inductance current through a self-adaptive feedback circuit, inhibit the overlarge output ripple and ensure the efficient operation of a system under light load.
Thus, to obtain system efficiency under full load conditions, one starts to control the DC-DC loop system using PWM/PFM dual mode technology so that the system operates in PWM mode for heavy load and PFM mode for light load. One conventional example is shown in fig. 1, and it can be seen that as the load increases, the error op-amp output voltage Vin in the main loop of the system also increases, so that the operation mode can be selected according to the Vin size, but in this example, the PWM mode and the PFM mode are independent of each other, and the system has three comparators, two RS flip-flops, an oscillator and a PWM/PFM control circuit, so that the system structure is complex, and the static loss is large.
Disclosure of Invention
The embodiment of the invention aims to provide a PWM/PFM dual-mode control circuit which can effectively reduce the loss of a functional module and improve the efficiency of a system under full load current.
In order to achieve the above objective, an embodiment of the present invention provides a PWM/PFM dual-mode control circuit, including a mode selection module, a PWM control module, a PFM control module, and an oscillation module; the input end of the mode selection module is connected with the input end of the dual-mode control circuit, and the output end of the mode selection module is simultaneously connected with the control end of the PWM control module and the control end of the PFM control module; the output end of the PWM control module is connected with the control end of the oscillation module; the input end of the PFM control module is connected with the input end of the dual-mode control circuit, and the output end of the PFM control module is connected with the control end of the oscillation module; and the output end of the oscillation module is connected with the output end of the dual-mode control circuit and is used for generating and outputting an oscillation voltage.
As an improvement of the scheme, the circuit further comprises a square root module, wherein the input end of the PFM control module is connected with the input end of the dual-mode control circuit through the square root module; the input end of the square root module is connected with the input end of the dual-mode control circuit, and the output end of the square root module is connected with the input end of the PFM control module and is used for outputting square root current which is in linear relation with the square root of the voltage of the input end of the dual-mode control circuit.
As an improvement of the above scheme, the mode selection module includes a first comparator, where an in-phase end of the first comparator is used to connect with a reference voltage, an opposite-phase end of the first comparator is connected with an input end of the mode selection module, and an output end of the first comparator is connected with an output end of the mode selection module.
As an improvement of the scheme, the PWM control module comprises a first inverter, a first NMOS tube, a first PMOS tube, a second PMOS tube and a current source; the input end of the first inverter is connected with the control end of the PWM control module, and the output end of the first inverter is connected with the grid electrode of the first NMOS tube; the source electrode of the first NMOS tube is connected with the drain electrode of the first PMOS tube, and the drain electrode of the first NMOS tube is connected with the output end of the PWM control module; the grid electrode of the first PMOS tube is connected with the current input end of the current source, and the source electrode of the first PMOS tube is connected with the power supply end; the grid electrode and the drain electrode of the second PMOS tube are both connected with the current input end of the current source, and the source electrode of the second PMOS tube is connected with the power supply end; and the current output end of the current source is connected with the grounding end.
As an improvement of the scheme, the PFM control module comprises a second PMOS tube, a second NMOS tube, a third PMOS tube and a current source; the grid electrode and the drain electrode of the second PMOS tube are both connected with the current input end of the current source, and the source electrode of the second PMOS tube is connected with the power supply end; the grid electrode of the second NMOS tube is connected with the control end of the PFM control module, the source electrode of the second NMOS tube is connected with the input end of the PFM control module, and the drain electrode of the second NMOS tube is connected with the output end of the PFM control module; the grid electrode of the third NMOS tube is connected with the grid electrode of the second NMOS tube, the source electrode of the third NMOS tube is connected with the drain electrode of the third PMOS tube, and the drain electrode of the third NMOS tube is connected with the output end of the PFM control module; the grid electrode of the third PMOS tube is connected with the current input end of the current source, and the source electrode of the third PMOS tube is connected with the power supply end; and the current output end of the current source is connected with the grounding end.
As an improvement of the scheme, the oscillation module comprises a first resistor, a second resistor, a third resistor, a first transmission gate, a second comparator, a second inverter, a fourth NMOS tube and a capacitor; the first resistor, the second resistor and the third resistor are sequentially connected in series between a grounding end and a power supply end; the input end of the first transmission gate is connected between the second resistor and the third resistor, the output end of the first transmission gate is connected with the same-phase end of the second comparator, the input end of the second transmission gate is connected between the first resistor and the second resistor, the output end of the second transmission gate is connected with the opposite-phase end of the second comparator, the positive control end of the first transmission gate and the negative control end of the second transmission gate are both connected with the output end of the second comparator, and the opposite control end of the first transmission gate and the opposite control end of the second transmission gate are both connected with the output end of the second inverter; the output end of the second comparator is connected to the output end of the oscillation module and the input end of the second inverter; the output end of the second inverter is connected to the grid electrode of the fourth NMOS tube; the source electrode of the fourth NMOS tube is connected with the control end of the oscillation module, and the drain electrode of the fourth NMOS tube is connected with the grounding end; one end of the capacitor is connected with the control end of the oscillation module, and the other end of the capacitor is connected with the grounding end.
As an improvement of the above scheme, the square root module includes a first amplifier, a second amplifier, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a fourth resistor, and a fifth resistor; the non-inverting terminal of the first amplifier is connected with the input terminal of the square root module, the inverting terminal of the first amplifier is connected with the grounding terminal through the fourth resistor, the output terminal of the first amplifier is connected with the grid electrode of the fifth NMOS tube, the source electrode of the fifth NMOS tube is connected with the drain electrode of the fourth PMOS tube, and the drain electrode of the fifth NMOS tube is connected with the grounding terminal through the fourth resistor; the source electrode of the fourth PMOS tube is connected with the power supply end, and the grid electrode of the fourth PMOS tube is connected with the drain electrode of the fourth PMOS tube and the grid electrode of the fifth PMOS tube; the source electrode of the fifth PMOS tube is connected with the power supply end, and the drain electrode of the fifth PMOS tube is connected with the source electrode of the sixth NMOS tube and the grid electrode of the sixth NMOS tube; the grid electrode of the sixth NMOS tube is connected with the same-phase end of the second amplifier, and the drain electrode of the sixth NMOS tube is connected with the source electrode of the seventh NMOS tube; the grid electrode of the seventh NMOS tube is connected with the inverting terminal of the second amplifier and the output terminal of the second amplifier, and the drain electrode of the seventh NMOS tube is connected with the grounding terminal; the drain electrode and the grid electrode of the sixth PMOS tube are connected to the output end of the second amplifier, and the source electrode of the sixth PMOS tube is connected to the power supply end; the drain electrode of the sixth PMOS tube is also connected to the source electrode of the seventh PMOS tube, and the grid electrode and the drain electrode of the seventh PMOS tube are both connected with the grounding end through the fifth resistor; the grid electrode of the eighth PMOS tube is connected with the grid electrode of the sixth PMOS tube, the source electrode of the eighth PMOS tube is connected with the power supply end, and the drain electrode of the eighth PMOS tube is connected with the output end of the square root module.
As an improvement of the above solution, the first comparator is a hysteresis comparator.
As an improvement of the above scheme, the oscillation module further includes an eighth NMOS transistor, a ninth NMOS transistor, and a tenth NMOS transistor; the grid electrode of the eighth NMOS tube is connected to the current output end of the current source, the source electrode of the eighth NMOS tube is connected to the control end of the oscillation module, and the drain electrode of the eighth NMOS tube is connected with the source electrode of the fourth NMOS tube; the source electrode of the fourth NMOS tube is connected with the control end of the oscillation module through the eighth NMOS tube; the source electrode and the grid electrode of the ninth NMOS tube are connected to the current output end of the current source, and the drain electrode of the ninth NMOS tube is connected to the source electrode of the tenth NMOS tube; the grid electrode of the tenth NMOS tube is connected with the grid electrode of the fourth NMOS tube, and the drain electrode of the tenth NMOS tube is connected with the grounding end; and the current output end of the current source is connected with the grounding end through the ninth NMOS tube and the tenth NMOS tube.
As an improvement of the scheme, the width-to-length ratio of the fourth PMOS tube is consistent with that of the fifth PMOS tube.
Compared with the prior art, the dual-mode control circuit of the PWM/PFM provided by the invention has the advantages that the mode selection module is used for starting the PWM control module under the heavy load condition according to the voltage value of the input end of the dual-mode control circuit, starting the PFM control module under the light load condition, generating a corresponding control signal by the PWM control module or the PFM control module, controlling the oscillation mode of the oscillating circuit, and obtaining the voltage of the corresponding PWM waveform or the voltage of the PFM waveform at the output end of the dual-mode control circuit. Because the PWM mode generating circuit formed by the PWM control module and the oscillation module and the PFM mode generating circuit formed by the PFM control module and the oscillation module are integrated in one oscillator control unit, and the mode selection module pair selects the working mode, the functional module of the circuit is reduced, the static power consumption of the circuit is reduced, the PFM mode is adopted to work under the light load condition, and the switching frequency range of the load current change system is more compact, so that the circuit is more stable under transient switching and steady-state interference, and the working efficiency under the full load current is improved.
Drawings
Fig. 1 is a circuit diagram of a PWM/PFM dual mode control circuit in an embodiment of the present invention.
Fig. 2 is a circuit diagram of a square root module in an embodiment of the invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1, a dual mode control circuit of PWM/PFM provided in an embodiment of the present invention includes a mode selection module, a PWM control module, a PFM control module, and an oscillation module. Preferably, the mode selection module includes a first comparator COM1; the PWM control module comprises a first inverter INV1, a first NMOS tube N1, a first PMOS tube P1, a second PMOS tube P2 and a current source I1; the PFM control module comprises a second PMOS tube P2, a second NMOS tube N2, a third NMOS tube N3, a third PMOS tube P3 and the current source I1; the oscillation module comprises a first resistor R1, a second resistor R2, a third resistor R3, a first transmission gate T1, a second transmission gate T2, a second comparator COM2, a second inverter INV2, a fourth NMOS tube N4 and a capacitor C.
A circuit structure of a PWM/PFM dual-mode control circuit according to an embodiment of the present invention will be described in detail with reference to fig. 1.
The control end of the mode selection module is connected with the input end Vin of the dual-mode control circuit, and the output end of the mode selection module is simultaneously connected with the control end of the PWM control module and the control end of the PFM control module.
Specifically, the non-inverting terminal of the first comparator COM1 is configured to be connected to the reference voltage Vr, the inverting terminal of the first comparator COM1 is connected to the input terminal of the mode selection module, that is, to the input terminal Vin of the dual-mode control circuit, and the output terminal of the first comparator COM1 is connected to the output terminal of the mode selection module. Preferably, the voltage value of the reference voltage Vr is a constant value between a maximum value and a minimum value of the voltage value of the input terminal Vin. When the voltage value of the input end Vin is smaller than the voltage value of the reference voltage Vr, the first comparator COM1 outputs a high level, that is, the mode selection module outputs a high level; when the voltage value of the input terminal Vin is greater than the voltage value of the reference voltage Vr, the first comparator COM1 outputs a low level, i.e., the mode selection module outputs a low level. Preferably, the first comparator COM1 is a hysteresis comparator, so as to avoid a false jump when the voltage value of the input terminal Vin is near the voltage value of the reference voltage Vr, thereby improving the stability of the dual-mode control circuit.
The control end of the PWM control module is connected with the output end of the mode selection module, and the output end of the PWM control module is connected with the input end of the oscillating circuit.
Specifically, an input end of the first inverter INV1 is connected to a control end of the PWM control module, and an output end of the first inverter INV1 is connected to a gate of the first NMOS transistor N1. The source electrode of the first NMOS tube N1 is connected with the drain electrode of the first PMOS tube P1, and the drain electrode of the first NMOS tube N1 is connected with the output end of the PWM control module. The grid electrode of the first PMOS tube P1 is connected with the current input end of the current source I1, and the source electrode of the first PMOS tube P1 is connected with the power supply end VCC. The grid electrode and the drain electrode of the second PMOS tube P2 are both connected with the current input end of the current source I1, and the source electrode of the second PMOS tube P2 is connected with the power supply end VCC. The current output end of the current source I1 is connected with the ground end GND. The grid electrode of the first PMOS tube P1 is communicated with the grid electrode of the second PMOS tube P2, the source electrode of the first PMOS tube P1 is communicated with the source electrode of the second PMOS tube P2, and the first PMOS tube P1 and the second PMOS tube P2 form a current mirror structure.
The control end of the PFM control module is connected with the output end of the mode selection module, the input end of the PFM control module is connected with the input end Vin of the dual-mode control circuit, and the output end of the PFM control module is connected with the control end of the oscillation module.
Specifically, the gate and the drain of the second PMOS transistor P2 are both connected to the current input end of the current source I1, and the source of the second PMOS transistor P2 is connected to the power supply end VCC. The grid electrode of the second NMOS tube N2 is connected with the control end of the PFM control module, the source electrode of the second NMOS tube N2 is connected with the input end of the PFM control module, and the drain electrode of the second NMOS tube N2 is connected with the output end of the PFM control module. The grid electrode of the third NMOS tube N3 is connected with the grid electrode of the second NMOS tube N2, the source electrode of the third NMOS tube N3 is connected with the drain electrode of the third PMOS tube P3, and the drain electrode of the third NMOS tube N3 is connected with the output end of the PFM control module. The gate of the third PMOS transistor P3 is connected to the current input end of the current source I1, and the source of the third PMOS transistor P3 is connected to the power supply end VCC. The current output end of the current source I1 is connected with the ground end GND. The gate of the third PMOS transistor P3 is connected to the gate of the second PMOS transistor P2, and the source of the third PMOS transistor P3 is connected to the source of the second PMOS transistor P2, where the third PMOS transistor P3 and the second PMOS transistor P2 form a current mirror structure.
The control end of the oscillation module is connected with the output end of the PWM control module and the output end of the PFM module at the same time, and the output end of the oscillation module is connected with the output end Vout of the dual-mode control circuit.
Specifically, the first resistor R1, the second resistor R2, and the third resistor R3 are sequentially connected in series between the ground terminal GND and the power supply terminal VCC. The input end of the first transmission gate T1 is connected between the second resistor R2 and the third resistor R3, the output end of the first transmission gate T1 is connected with the in-phase end of the second comparator COM2, the input end of the second transmission gate T2 is connected between the first resistor R1 and the second resistor R2, the output end of the second transmission gate T2 is connected with the inverting end of the second comparator COM2, the positive control end of the first transmission gate T1 and the negative control end of the second transmission gate T2 are both connected with the output end of the second comparator COM2, and the inverse control end of the first transmission gate T1 and the inverse control end of the second transmission gate T2 are both connected with the output end of the second inverter INV 2. An output terminal of the second comparator COM2 is connected to an output terminal of the oscillation module and an input terminal of the second inverter INV 2. The output end of the second inverter INV2 is connected to the gate of the fourth NMOS transistor N4. One end of the capacitor C is connected with the control end of the oscillation module, and the other end of the capacitor C is connected with the ground end GND. The source electrode of the fourth NMOS tube N4 is connected with the control end of the oscillation module, and the drain electrode of the fourth NMOS tube is connected with the grounding end to form a discharging loop of the capacitor C controlled by the output voltage of the oscillation module.
Preferably, the oscillation module further includes an eighth NMOS transistor N8, a ninth NMOS transistor N9, and a tenth NMOS transistor N10. The source electrode and the grid electrode of the ninth NMOS tube N9 are connected to the current output end of the current source I1, and the drain electrode of the ninth NMOS tube N9 is connected with the source electrode of the tenth NMOS tube N10; the gate of the tenth NMOS transistor N10 is connected to the gate of the fourth NMOS transistor N4, and the drain of the tenth NMOS transistor N10 is connected to the ground GND; the current output end of the current source I1 is connected to the ground GND through the ninth NMOS transistor N9 and the tenth NMOS transistor N10.
Preferably, the dual-mode control circuit further comprises a square root module, wherein an input end of the square root module is connected with an input end Vin of the dual-mode control circuit, and an output end I2 of the square root module is connected with an input end of the PFM control module, that is, the input end of the PFM control module is connected with the input end Vin of the dual-mode control circuit through the square root module.
Specifically, referring to fig. 2, the square root module includes a first amplifier COM3, a second amplifier COM4, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh PMOS transistor P7, an eighth PMOS transistor P8, a fifth NMOS transistor N5, a sixth NMOS transistor N6, a seventh NMOS transistor N7, a fourth resistor R4, and a fifth resistor R5.
The non-inverting terminal of the first amplifier COM3 is connected to the input terminal of the square root module, the inverting terminal of the first amplifier COM3 is connected to the ground terminal GND through the fourth resistor R4, the output terminal of the first amplifier COM3 is connected to the gate of the fifth NMOS transistor N5, the source of the fifth NMOS transistor N5 is connected to the drain of the fourth PMOS transistor P4, and the drain of the fifth NMOS transistor N5 is connected to the ground terminal GND through the fourth resistor R4. The source electrode of the fourth PMOS transistor P4 is connected to the power supply terminal VCC, and the gate electrode of the fourth PMOS transistor P4 is connected to the drain electrode of the fourth PMOS transistor P4 and the gate electrode of the fifth PMOS transistor P5. The source electrode of the fifth PMOS transistor P5 is connected to the power supply terminal VCC, and the drain electrode of the fifth PMOS transistor P5 is connected to the source electrode of the sixth NMOS transistor N6 and the gate electrode of the sixth NMOS transistor N6. The gate of the sixth NMOS transistor N6 is connected to the non-inverting terminal of the second amplifier COM4, and the drain of the sixth NMOS transistor N6 is connected to the source of the seventh NMOS transistor N7. The gate of the seventh NMOS transistor N7 is connected to the inverting terminal of the second amplifier COM4 and the output terminal of the second amplifier COM4, and the drain of the seventh NMOS transistor N7 is connected to the ground GND. The drain electrode and the gate electrode of the sixth PMOS transistor P6 are both connected to the output end of the second amplifier COM4, and the source electrode of the sixth PMOS transistor P6 is connected to the power supply end. The drain electrode of the sixth PMOS transistor P6 is further connected to the source electrode of the seventh PMOS transistor P7, and both the gate electrode and the drain electrode of the seventh PMOS transistor P7 are connected to the ground GND through the fifth resistor R5. The gate of the eighth PMOS transistor P8 is connected to the gate of the sixth PMOS transistor P6, the source of the eighth PMOS transistor P8 is connected to the power supply terminal VCC, and the drain of the eighth PMOS transistor P8 is connected to the output terminal I2 of the square root module.
And the fifth PMOS transistor P5 and the fourth PMOS transistor P4 form a current mirror structure, and the sixth PMOS transistor P6 and the eighth PMOS transistor P8 form a current mirror structure.
The input voltage Vin of the dual-mode control circuit is input from the input end of the square root module, the negative feedback circuit composed of the first amplifier COM3, the fifth NMOS transistor N5 and the fourth resistor R4 makes the voltage value of the in-phase end and the opposite-phase end of the first amplifier COM3 equal, preferably, when the width-to-length ratio of the fourth PMOS transistor P4 and the fifth PMOS transistor P5 is identical, the current flowing through the fifth PMOS transistor P5 is equal to the current flowing through the fourth PMOS transistor P4, and the current value I3 flowing through the fifth PMOS transistor P5 is set to have:
because the second amplifier COM4, the fifth PMOS transistor P5, the seventh PMOS transistor P7, the sixth NMOS transistor N6, the seventh NMOS transistor N7, and the fifth resistor R5 form a unit gain negative feedback loop, a gate voltage value of the seventh NMOS transistor N7 is equal to a source voltage value of the seventh PMOS transistor P7, so that the seventh NMOS transistor N7 works in a saturation region, the seventh PMOS transistor P7 works in a subthreshold region, a threshold voltage value of the seventh NMOS transistor N7 is approximately equal to a gate-source voltage value of the seventh PMOS transistor P7, and the threshold voltage value is set to be V0, so that a threshold voltage of the seventh NMOS transistor N7 is equal to a threshold voltage value of the seventh PMOS transistor P7. Namely:
V THN7 ＝V THP7 ≈V GSP7
for the seventh PMOS transistor, there is:
Vb＝Va-V GSP7 ＝Va-V THP7
where Va is the voltage value at a in fig. 2 and Vb is the voltage value at b in fig. 2.
According to the saturated current calculation formula of the MOS tube, the drain current of the seventh NMOS tube N7 is:
let the width-to-length ratio of the sixth PMOS transistor P6 to the seventh PMOS transistor P7 be 1: m, the current flowing through the seventh PMOS transistor P7 is:
from the above formula, it can be obtained:
since the resistance of the fourth resistor R4 is determined by the resistance of the fifth resistor R5, the output current value of the output terminal I2 is in a linear relationship with the square of the voltage value input by the input terminal Vin. Setting:
the method comprises the following steps:
under the condition that the output current value of the output end I2 and the voltage value of the input end Vin form a linear relation, the problem that the switching frequency adjustment amplitude of a system applied by the dual-mode control circuit is too large when a large-range load is switched is avoided, so that the system is not easy to control, and the controllability of the system is improved.
The operation of a PWM/PFM dual-mode control circuit according to the present invention will be described in detail with reference to fig. 1 and 2.
First, a load voltage is input to the dual mode control circuit through the input terminal Vin. The mode selection module compares the voltage value input by the input end Vin with the voltage value of the reference voltage Vr, when the voltage value input by the input end Vin is smaller than the voltage value of the reference voltage Vr, the dual-mode control circuit outputs a high level, and in the circuit of the embodiment, the PFM control module is controlled to start, so that the dual-mode control circuit enters the PFM mode to work; when the voltage value input by the input end Vin is greater than the voltage value of the reference voltage Vr, the dual-mode control circuit outputs a low level, and in the circuit of the embodiment, the PWM control module is controlled to start, so that the dual-mode control circuit enters a PWM mode to work.
When the oscillating circuit outputs a low level, the grid electrode of the second NMOS tube N2 and the grid electrode of the third NMOS tube N3 are both low level, the second NMOS tube N2 and the third NMOS tube N3 are both cut off, and the PFM control module is closed. Because the first PMOS transistor P1 and the second PMOS transistor P2 form a current mirror structure, the first PMOS transistor P1 is turned on, and the second NMOS transistor N2 is turned on, so that the channel current of the first PMOS transistor P1 and the current of the current source I1 are in a linear relationship. The PWM control module is started and outputs the PWM control module to the oscillating circuit, and the capacitor C starts to charge. The current of the output end of the PWM control module is as follows:
I PWM ＝k 1 I1
wherein k is 1 The mirror current ratio of the first PMOS tube P1 to the second PMOS tube P2.
When the voltage difference between the two ends of the capacitor C exceeds the voltage value of the same phase end of the second comparator COM2, the output end of the second comparator COM2 outputs a low level, that is, the dual-mode control circuit outputs a low level, the discharging loop is turned on, and the capacitor C starts to discharge; and until the voltage difference between the two ends of the capacitor C is smaller than the voltage value of the same phase end of the second comparator COM2, the output end of the second comparator COM2 outputs a high level, namely the dual-mode control circuit outputs a high level, the discharging loop is cut off, and the capacitor C is continuously charged. Therefore, there are upper and lower limits V1 and V2 of the capacitor C voltage:
thus, in PWM mode, the dual mode control circuit output pulse period is:
and obtaining output pulses with constant periods, namely outputting PWM waveform pulses by the dual-mode control circuit in a PWM mode.
When the oscillating circuit outputs a high level, the first NMOS tube N1 is turned off, and the PWM control module is turned off. The second NMOS tube N2 and the third NMOS tube N3 are both conducted, and the PFM control module is started. And the output end I2 of the square root module outputs current through the second NMOS tube N2 and is output from the output end of the PFM control module. Because the third PMOS transistor P3 and the second PMOS transistor P2 form a current mirror structure, the third PMOS transistor P3 is turned on, and the third NMOS transistor N3 is turned on, so that the drain current of the third PMOS transistor P3 is:
I4＝k 2 I1
wherein k is 2 The mirror current ratio of the third PMOS tube P3 to the second PMOS tube P2
At this time, the charging current of the capacitor C is the sum of the current source I1 and the current of the output end I2 of the square root module, when the voltage difference between the two ends of the capacitor C exceeds the in-phase end voltage value of the second comparator COM2, the output end of the second comparator COM2 outputs a low level, that is, the dual-mode control circuit outputs a low level, the discharging loop is turned on, and the capacitor C begins to discharge; and until the voltage difference between the two ends of the capacitor C is smaller than the voltage value of the same phase end of the second comparator COM2, the output end of the second comparator COM2 outputs a high level, namely the dual-mode control circuit outputs a high level, the discharging loop is cut off, and the capacitor C is continuously charged.
Thus, in PFM mode, the dual mode control circuit output pulse period is:
and obtaining an output pulse with the output frequency changing along with the voltage value of the input end Vin, and outputting PFM waveform pulses by the dual-mode control circuit in the PFM mode.
According to the PWM/PFM dual-mode control circuit provided by the embodiment of the invention, the PWM control module is started under the heavy load condition according to the voltage value of the input end of the dual-mode control circuit through the mode selection module, the PFM control module is started under the light load condition, the PWM control module or the PFM control module generates a corresponding control signal to control the oscillation mode of the oscillation circuit, and the corresponding PWM waveform voltage or PFM waveform voltage is obtained at the output end of the dual-mode control circuit. Because the PWM mode generating circuit formed by the PWM control module and the oscillation module and the PFM mode generating circuit formed by the PFM control module and the oscillation module are integrated in one oscillator control unit, and the mode selection module pair selects the working mode, the functional module of the circuit is reduced, the static power consumption of the circuit is reduced, the PFM mode is adopted to work under the light load condition, and the switching frequency range of the load current change system is more compact, so that the circuit is more stable under transient switching and steady-state interference, and the working efficiency under the full load current is improved.
While the foregoing is directed to the preferred embodiments of the present invention, it will be appreciated by those skilled in the art that changes and modifications may be made without departing from the principles of the invention, such changes and modifications are also intended to be within the scope of the invention.
Claims (6)
1. The PWM/PFM dual-mode control circuit is characterized by comprising a mode selection module, a PWM control module, a PFM control module and an oscillation module;
the input end of the mode selection module is connected with the input end of the dual-mode control circuit, and the output end of the mode selection module is simultaneously connected with the control end of the PWM control module and the control end of the PFM control module;
the PWM control module comprises a first inverter, a first NMOS tube, a first PMOS tube, a second PMOS tube and a current source; the input end of the first inverter is connected with the control end of the PWM control module, and the output end of the first inverter is connected with the grid electrode of the first NMOS tube; the source electrode of the first NMOS tube is connected with the drain electrode of the first PMOS tube, and the drain electrode of the first NMOS tube is connected with the output end of the PWM control module; the grid electrode of the first PMOS tube is connected with the current input end of the current source, and the source electrode of the first PMOS tube is connected with the power supply end; the grid electrode of the second PMOS tube and the drain electrode of the second PMOS tube are both connected with the current input end of the current source, and the source electrode of the second PMOS tube is connected with the power supply end;
the PFM control module comprises a second PMOS tube, a second NMOS tube, a third PMOS tube and a current source; the grid electrode of the second NMOS tube is connected with the control end of the PFM control module, the source electrode of the second NMOS tube is connected with the input end of the PFM control module, and the drain electrode of the second NMOS tube is connected with the output end of the PFM control module; the grid electrode of the third NMOS tube is connected with the grid electrode of the second NMOS tube, the source electrode of the third NMOS tube is connected with the drain electrode of the third PMOS tube, and the drain electrode of the third NMOS tube is connected with the output end of the PFM control module; the grid electrode of the third PMOS tube is connected with the current input end of the current source, and the source electrode of the third PMOS tube is connected with the power supply end;
the oscillation module comprises a first resistor, a second resistor, a third resistor, a first transmission gate, a second comparator, a second inverter, a fourth NMOS tube, a capacitor, an eighth NMOS tube, a ninth NMOS tube and a tenth NMOS tube; the first resistor, the second resistor and the third resistor are sequentially connected in series between a grounding end and a power supply end; the input end of the first transmission gate is connected between the second resistor and the third resistor, the output end of the first transmission gate is connected with the same-phase end of the second comparator, the input end of the second transmission gate is connected between the first resistor and the second resistor, the output end of the second transmission gate is connected with the opposite-phase end of the second comparator, the positive control end of the first transmission gate and the negative control end of the second transmission gate are both connected with the output end of the second comparator, and the negative control end of the first transmission gate and the positive control end of the second transmission gate are both connected with the output end of the second inverter; the output end of the second comparator is connected to the output end of the oscillation module and the input end of the second inverter; the output end of the second inverter is connected to the grid electrode of the fourth NMOS tube; the drain electrode of the fourth NMOS tube is connected with the grounding end; one end of the capacitor is connected with the control end of the oscillation module, and the other end of the capacitor is connected with the grounding end; the grid electrode of the eighth NMOS tube is connected to the current output end of the current source, the source electrode of the eighth NMOS tube is connected to the control end of the oscillation module, and the drain electrode of the eighth NMOS tube is connected with the source electrode of the fourth NMOS tube; the source electrode of the fourth NMOS tube is connected with the control end of the oscillation module through the eighth NMOS tube; the source electrode of the ninth NMOS tube and the grid electrode of the ninth NMOS tube are connected to the current output end of the current source, and the drain electrode of the ninth NMOS tube is connected with the source electrode of the tenth NMOS tube; the grid electrode of the tenth NMOS tube is connected with the grid electrode of the fourth NMOS tube, and the drain electrode of the tenth NMOS tube is connected with the grounding end; the current output end of the current source is connected with the grounding end through the ninth NMOS tube and the tenth NMOS tube in sequence;
the output end of the PWM control module is connected with the control end of the oscillation module;
the input end of the PFM control module is connected with the input end of the dual-mode control circuit, and the output end of the PFM control module is connected with the control end of the oscillation module;
and the output end of the oscillation module is connected with the output end of the dual-mode control circuit and is used for generating and outputting an oscillation voltage.
2. The dual mode control circuit of claim 1, further comprising a square root module, an input of the PFM control module being connected to an input of the dual mode control circuit through the square root module;
the input end of the square root module is connected with the input end of the dual-mode control circuit, and the output end of the square root module is connected with the input end of the PFM control module and is used for outputting square root current which is in linear relation with the square root of the voltage of the input end of the dual-mode control circuit.
3. The dual mode control circuit of claim 1, wherein the mode selection module comprises a first comparator having an in-phase terminal for coupling to a reference voltage, an inverting terminal coupled to the input terminal of the mode selection module, and an output terminal coupled to the output terminal of the mode selection module.
4. The dual mode control circuit of claim 2, wherein the square root module comprises a first amplifier, a second amplifier, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a fourth resistor, and a fifth resistor;
the non-inverting terminal of the first amplifier is connected with the input terminal of the square root module, the inverting terminal of the first amplifier is connected with the grounding terminal through the fourth resistor, the output terminal of the first amplifier is connected with the grid electrode of the fifth NMOS tube, the source electrode of the fifth NMOS tube is connected with the drain electrode of the fourth PMOS tube, and the drain electrode of the fifth NMOS tube is connected with the grounding terminal through the fourth resistor;
the source electrode of the fourth PMOS tube is connected with the power supply end, and the grid electrode of the fourth PMOS tube is connected with the drain electrode of the fourth PMOS tube and the grid electrode of the fifth PMOS tube; the source electrode of the fifth PMOS tube is connected with the power supply end, and the drain electrode of the fifth PMOS tube is connected with the source electrode of the sixth NMOS tube and the grid electrode of the sixth NMOS tube; the grid electrode of the sixth NMOS tube is connected with the same-phase end of the second amplifier, and the drain electrode of the sixth NMOS tube is connected with the source electrode of the seventh NMOS tube; the grid electrode of the seventh NMOS tube is connected with the inverting terminal of the second amplifier and the output terminal of the second amplifier, and the drain electrode of the seventh NMOS tube is connected with the grounding terminal;
the drain electrode of the sixth PMOS tube and the grid electrode of the sixth PMOS tube are both connected to the output end of the second amplifier, and the source electrode of the sixth PMOS tube is connected with the power supply end; the drain electrode of the sixth PMOS tube is also connected to the source electrode of the seventh PMOS tube, and the grid electrode and the drain electrode of the seventh PMOS tube are both connected with the grounding end through the fifth resistor; the grid electrode of the eighth PMOS tube is connected with the grid electrode of the sixth PMOS tube, the source electrode of the eighth PMOS tube is connected with the power supply end, and the drain electrode of the eighth PMOS tube is connected with the output end of the square root module.
5. A dual mode control circuit as claimed in claim 3, wherein the first comparator is a hysteresis comparator.
6. The dual-mode control circuit of claim 4, wherein the fourth PMOS transistor and the fifth PMOS transistor have a uniform aspect ratio.
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| CN111416505B (en) * | 2020-04-14 | 2021-05-11 | 上海顺久电子科技有限公司 | Switching power supply converter |
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