KR101039906B1 - Adaptive on-time controller and pulse frequency modulation buck converter using the same - Google Patents

Abstract

An adaptive on time controller for a PFM buck converter is disclosed. An adaptive on time controller for adjusting the on time of a PFM buck converter connected to an external LC output stage, wherein the difference between the output voltage and the supply voltage fed back from the external LC output stage decreases the on time, and reduces the external LC output stage. When the difference between the output voltage and the supply voltage fed back is small, the adaptive on time controller characterized in that the control to increase the on time. According to the adaptive on-time controller and the PFM buck converter using the same, the on-time of the PFM buck converter is controlled to have a high output efficiency and a small output voltage ripple at various output voltages as well as a fixed output voltage. have.

Adaptive, On Time, PFM, Buck Converter, Controller

Description

ADAPTIVE ON-TIME CONTROLLER AND PULSE FREQUENCY MODULATION BUCK CONVERTER USING THE SAME}

The present invention relates to an on time controller and a PFM buck converter using the same, and more particularly, to an adaptive on time controller and a PFM buck converter using the same.

A portable terminal such as a mobile communication terminal or a personal digital assistant (PDA) keeps most of its time in an idle state. Since power consumption continues in the standby state, reducing power loss in the standby state is a key factor.

Most of the power lost in the standby state is a switching loss for driving the power transistor of the switch converter, which is very large when using a pulse width modulation buck converter. Accordingly, in order to prevent such a loss, a PFM buck converter (pulse frequency modulation buck converter) is mainly used instead of the conventional PWM buck converter.

These PFM buck converters can be divided into two structures. First, the PFM method for detecting inductor current and the PFM method for supplying power to the system for a fixed time without detecting the inductor current can be divided. PFMs that sense inductor current require complex inductor current sense circuits and high performance comparators. On the other hand, the PFM method that supplies power to the system for a fixed time does not require a complex inductor current sensing circuit, but the inductor current value changes according to the supply voltage and the output voltage to supply the system with uneven power. Voltage ripple also changes significantly, which degrades overall system performance. In order to solve this problem, a method of improving performance by supplying a constant inductor current through adaptive on-time adjustment even though supply voltage and output voltage change is being studied.

One example is the paper An Accurate, Low-Voltage, CMOS Switching Power Supply With Adaptive On-Time Pulse-Frequency Modulation (PFM) Control (Biranchinath Sahu and Gabriel A. Rincon-Mora, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPAERS, VOL. 54, NO.2, February 2007). However, in the scheme proposed in the above paper, the on time is controlled only for the change of supply voltage.

FIG. 1A is a circuit diagram showing a schematic configuration of a PFM buck converter according to the prior art, and FIG. 1B is a timing diagram of the PFM buck converter.

Referring to FIG. 1, power is supplied through the supply voltage V _IN during an on time when the transistor MP1 is turned on, and the inductor current increases with a constant slope. When transistor MP1 is turned off and transistor MN1 is turned on, power is supplied through ground VSS. At this time, the inductor current decreases with a constant slope. This action charges the capacitor with energy and maintains a constant voltage through a feedback loop. On the other hand, it can be seen that the on-time T _PMOS of the PMOS transistor MP1 of FIG. 1 mentioned above may be expressed as Equation 1 from the current and voltage formula of the inductor.

Where I _{L_PEAK} is the peak current value of the inductor L, V _IN is the supply voltage, and V _OUT is the output voltage.

And I _{L_PEAK} can be expressed as Equation 2 below.

Where C is the capacitance and ΔV is the output ripple voltage.

As discussed earlier, the fixed on-time PFM controller generates a variety of inductor currents over a wide range of input voltages, which in turn produces a variety of output ripple voltages.

Thus, to make a small ripple voltage, the on-time of the PFM buck converter needs to be adaptively changed. This on time may be expressed as Equation 3 below.

Next, FIG. 2A is a circuit diagram showing a schematic configuration of an adaptive on time PFM controller according to the prior art, and FIG. 2B is a timing diagram of the adaptive on time PFM controller.

Referring to Figure 2, I _VAR supply voltage V _IN and the output voltage V and _OUT dependent on, V _CONST (in the example V _CONST is the gate-source voltage), a voltage charged in the capacitor C by the current source I _VAR. Therefore, the consumption time T _CHARGE for the V _CONST to turn on the NMOS transistor is proportional to I _VAR only, which means that T _CHARGE, that is, T _ON can vary only by the output voltage V _OUT and the supply voltage V _IN . The on time of the PFM buck converter is expressed by Equation 4 below.

Here, the resistor R is used to determine the magnitude of the current.

As such, to maintain a constant peak current in inductor L, the on-time of the PFM buck converter must match the charge time of capacitor C, regardless of the supply voltage. Therefore, the ON time T _ON of the PFM buck converter may be expressed as Equation 5 below.

As can be seen from Equation 5, it can be seen that the on time of the PFM buck converter is determined by the difference between V _CONST , resistance R, capacitance C, supply voltage V _IN, and output voltage V _OUT . However, in the conventional adaptive on time PFM buck converter, the output voltage is fixed, which makes it less useful in portable terminals requiring various output voltages.If the supply voltage is changed, the ripple of the output voltage is changed to affect the overall system performance. do. In addition, since the output voltage is assumed to be similar to the threshold voltage of the transistor, there is a problem in that the accurate on-time cannot be adjusted when the threshold voltage of the transistor varies with process and temperature.

An object of the present invention is to provide an adaptive on time controller.

Another object of the present invention is to provide a PFM buck converter using an adaptive on time controller.

An adaptive on time controller for achieving the above object of the present invention is an adaptive on time controller for adjusting an on time of a PFM buck converter connected to an external LC output stage, the output voltage fed back from the external LC output stage. The on time may be reduced when the supply voltage increases, and the on time may be increased when the difference between the output voltage fed back from the external LC output terminal and the supply voltage becomes small.

The adaptive on time controller may include an adaptive current generator configured to generate a current I_adp proportional to a difference between an output voltage fed back from the external LC output terminal and the supply power, and a current I_adp generated by the adaptive current generator. It may be configured to include a current mirror for mirror copying and a comparison output unit for outputting the adaptive voltage V _ramp generated by the current mirrored in the current mirror unit compared with the reference voltage V _ref1 .

On the other hand, one aspect of the present invention for achieving the other object, in the PFM buck converter connected to the external LC output terminal, the reference voltage generating unit for generating a reference voltage, the reference voltage generated by the reference voltage generator and the A comparison unit comparing the output voltage fed back from the external LC output stage and outputting a result value, an adaptive on time controller for adjusting an on time according to a difference between the output voltage fed back from the external LC output stage and the supply voltage, and the comparing unit The SR latch unit may receive a result value output from the result value and the result value output from the adaptive on time controller, and an ON time TR unit performing a converting operation according to the output value of the SR latch unit.

The adaptive on time controller may reduce the on time when the difference between the output voltage fed back from the external LC output terminal and the supply voltage increases, and when the difference between the output voltage fed back from the external LC output terminal and the supply voltage decreases, Control to increase the on time.

In this case, the adaptive on time controller mirrors an adaptive current generator for generating a current I_adp proportional to a difference between the output voltage fed back from the external LC output terminal and the supply power, and the current I_adp generated by the adaptive current generator. And a comparison output unit for outputting the current mirror unit for copying and comparing the adaptive voltage V _ramp generated by the current mirrored by the current mirror unit with the reference voltage V _ref1 generated in the reference voltage generator. have.

The reference voltage generator may be configured to adjust the on time by adjusting the magnitude of the reference voltage V _ref1 .

In this case, the reference voltage generator may be configured to generate the reference voltage by changing the reference voltage according to the resistor R_off of the off-chip configuration.

Meanwhile, referring to FIG. 3, when the output voltage V _buck of the external LC output terminal is smaller than the reference voltage V _ref _adp, the output transistor QP1 of the on-time TR unit is turned on and the output voltage V _buck of the external LC output terminal is turned on. When the reference voltage V _ref _adp is greater than the reference voltage V _ref _adp, the output transistor QP1 of the on-time TR unit may be turned off.

According to the adaptive on-time controller and the PFM buck converter using the same, the on-time of the PFM buck converter is controlled to have a high output efficiency and a small output voltage ripple at various output voltages as well as a fixed output voltage. have.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. Like reference numerals are used for like elements in describing each drawing.

The terms first, second, A, B, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component. And / or < / RTI > includes any combination of a plurality of related listed items or any of a plurality of related listed items.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram showing a schematic configuration of a PFM buck converter according to an embodiment of the present invention.

First, a schematic configuration of the present invention will be described with reference to FIG. 3.

As shown in FIG. 3, the PFM buck converter 100 of the present invention is a main component and includes a reference voltage generator 110, a comparator 120, an adaptive on-time controller 130, and an SR latch unit 140. ), It may be configured to include an on-time TR unit 150.

The off-chip component 200 of the PFM buck converter 100 may include an external LC output terminal connected to the output terminal of the on-time TR unit 150 and a resistor R_off connected to the reference voltage generator 110. . In addition, the output voltage V _buck of the PFM buck converter 100 is output through an external LC output terminal.

First, the reference voltage generator 110 is a component for generating a reference voltage. The reference voltage generator 110 generates an adaptive reference voltage V _ref _adp and inputs it to the comparator 121, and generates a reference voltage V _ref1 and inputs it to the adaptive on time controller 130.

In most cases, the resistors for sensing the output voltage are adjusted to adjust the output voltage. However, in the present invention, the output voltage is controlled by changing the reference voltage using one R_off resistor. As a result, the number of external components can be reduced, which is suitable for portable devices requiring light and small size.

The reference voltage generator 110 is configured to be connected to the resistor R_off of the off chip component 200, and the user may generate a desired reference voltage by changing only the resistor R_off.

The comparator 120 compares the reference voltage generated by the reference voltage generator 110 with another target voltage and outputs a result value. The comparator 120 may include a first comparator 121 and a second comparator 122.

First, the first comparator 121 compares the adaptive reference voltage V _ref _adp generated by the reference voltage generator 110 with the output voltage V _buck fed back from the external LC output terminal and outputs a result value.

Next, the second comparator 122 compares and outputs the ground voltage and the output voltage SW of the on-time TR unit 150. This is a configuration for preventing generation of reverse current, which will be described later.

The adaptive on time controller 130 is configured to adjust the on time in consideration of the difference between the output voltage V _buck and the supply voltage VDD. Here, the on time is configured to be inversely proportional to the difference between the output voltage V _buck and the supply voltage VDD. By the on time adjustment, the amount of the inductor current i _L flowing through the external LC output terminal can be kept constant, which is the most characteristic feature of the present invention.

Next, the SR latch unit 140 receives the result value output from the comparator 120 and the result value output from the adaptive on time controller 130 and transmits the result value to the on time TR unit 150. The SR latch unit 140 causes the transistor of the on time TR unit 150 to operate on time according to the on time adjusted by the adaptive on time controller 130. The SR latch unit 140 may be configured as a NOR gate.

Lastly, the ON time TR unit 150 is configured to perform the conversion by turning the transistor on or off according to the output value of the SR latch unit 140. At this time, the output value of the SR latch unit 140 is output according to the on time adjusted by the adaptive on time controller 130, of course.

Hereinafter, the operation of the PFM buck converter 100 will be described in more detail with reference to FIGS. 3 to 6.

First, it is assumed in FIG. 3 that the output voltage V _buck is lower than the adaptive reference voltage V _ref _adp at the start of the operation of the present invention. When the output voltage V _buck is input to the first comparator 121, the first comparator 121 compares the adaptive reference voltage V _ref _adp and the output voltage V _buck already generated by the reference voltage generator 110 to obtain a result value. Output

6, as described above, the reference voltage generator 110 may generate the adaptive reference voltage V _ref _adp using the resistor R_off of the off-chip component 200.

In operation description of the first comparator 121, when the output voltage V _buck of the external LC output terminal is lower than the adaptive reference voltage V _ref _adp at the start of operation, the output value of the first comparator 121 becomes 'high'. . The 'high' output value drives the SR_latch 141, and when the 'high' signal is input to the S terminal, the output value of Qb becomes 'low'. The low output value turns on the transistor QP1 via the PMOS driver 151 of the on-time TR unit 150. The transistor QP1 is connected to the supply voltage VDD so that the output value of the SW terminal rises to VDD. At this point, the on time starts.

Here, the capacitor C is charged while the current continues to flow through the inductor L existing between the SW terminal and the external LC output terminal V _buck . After a certain time, the output voltage of the output terminal CNT of the adaptive on time controller 130 becomes 'high', and this signal passes the PMOS driver 151 by making Qb of the SR_latch 141 high. Turn off transistor QP1.

Next, when the changed output voltage V _buck is larger input of a first comparator 121 than the adaptive reference voltage V _ref _adp, having a level exceeding the adaptive reference voltage V _ref _adp, the first comparator 121 is as before On the contrary, 'low' value is printed.

On the other hand, the output voltage V _buck is input to the adaptive on time controller 130, the adaptive on time controller 130 adjusts the on time in consideration of the difference between the input V _buck and the supply voltage VDD, and then the corresponding result value Output to CNT terminal.

The adaptive on time controller 130 will now be described with reference to FIGS. 4 and 5.

The adaptive on time controller 130 may include an adaptive current generator 131, a current mirror 132, and a comparison output unit 133.

The adaptive current generator 131 may include an operational amplifier, a resistor R1, a capacitor C2, a transistor MN1, and the like.

The output voltage V _buck is input through the inverting terminal of the operational amplifier. Due to the virtual short circuit between the input terminals due to the characteristics of the operational amplifier, the output voltage V _buck can be expressed as Equation 6 below.

In addition, I_adp is expressed as in Equation 7 below.

The signal amplified by the operational amplifier is used as the gate voltage for operating the transistors MN1 and MN2 in the saturation region. In particular, I_adp is copied to the current mirror 132 through transistors MN1 and MN2. Therefore, MP1 and MP2 constituting the current mirror generate a current of I_adp. The current I_adp supplied through transistor MP2 is supplied to capacitor C1 or transistor MN3. If the 'high' signal is input to PDRIVE, transistor MN3 is turned on and current I_adp flows through transistor MN3 to ground.

On the other hand, when the low-level PDRIVE is supplied, the transistor MN3 is turned off, the current I_adp flows into the capacitor C1, and the voltage V _ramp of the capacitor C1 rises.

On the other hand, the current I_adp is supplied to the capacitor C1 for a predetermined time T _ON , and forms a voltage increase V _ramp (t) according to Equation 8 below.

The formation of this voltage rise V _ramp (t) begins when transistor QP1 is turned on when the signal from PDRIVE is 'low'. In addition, in FIG. 4 and Equation 8, if the voltage level of the capacitor C1 is assumed to be 0 V before the time of T _ON , the voltage increase is V _ramp (T _ON ). Hereinafter, the description will be made on the assumption that the voltage V _ramp (T _ON ) is a voltage increase for convenience of description.

As in FIG. 4, PDRIVE turns off transistor MN3, whereby voltage V _ramp (T _ON ) begins to form in capacitor C1. This shows that the voltage V _ramp (T _ON ) is formed in the timing diagram of FIG. 5.

This _ramp voltage V (T _ON) is compared to the reference voltage V _ref1 grows more compared to the comparative reference voltage V _ref1 from the comparison output unit 133, the on-time is ended. More specifically, as the magnitude of the voltage V _ramp (T _ON ) becomes larger than the reference voltage V _ref1 , the voltage at the CNT terminal becomes 'high', and the Qb of the SR_latch_P 141 also has a 'high' signal. And input to the PMOS driver 151. The PMOS driver 151 converts the received signal level into a voltage suitable for subsequent operation of the driving transistor. The high level signal input to the PMOS driver 151 eventually turns off the transistor QP1.

At the same time, the output signal CNT of the adaptive on-time controller changes the Q signal to a 'high' signal through the SR_latch 142 and turns on the transistor QN1 through the NMOS driver.

Here, the on time T _ON using Equations 7 and 8 described above may be expressed as Equation 9 below.

Here, it can be seen that the _ON time T _ON depends on the VDD-V _{buck which} is the difference between the supply voltage and the output voltage.

Here, the meaning of the circuit operation of FIG. 4 will be described in more detail as follows.

When V _buck decreases rapidly in Equation 7, the current I_adp rises steeply. Accordingly, the voltage V _ramp (t) also quickly rises in Equation 8, which means that the time taken until the voltage V _ramp (t) exceeds the reference voltage V _ref1 is shortened. Herein, when the voltage V _ramp (t) exceeds the reference voltage V _ref1 , the 'high' signal is output from the terminal CNT, and thus the time means ON time T _ON . That is, as shown in Equation 9, when the output voltage V _buck decreases, the on time T _ON becomes short.

On the other hand, when looking at the current of the inductor L, it can be seen that it can be expressed by the following equation (10) according to the voltage and current relationship of the inductor.

Referring to Equation 10, the inductor current Δi _L varies in size depending on VDD-V _buck , which is a difference between the supply voltage and the output voltage of the external LC output terminal.

Here, in order to maintain a constant peak of the inductor current Δi _L regardless of the supply voltage VDD or the output voltage V _buck of the external LC output terminal and to deliver power to the load stably, the ON time T _ON according to the VDD-V _buck is used. Should be changed.

That is, when the adaptive on-time controller 130 is the VDD-V _buck is increased reducing the on-time T _ON and the VDD-V _buck is reduced, thereby increasing the on-time T _ON. As a result, the peak of the inductor current Δi _L is kept constant.

In the present invention, as a method of changing the on time T _ON by the adaptive on time controller 130, the reference voltage generator 110 may adjust the comparison reference voltage V _ref1 to eventually change the on time T _ON .

In practice, the desired on time T _ON can be obtained by adjusting the resistor R1 and the capacitor C1 of the adaptive on time controller 130 and the comparison reference voltage V _ref1 generated by the reference voltage generator 110. This means that the present invention can maintain a constant power at the output terminal even if the output voltage V _buck is changed as well as the supply voltage VDD.

On the other hand, when the transistor QN1 is turned on for a long time at the SW terminal mentioned above, reverse current is generated. This reverse current occurs when the voltage at the SW terminal is higher than VSS (0 V).

Thus, in order to prevent the occurrence of such reverse current, a second comparator 122 is additionally provided for detecting a possibility of generating reverse current. Accordingly, in the second comparator 122, when the voltage of the SW terminal becomes the 'high' signal, the output of the second comparator 122 becomes 'high', and then the Q of the SR_latch 142 is 'low'. To be a signal.

As a result, the transistor QN1 is turned off via the NMOS driver 152. When transistor QN1 is turned off, the SW terminal is floating and the voltage at the SW terminal is LC oscillated and no reverse current occurs.

Hereinafter, a simulation result of the adaptive on time PFM buck converter 100 of the present invention will be described with reference to FIGS. 7 to 8.

7 is a waveform diagram illustrating (a) an output voltage and (b) an inductor current corresponding to a supply voltage change in a PFM buck converter according to an embodiment of the present invention.

As shown in FIG. 7, it can be seen that the ripple voltage of the output voltage V _buck and the peak value of the inductor current are kept constant despite the change in the supply voltage VDD.

Next, FIG. 8 is a waveform diagram illustrating (a) and (b) output voltages and (c) inductor currents corresponding to changes in output voltage in a PFM buck converter according to an embodiment of the present invention.

Referring to FIG. 8, it can be seen that when the output voltage V _buck is changed, the peak value of the inductor current is kept constant and the magnitude of the ripple voltage of the output voltage V _buck is kept small.

FIG. 9A illustrates a ripple magnitude of an output voltage and an inductor corresponding to a supply voltage change in a PFM buck converter and a conventional fixed on-time PFM buck converter according to an embodiment of the present invention. Figures comparing the peak currents respectively.

9 shows that in the case of a fixed on-time PFM buck converter, the ripple or inductor current of the output voltage varies greatly depending on the supply voltage VDD. It is showing a slight change.

Next, FIG. 10 illustrates a ripple magnitude of an output voltage and (b) an inductor peak corresponding to an output voltage change in a PFM buck converter and a conventional fixed on-time PFM buck converter according to an embodiment of the present invention. A diagram comparing current values.

10, in the case of a fixed on-time PFM buck converter, the ripple or inductor current of the output voltage varies greatly according to the output voltage V _buck , but in the case of the proposed PFM buck converter, the ripple or inductor current of the output voltage is output. There is almost no change in voltage V _buck .

Although described with reference to the embodiments above, those skilled in the art will understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention as set forth in the claims below. Could be.

Figure 1 (a) is a circuit diagram showing a schematic configuration of a PFM buck converter according to the prior art, Figure 1 (b) is a timing diagram of a PFM buck converter according to the prior art.

Fig. 2A is a circuit diagram showing a schematic configuration of an adaptive on time PFM controller according to the prior art, and Fig. 2B is a timing diagram of an adaptive on time PFM controller according to the prior art.

3 is a block diagram showing a schematic configuration of a PFM buck converter according to an embodiment of the present invention.

4 is a circuit diagram of an adaptive on time controller according to an embodiment of the present invention.

5 is a timing diagram of an adaptive on time controller according to an exemplary embodiment of the present invention.

6 is a circuit diagram of a reference voltage generator according to an embodiment of the present invention.

7 is a waveform diagram illustrating (a) an output voltage and (b) an inductor current corresponding to a supply voltage change in a PFM buck converter according to an embodiment of the present invention.

8 is a waveform diagram illustrating (a) and (b) output voltages and (c) inductor currents corresponding to changes in output voltage in a PFM buck converter according to an embodiment of the present invention.

FIG. 9A illustrates a ripple magnitude of an output voltage and an inductor corresponding to a supply voltage change in a PFM buck converter and a conventional fixed on-time PFM buck converter according to an embodiment of the present invention. Figures comparing the peak currents respectively.

10 illustrates a ripple magnitude of an output voltage and (b) an inductor peak current value corresponding to an output voltage change in a PFM buck converter and a conventional fixed on-time PFM buck converter according to an embodiment of the present invention. It is a figure compared.

<Explanation of symbols for main parts of the drawings>

100: PFM buck converter 200: off chip component

110: reference voltage generator 120: comparison unit

121: first comparator 122: second comparator

130: adaptive on time controller 131: input unit

132: current mirror unit 133: output unit

140: SR latch portion 141: first latch

142: second latch 150: on time TR portion

151: PMOS driver 152: NMOS driver

Claims (8)

An adaptive on time controller for adjusting the on time of a PFM buck converter connected to an external LC output stage, An adaptive current generator for generating a current I_adp proportional to a difference between an output voltage fed back from the external LC output terminal and a supply voltage; A current mirror unit for mirror copying the current I_adp generated by the adaptive current generator; And a comparison output unit configured to compare the adaptive voltage V _ramp generated by the current mirrored by the current mirror unit with a comparison reference voltage V _ref1, and output the comparison voltage. When the difference between the output voltage fed back from the external LC output terminal and the supply voltage increases, the on time is reduced, And when the difference between the output voltage fed back from the external LC output terminal and the supply voltage decreases, the on time increases. delete In a PFM buck converter connected to an external LC output, A reference voltage generator configured to generate the reference voltage V _ref1 and the adaptive reference voltage V _ref _adp; A comparator for comparing the adaptive reference voltage V _ref _adp generated by the reference voltage generator with an output voltage fed back from the external LC output terminal and outputting a result value; An adaptive on time controller configured to adjust an on time according to a difference between the output voltage and a supply voltage fed back from the external LC output terminal; An SR latch unit configured to receive a result value output from the comparison unit and a result value output from the adaptive on time controller; And An on time TR unit configured to perform a converting operation according to an output value of the SR latch unit, The adaptive on time controller, An adaptive current generator for generating a current I_adp proportional to a difference between an output voltage fed back from the external LC output terminal and the supply voltage; A current mirror unit for mirror copying the current I_adp generated by the adaptive current generator; And And a comparison output unit configured to compare the adaptive voltage V _ramp generated by the current mirrored by the current mirror unit with the comparison reference voltage V _ref1 generated by the reference voltage generator. The method of claim 3, wherein the adaptive on time controller, When the difference between the output voltage fed back from the external LC output terminal and the supply voltage increases, the on time is reduced, And if the difference between the output voltage fed back from the external LC output stage and the supply voltage decreases, controlling the on-time to increase. delete The method of claim 3, wherein the reference voltage generator, The PFM buck converter, characterized in that for controlling the on time by adjusting the magnitude of the reference voltage _Vref1 . The method of claim 6, wherein the reference voltage generator, And the comparison reference voltage V _ref1 is generated according to the resistance R_off which is an off chip configuration. The method of claim 7, wherein the SR latch unit, When the adaptive voltage V _ramp is smaller than the comparison reference voltage V _ref1 generated by the reference voltage generator and the output voltage of the external LC output terminal is smaller than the adaptive reference voltage V _ref _adp, the output of the on-time TR part is output. Turn on transistor QP1, Turning off the output transistor QP1 of the on-time TR unit when the adaptive voltage V _ramp is greater than the reference voltage V _ref1 and the output voltage of the external LC output terminal is greater than the adaptive reference voltage V _ref _adp. PFM Buck Converter.

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