CN111416505B - Switching power supply converter - Google Patents

Switching power supply converter Download PDF

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Publication number
CN111416505B
CN111416505B CN202010289547.3A CN202010289547A CN111416505B CN 111416505 B CN111416505 B CN 111416505B CN 202010289547 A CN202010289547 A CN 202010289547A CN 111416505 B CN111416505 B CN 111416505B
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electrically connected
signal
inverter
input end
switching
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CN111416505A (en
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陈锡明
荣荧
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Shanghai Shunjiu Electronic Technology Co ltd
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Shanghai Shunjiu Electronic Technology Co ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/14—Arrangements for reducing ripples from dc input or output
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0009—Devices or circuits for detecting current in a converter

Abstract

The invention discloses a switching power supply converter, which is characterized in that a detection module is determined according to a grid opening signal of an input switching transistor when detecting whether a load is in a heavy load state at present, so that the current state of the load can be effectively detected in time even if the switching power supply converter is a low-power converter and works in a PFM working mode, and then the switching power supply converter is effectively switched to a corresponding working mode in time, thereby reducing output voltage ripples.

Description

Switching power supply converter
Technical Field
The invention relates to the technical field of power supplies, in particular to a switching power supply converter.
Background
For a switching power converter with a PWM (Pulse Width Modulation)/PFM (Pulse frequency Modulation) mixed Modulation mode, two working modes are included, namely a PWM mode and a PFM mode; when the load is in a heavy load state, the switching power supply converter works in a PWM mode, so that voltage ripples output by the switching power supply converter are small, and the efficiency is high; when the load is in a light load state, the switching power converter works in a PFM mode so as to reduce the power consumption of the switching power converter.
Therefore, a technical problem to be solved by those skilled in the art is how to detect whether a load is in a heavy load state so as to switch the operating mode of the switching power converter.
Disclosure of Invention
The embodiment of the invention provides a switching power converter which is used for detecting whether a load is in a heavy load state or not so as to switch the working mode of the switching power converter.
In a first aspect, an embodiment of the present invention provides a switching power converter, including: the device comprises a detection module, a switching module and a switch module;
the switch module comprises a switch transistor, the detection module is electrically connected with a grid electrode of the switch transistor, and the detection module is also electrically connected with the switching module;
the detection module is used for:
and when determining that the load is currently in a heavy-load state according to the gate opening signal input to the switching transistor, sending an enabling signal to the switching module so as to enable the switching module to be switched to a corresponding working mode.
Optionally, in an embodiment of the present invention, the detection module is specifically configured to:
and determining the enabling signal according to the pulse period of the grid opening signal and the pulse period of the clock signal.
Optionally, in an embodiment of the present invention, the switch module is electrically connected to the load;
when the load is in the heavy load state, the pulse period of the grid opening signal is smaller than a first preset value; or when the load is in a light load state, the pulse period of the grid opening signal is not less than the first preset value.
Optionally, in an embodiment of the present invention, the detection module includes: the frequency dividing unit, the logic control unit and the signal control unit;
the input end of the frequency dividing unit is electrically connected with the grid electrode of the switching transistor, and the output end of the frequency dividing unit is electrically connected with the first input end of the logic control unit, and is used for: performing frequency division processing on the grid opening signal to obtain a first pulse signal;
the second input end of the logic control unit is electrically connected with the clock signal end, and the output end of the logic control unit is electrically connected with the input end of the signal control unit and used for: performing logic processing on the first pulse signal and a clock signal provided by the clock signal end to obtain a second pulse signal;
the output end of the signal control unit is electrically connected with the switching module and is used for: determining the number of the corresponding clock signals in the pulse period of the first pulse signal according to the second pulse signal, and defining the number as a first number; and when the first quantity is judged to be larger than a second preset value, sending the enabling signal to the switching module.
Optionally, in an embodiment of the present invention, the frequency dividing unit includes a frequency dividing circuit.
Optionally, in an embodiment of the present invention, the switch transistor electrically connected to the detection module is an N-type transistor;
or, the switch transistor electrically connected with the detection module is a P-type transistor; the detection module further comprises: and the first inverter is arranged between the grid of the switching transistor and the frequency dividing unit.
Optionally, in an embodiment of the present invention, the logic control unit includes a nand gate logic circuit and a second inverter;
the first input end of the NAND gate logic circuit is electrically connected with the frequency dividing unit, the second input end of the NAND gate logic circuit is electrically connected with the clock signal end, and the output end of the NAND gate logic circuit is electrically connected with the input end of the second inverter;
and the output end of the second inverter is electrically connected with the signal control unit.
Optionally, in an embodiment of the present invention, the signal control unit includes: the trigger comprises a judgment structure, a first trigger structure and a second trigger structure;
the input end of the judging structure is electrically connected with the output end of the logic control unit, and the output end of the judging structure is electrically connected with the first input end of the first triggering structure and used for:
determining the first number from the second pulse signal; judging whether the first quantity is greater than the second preset value or not; if yes, outputting a first control signal; if not, stopping outputting the first control signal;
the second input end of the first trigger structure is electrically connected with the first constant voltage end, the third input end is electrically connected with the frequency dividing unit, and the output end is electrically connected with the first input end of the second trigger structure, so as to:
when the rising edge of the first control signal is not acquired, outputting a second control signal according to a first constant voltage provided by the first constant voltage end; carrying out reset processing according to the first pulse signal and the second control signal;
the second input end of the second trigger structure is electrically connected with the frequency dividing unit, and the output end of the second trigger structure is electrically connected with the switching module and is used for:
when the second control signal is received, the enabling signal is sent to the switching module according to the first pulse signal; and carrying out reset processing according to the first pulse signal.
Optionally, in an embodiment of the present invention, the determining structure includes a K-ary counter and a third inverter;
the K-system counter is provided with a reset end, and the third phase inverter is arranged between the reset end and the output end of the K-system counter.
Optionally, in an embodiment of the present invention, the first trigger structure includes: the circuit comprises a first D trigger, a fourth inverter, a fifth inverter, a NOR gate logic circuit and a first delay circuit;
a reference input end of the first D trigger is electrically connected with an output end of the judging structure, a control input end of the first D trigger is electrically connected with the first constant voltage end, and an output end of the first D trigger is electrically connected with an input end of the fifth inverter;
the output end of the fifth inverter is electrically connected with the first input end of the NOR gate logic circuit;
the input end of the first delay circuit is electrically connected with the frequency dividing unit, and the output end of the first delay circuit is electrically connected with the second input end of the NOR gate logic circuit;
the output end of the NOR gate logic circuit is electrically connected with the input end of the fourth inverter;
and the output end of the fourth inverter is electrically connected with the reset end of the first D trigger.
Optionally, in an embodiment of the present invention, the second trigger structure includes: the second D trigger, the sixth inverter, the seventh inverter and the second delay circuit;
the control input end of the second D trigger is electrically connected with the output end of the first trigger structure, the reference input end of the second D trigger is electrically connected with the output end of the sixth phase inverter, the reset end of the second D trigger is electrically connected with the output end of the seventh phase inverter, and the output end of the second D trigger is electrically connected with the switching module;
the input end of the sixth inverter is electrically connected with the input end of the second delay circuit;
the input end of the seventh inverter is electrically connected with the input end of the second delay circuit;
the input end of the second delay circuit is electrically connected with the frequency dividing unit;
the first delay circuit is used for delaying a first time, the second delay circuit is used for delaying a second time, and the second time is smaller than the first time.
The invention has the following beneficial effects:
according to the switching power converter provided by the embodiment of the invention, the detection module is determined according to the gate turn-on signal of the input switching transistor when detecting whether the load is currently in a heavy load state, so that even if the switching power converter is a low-power converter and the switching power converter works in a PFM working mode, the current state of the load can be effectively detected in time, and further the switching power converter can be effectively switched to a corresponding working mode (such as a PWM working mode) in time, so that the output voltage ripple is reduced.
Drawings
Fig. 1 is a PFM operating loop in a switching power converter;
fig. 2 is a switching power converter according to an embodiment of the present invention;
fig. 3 is another switching power converter provided in an embodiment of the present invention;
FIG. 4 is a schematic diagram of a specific structure of a detection module corresponding to FIG. 2;
FIG. 5 is a schematic diagram of a specific structure of a detection module corresponding to FIG. 3;
fig. 6 is a schematic structural diagram of a logic control unit provided in the embodiment of the present invention;
fig. 7 is a schematic structural diagram of a signal control unit provided in an embodiment of the present invention;
FIG. 8 is a schematic diagram of another exemplary structure of the detecting module corresponding to FIG. 2;
FIG. 9 is a schematic diagram of another exemplary structure of the detecting module corresponding to FIG. 3;
FIG. 10 is a timing diagram provided in an embodiment of the present invention;
fig. 11 is another timing diagram provided in an embodiment of the invention.
Wherein, the device comprises a1, a 2-D trigger, a 3-low voltage comparator, a 4-high current threshold comparator, a 5-2to 1MUX unit, a 6-logic adjusting unit, a 7-PWM/PFM determining unit, an 8-heavy load detecting unit, a 9-zero crossing detector, a 10-detecting module, a 20-switching module, a 30-switching module, an 11-frequency dividing unit, a 12-logic control unit, a 13-signal control unit, a 13 a-judging structure, a 13 b-first triggering structure, a 13 c-second triggering structure, a W1-first inverter, a W2-second inverter, a W3-third inverter, a W4-fourth inverter, a W5-fifth inverter, a W6-sixth inverter, a W7-seventh inverter, 12 a-nand gate logic circuit, 13a1-K system counter, 13b 1-first D flip-flop, 13b 2-nor gate logic circuit, 13b 3-first delay circuit, 13c 1-second D flip-flop, 13c 2-second delay circuit.
Detailed Description
A detailed description will be given below of a specific implementation of a switching power converter according to an embodiment of the present invention with reference to the accompanying drawings. It should be noted that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The inventor finds in research that, for a conventional switching power converter, such as the PFM operating loop shown in fig. 1, when the load current is smaller than the critical value, it indicates that the load is in a light load state, so the operation of the switching power converter needs to enter the PFM mode, at this time, the PWM/PFM determining unit 7 outputs a low level signal, that is, PFM is equal to L, so that the 2to 1MUX unit 5 switches the switching power converter from the PWM mode to the PFM mode, that is, the switching power converter switches from the PWM operating loop to the PFM operating loop.
In PFM mode, the specific operation may be as follows:
when the N-type transistor T2 is turned on, a ground signal provided from the ground GND is transmitted to the inductor L, so that the current flowing through the inductor L linearly decreases. When the current flowing through the inductor L crosses zero, ZCD (i.e., zero crossing detector) 9 outputs a low level signal, and then the transistor T2 is turned off by the control of D flip-flop 1 and logic adjusting unit 6. Since the P-type transistor T1 is also currently off, only the output capacitor C is presentoutIs a load resistance RLSupply power so as to output a voltage VoutAnd gradually decreases.
When the output voltage V isoutWhen the voltage drops to a level at which the signal output from the low voltage comparator 3 is inverted to a high level signal, the transistor T1 is turned on by the D flip-flop 2, the 2to 1MUX unit 5, and the logic adjusting unit 6, so as to output the power voltage V0 to the load, and further output the voltage V0outGradually increasing. Until the signal output by the high current threshold comparator 4 is inverted to a high level signal, the transistor T1 is turned off under the control of a plurality of structures, and the transistor T2 is turned on, so that the current flowing through the inductor L linearly decreases again. Then, ZCD 9 continues to detect whether the current flowing through inductor L crosses zero, and repeats itself and works in cycles.
When the switching power converter operates in the PFM mode, the overload detection unit 8 is configured to detect whether the load has entered a overload state, or whether the load is currently in the overload state.
When the load current is greater than or equal to the critical value, the overload detection unit 8 outputs a signal to the PWM/PFM determination unit 7, so that the PWM/PFM determination unit 7 outputs a high level signal, that is, PFM is equal to H, and then the switching power converter is switched from the PFM operation loop to the PWM operation loop (the PWM operation loop is not shown in the figure) through the 2to 1MUX unit 5, thereby realizing the switching power converter jumping from the PFM mode to the PFM mode.
For the present heavy load detection unit 8, as shown in fig. 1, a comparator is included, a first input terminal of the comparator is used for inputting a first voltage V1, and the first voltage V1 is obtained when an output voltage V is collectedoutThe voltage is obtained by dividing voltage through a first resistor R1 and a second resistor R2; the first input of the comparator is used for inputting a reference voltage, and the reference voltage can be Vref1-Va, where Va is a constant number.
For the result shown in fig. 1, the principle of heavy load detection may specifically be:
when the load jumps from light load to large heavy load, the load resistance RLInitially from the output capacitor CoutObtain current to make output voltage V of switching power supply converteroutAnd gradually decreases. Since the switching power converter operates in PFM mode and the switching speeds of the transistor T1 and the transistor T2 are slow, the inductance L and the output capacitance C cannot be controlled by two transistorsoutSupply sufficient power to ensure output voltage VoutThe output is stable; thus, the output voltage VoutIt will gradually decrease until the corresponding first voltage V1 is lower than the reference voltage (i.e. Vref1-Va), so that the signal output by the comparator in the reload detection unit 8 flips, for example, but not limited to, from a low level signal to a high level signal, and the high level signal is processed when being output to the PWM/PFM determination unit 7, and the PWM/PFM determination unit 7 outputs a high level signal, thereby realizing the switching of the switching power converter from the PFM mode to the PWM mode.
Moreover, the heavy load detection unit 8 in fig. 1 is only suitable for the case where the load enters the heavy load with a large critical value from the light load, that is, only suitable for the switching power converter with large power.
This is due to:
for example, for a switching power converter supporting a maximum load current of 1A, the switching power converter may be understood as a higher-power switching power converter, and the heavy load critical value of the switching power converter may be 100 mA; when the load current is 1mA, the switching power supply converter works in a PFM mode; when the load current jumps from 1mA to 500mA, the load resistor R is caused by the larger load currentLThe slave output capacitor C is requiredoutObtain a larger current so as to output a voltage VoutThe drop is faster. Thus, the output voltage VoutThe corresponding first voltage V1 drops to be less than the reference voltage very quickly, so that the comparator in the heavy load detection unit 8 outputs a high level signal, thereby enabling the switching power converter to correctly jump from the PFM mode to the PWM mode.
However, for a low power switching power converter, such as a switching power converter supporting a maximum load current of 100mA, the heavy load threshold may be 10 mA; when the load current is 1mA, the switching power supply converter works in a PFM mode; when the load current jumps from 1mA to 10mA, the load resistor R is caused by the fact that the load current jumped to is smallLThe slave output capacitor C is requiredoutObtain a small current so as to output a voltage VoutThe drop is slower.
Even if the switching speed of the transistors (such as T1 and T2 in FIG. 1) of the switching power converter is slow at this time, the power supply voltage V0 can be the inductor L and the output capacitor C if the transistors pass through the power supply voltage V0outProviding sufficient power to maintain the output voltage VoutWhen stable, the output voltage VoutThe drop will not continue; however, at the output voltage VoutBefore the PFM mode drops to the critical point, a new switching cycle corresponding to the PFM mode has come, i.e., the transistor T1 is turned on, and the power voltage V0 is transmitted to the inductor L and the output capacitor CoutIn, to inductance L and output capacitance CoutCharging, at the time of output voltage VoutIt will increase. Thus, the output voltage VoutThe corresponding first voltage V1 is notIt will be decreased to be less than the reference voltage (i.e. Vref1-Va), so that the comparator in the heavy load detection unit 8 will not output a high level signal, which results in that the switching power supply converter cannot jump from the PFM mode to the PWM mode, and finally cannot realize the switching of the operating mode.
Based on this, the embodiment of the present invention provides a switching power converter, which is used for enabling a low-power switching power converter to still accurately and effectively implement switching of a working mode.
Specifically, a switching power converter provided in an embodiment of the present invention, as shown in fig. 2 and fig. 3, may include: a detection module 10, a switching module 20, and a switch module 30;
the switch module 30 includes switch transistors (e.g., T1 and T2), the detection module 10 is electrically connected to gates of the switch transistors, and the detection module 10 is further electrically connected to the switching module 20;
the detection module 10 is configured to:
determining the load (such as but not limited to the load resistor R) based on the gate turn-on signal input to the switching transistorL) When the current state is in the overload state, an enable signal is sent to the switching module 20, so that the switching module 20 is switched to the corresponding working mode.
Therefore, in the embodiment of the present invention, since the detection module determines according to the gate turn-on signal of the input switching transistor when detecting whether the load is currently in the heavy load state, even if the switching power converter is a low power converter and the switching power converter operates in the PFM operating mode, the current state of the load can be effectively detected in time, and then the switching power converter can be effectively switched to the corresponding operating mode (for example, the PWM operating mode) in time, so as to reduce the output voltage ripple.
Optionally, in an embodiment of the present invention, referring to fig. 2, the load may include: inductor L and output capacitor CoutAnd a load resistor RLOf course, other structures may be included, and the specific structure of the load may be set according to actual needs, and is not limited herein, and only the example shown in fig. 2 is described here.
Alternatively, in an embodiment of the present invention, as shown in fig. 2 and 3, the switch module 30 is electrically connected to the load;
when the load is in a heavy load state, the pulse period of the grid opening signal is smaller than a first preset value; or when the load is in a light load state, the pulse period of the grid opening signal is not less than the first preset value.
That is, when the load is in a heavy load state, the pulse period of the gate-on signal is small, and when the load is in a light load state, the pulse period of the gate-on signal is large.
This is due to:
taking the structure shown in fig. 2 as an example, the output capacitance can be obtained through an inductor L and an output capacitor CoutIs a load resistance RLPower is supplied and the inductor L and the output capacitor C can be driven by the supply voltage V0 each time the switching transistors T1 and T2 are turned onoutCharging is performed, then:
if the load is in a light load state, the load resistor RLThe required electric energy is less, so the on-off of the switch transistor T1 and the switch transistor T2 can be controlled by less times, namely the load resistance R can be satisfiedLThe need of (c); therefore, the opening frequency of the switch transistor is smaller, and the pulse period of the grid opening signal is larger;
if the load is in a heavy load state, the load resistor RLMore power is required, so that the load resistor R can be satisfied by controlling the on-state of the switch transistor T1 and the switch transistor T2 for more timesLThe need of (c); therefore, the opening frequency of the switch transistor is larger, and the pulse period of the grid opening signal is smaller.
Therefore, based on the principle, the current state of the load can be judged according to the pulse period of the grid opening signal, so that heavy load detection is realized, and the switching power supply converter can work normally and effectively.
Optionally, in an embodiment of the present invention, the detection module is specifically configured to:
the enable signal is determined according to a pulse period of the gate-on signal and a pulse period of the clock signal.
Therefore, because the pulse period of the gate-on signal is fixed, the pulse period of the clock signal is also fixed, and the pulse period of the gate-on signal is related to the state of the load, when the enable signal is determined, that is, when the load is detected to be in a heavy load state, the current state of the load can still be accurately detected without being affected by the power of the switching power converter, so that the switching power converter provided by the embodiment of the invention has a wide application range.
In specific implementation, in the embodiment of the present invention, when the detection module is configured, as shown in fig. 4 and 5, where the structure shown in fig. 4 corresponds to fig. 2, and the structure shown in fig. 5 corresponds to fig. 3, the detection module 10 includes: a frequency dividing unit 11, a logic control unit 12, and a signal control unit 13;
the input end of the frequency dividing unit 11 is electrically connected to the gate of the switching transistor, and the output end is electrically connected to the first input end of the logic control unit 12, and is configured to: performing frequency division processing on a gate-on signal (such as a Pgate signal or an Ngate signal, wherein the gate-on signal is a periodic square wave signal) to obtain a first pulse signal (such as M1);
a second input terminal of the logic control unit 12 is electrically connected to the clock signal terminal CLK, and an output terminal is electrically connected to an input terminal of the signal control unit 13, and is configured to: performing logic processing on the first pulse signal M1 and the clock signal provided by the clock signal terminal CLK to obtain a second pulse signal (as shown in M2);
the output end of the signal control unit 13 is electrically connected to the switching module 20, and is configured to: determining the number of corresponding clock signals in the pulse period of the first pulse signal M1 according to the second pulse signal M2, and defining the number as a first number; when the first number is greater than the second preset value, an enable signal (shown as X) is sent to the switching module 20.
Therefore, through the synergistic effect among the three units, the detection module can determine the enabling signal according to the pulse period of the grid opening signal and the pulse period of the clock signal, so that the switching module switches the working module according to the enabling signal, and the switching power supply converter can normally and effectively work when heavy load detection is completed.
Specifically, in the embodiment of the present invention, the frequency dividing unit may include a frequency dividing circuit.
The frequency dividing circuit may be, but is not limited to, a frequency dividing circuit, and N may be an integer greater than 1.
Therefore, the function of the frequency division unit can be realized through a simple structure, heavy load detection is favorably realized, the structure of the detection module is favorably simplified, the structure of the switching power supply converter is further simplified, and the manufacturing cost of the switching power supply converter is reduced.
Further, in the embodiment of the present invention, as shown in fig. 2, the switching transistor electrically connected to the detection module 10 may be an N-type transistor;
alternatively, as shown in fig. 3, the switching transistor electrically connected to the detection module 10 may also be a P-type transistor, and in this case, as shown in fig. 5, the detection module 10 may further include: and a first inverter W1 provided between the gate of the switching transistor and the frequency dividing unit 11.
So, can set up detection module according to the type of switching transistor for no matter what type of switching transistor, the overload detection all can be realized, with the needs that satisfy various application scenarios, the flexibility of improvement design.
To explain one point, optionally, in the embodiment of the present invention, the setting number of the switching transistors included in the switching unit is not limited to that shown in fig. 2 and 3, that is, the number of the switching transistors included in the switching unit may be 1, 3, or another number, as long as the function of the switching module can be realized, and the switching power converter can be ensured to operate normally.
Specifically, in the embodiment of the present invention, as shown in fig. 6, the logic control unit 12 includes a nand gate logic circuit 12a and a second inverter W2;
the nand gate circuit 12a has a first input terminal (e.g., Y1) electrically connected to the frequency divider 11, a second input terminal (e.g., Y2) electrically connected to the clock signal terminal CLK, and an output terminal electrically connected to the input terminal of the second inverter W2;
an output terminal of the second inverter W2 is electrically connected to the signal control unit 13.
That is, the nand gate logic circuit needs to perform and processing on the input first pulse signal and the clock signal, and then obtain the second pulse signal after the inversion processing of the second inverter.
The specific processing procedure may include:
if the first pulse signal is a high-level signal and the clock signal is also a high-level signal, the low-level signal is output after the processing of the NAND gate logic circuit, and the high-level signal is output by the logic control unit through the reverse processing of the second inverter;
if the first pulse signal is a high-level signal and the clock signal is a low-level signal, the high-level signal is output after being processed by the nand gate logic circuit, and the logic control unit outputs a low-level signal after being reversely processed by the second inverter, so that the pulse signal shown as M2 in fig. 10 and 11 is finally obtained.
Therefore, the signal control unit can read the first number according to the second pulse signal, that is, the number of the clock signals (N shown in fig. 10 and 11) corresponding to the pulse period of the first pulse signal is determined, so that whether the signal control unit outputs the enable signal or not is facilitated, that is, whether the load is currently in a heavy load state or not is determined by the signal control unit, and the switching of the working modes is facilitated.
Specifically, in the embodiment of the present invention, when the signal control unit is set, the following manner may be adopted:
mode 1:
optionally, in the embodiment of the present invention, not shown in the drawings, the signal control unit may be a processor, a controller, or a single chip microcomputer.
Therefore, the function of the signal control unit can be realized through a simple structure, heavy load detection is favorably realized, the structure of the detection module is favorably simplified, the structure of the switching power supply converter is further simplified, and the manufacturing cost of the switching power supply converter is reduced.
Mode 2:
optionally, in the embodiment of the present invention, as shown in fig. 7, the signal control unit 13 may include: a judgment structure 13a, a first trigger structure 13b, and a second trigger structure 13 c;
the input end of the judging structure 13a is electrically connected to the output end of the logic control unit 12, and the output end is electrically connected to the first input end of the first triggering structure 13b, and is configured to:
determining a first number from the second pulse signal M2; judging whether the first quantity is greater than a second preset value or not; if yes, outputting a first control signal (as S1); if not, stopping outputting the first control signal S1;
the second input terminal of the first triggering structure 13b is electrically connected to the first constant voltage terminal VDD, the third input terminal is electrically connected to the frequency dividing unit 11, and the output terminal is electrically connected to the first input terminal of the second triggering structure 13c, for:
outputting a second control signal according to the first constant voltage provided by the first constant voltage terminal VDD when the rising edge of the first control signal S1 is not collected (e.g., S2); performing reset processing according to the first pulse signal M1 and the second control signal S2;
a second input end of the second triggering structure 13c is electrically connected to the frequency dividing unit 11, and an output end is electrically connected to the switching module 20, and is configured to:
upon receiving the second control signal S2, sending an enable signal (e.g., X) to the switching module 20 according to the first pulse signal M1; the reset process is performed in accordance with the first pulse signal M1.
When the first trigger structure 13b acquires the rising edge of the first control signal S1, the third control signal (e.g., S3) may be output according to the first constant voltage provided by the first constant voltage terminal VDD, so that the second trigger structure 13c sends the disable signal to the switching module 20 when receiving the third control signal S3, so that the switching module 20 does not switch the operating mode.
The second control signal and the third control signal may be implemented in the form of: the second control signal is a high level signal, and the third control signal is a low level signal; or, the second control signal is a low level signal, and the third control signal is a high level signal. As long as the second control signal and the third control signal can be distinguished, the implementation forms of the second control signal and the third control signal are not particularly limited.
Moreover, taking the first control signal as an example when the high level signal is valid, when the determining structure 13a stops outputting the first control signal, no signal may be output, or a low level signal may be output, which may be set according to actual needs to meet the needs of different application scenarios, thereby improving the flexibility of design.
Therefore, the function of the signal control unit can be realized through the synergistic effect of the judging structure, the first triggering structure and the second triggering structure, so that the enabling signal needing to be output can be accurately and effectively controlled, and the accuracy of heavy load detection is improved.
Specifically, in the embodiment of the present invention, as shown in fig. 8 and 9, the judgment structure 13a includes a K-system counter 13a1 and a third inverter W3;
the K-ary counter 13a1 has a reset terminal R, and the third inverter W3 is disposed between the reset terminal R and the output terminal Q of the K- ary counter 13a 1.
At this time, since the third inverter W3 is disposed between the reset terminal R and the output terminal Q of the K-ary counter 13a1, when the K-ary counter 13a1 outputs the first control signal S1 (for example, but not limited to, a high level signal), the first control signal S1 is inverted by the third inverter W3 and then outputted to the reset terminal R of the K-ary counter 13a1, and accordingly, a low level signal is inputted to the reset terminal R, and when the reset process is performed by inputting a low level signal to the reset terminal R, the low level signal can perform the reset process on the K-ary counter 13a1 to stop outputting the first control signal S1.
Therefore, the first control signal S1 outputted by the determining structure 13a is a short pulse signal, and the pulse width of the first control signal S1 can be set according to the timing requirement of the first D flip-flop (described later) and other factors, so as to ensure the normal operation of the first D flip-flop, and further ensure the normal operation of the first triggering structure.
The value of K in the K-system counter 13a1 may be determined according to a reloading threshold, and may be a value of 1, 2, or 3, and the like, which is not limited herein.
The specific structure of the K-ary counter 13a1 may be other structures known to those skilled in the art, and is not limited herein.
Thus, by the cooperation between the K-ary counter 13a1 and the third inverter W3, the determining structure 13a can accurately and effectively output the first control signal S1, so that the first triggering structure 13b operates according to the first control signal S1, thereby implementing the function of the signal control unit 13 and implementing the heavy load detection.
Specifically, in the embodiment of the present invention, as shown in fig. 8 and 9, the first triggering structure 13b may include: a first D flip-flop 13b1, a fourth inverter W4, a fifth inverter W5, a nor gate logic circuit 13b2, and a first delay circuit 13b 3;
a reference input terminal (e.g., C) of the first D flip-flop 13b1 is electrically connected to the output terminal of the determining structure 13a, a control input terminal (e.g., D) is electrically connected to the first constant voltage terminal VDD, and an output terminal (e.g., Q) is electrically connected to the input terminal of the fifth inverter W5;
the output terminal of the fifth inverter W5 is electrically connected to the first input terminal (e.g., Y1) of the nor gate logic circuit 13b 2;
the input end of the first delay circuit 13b3 is electrically connected with the frequency dividing unit 11, and the output end is electrically connected with the second input end (such as Y2) of the NOR gate logic circuit 13b 2;
the output terminal of the nor gate logic circuit 13b2 is electrically connected to the input terminal of the fourth inverter W4;
an output terminal of the fourth inverter W4 is electrically connected to the reset terminal R of the first D flip- flop 13b 1.
For the first D flip-flop 13b1, the operation principle may be as follows:
referring to fig. 8, when the reference input terminal C acquires a rising edge signal, if the control input terminal D inputs a high level signal, the output terminal Q outputs a high level signal; or, when the reference input terminal C collects a rising edge signal, if the control input terminal D inputs a low level signal, the output terminal Q outputs a low level signal.
For the nor gate logic circuit 13b2, the operation principle may be:
when both input terminals of the nor gate logic circuit 13b2 receive a low level signal, a high level signal is output; alternatively, when a high-level signal is input to one of the two input terminals of the nor gate logic circuit 13b2 and a low-level signal is input to the other input terminal, a low-level signal is output.
The operation of the first trigger structure 13b will be described with reference to the timing charts shown in fig. 10 and 11, taking fig. 8 and 9 as an example.
1. See the timing diagram shown in fig. 10.
When the reference input terminal C of the first D flip-flop 13b1 picks up a rising edge of the first control signal (as shown in S1 in fig. 10), since the control input terminal D is electrically connected to the first constant voltage terminal VDD, and when the first constant voltage provided by the first constant voltage terminal VDD is a high level signal, the output terminal Q of the first D flip-flop 13b1 may output a high level signal (as shown in K0 in fig. 8 to 10), and the high level signal is inverted into a low level signal (as shown in S3 in fig. 10) after being inverted by the fifth inverter W5, and the low level signal is respectively input into the nor logic circuit 13b2 and the second trigger structure 13C; therefore, ignoring the processing time of the fifth inverter W5, the first flip-flop structure 13b outputs a low level signal from the time when the rising edge of the first control signal S1 is acquired.
By the delay action of the first delay circuit 13b3, the falling edge of the first pulse signal M1 (e.g., a high signal) can be delayed by a first time t1, so that the pulse signal shown by M1a in fig. 10 is obtained and then output to the nor gate logic circuit 13b 2.
Since the fifth inverter W5 and the first delay circuit 13b3 both currently input a low level signal to the nor gate logic circuit 13b2, the nor gate logic circuit 13b2 outputs a high level signal to the fourth inverter W4, and after the inversion processing of the fourth inverter W4, inputs a low level signal to the reset terminal R of the first D flip- flop 13b 1.
Since the first D flip-flop 13b1 can perform the reset process when the reset terminal R inputs a low-level signal, the output terminal Q of the first D flip-flop 13b1 toggles from outputting a high-level signal to outputting a low-level signal at the end of the first time t1, that is, the first flip-flop 13b toggles from outputting a low-level signal to outputting a high-level signal at the end of the first time t 1.
2. See the timing diagram shown in fig. 11.
When the reference input C of the first D flip-flop 13b1 does not capture the rising edge of the first control signal (as shown in S1 in fig. 11), the output Q of the first D flip-flop 13b1 outputs a low level signal (as shown in K0 in fig. 8, 9 and 11), and the low level signal is inverted into a high level signal (as shown in S2 in fig. 11) after being inverted by the fifth inverter W5 and is input into the nor logic circuit 13b2 and the second flip-flop structure 13C, respectively.
By the delay action of the first delay circuit 13b3, the falling edge of the first pulse signal M1 (e.g., a high signal) can be delayed by a first time t1, so that the pulse signal shown by M1a in fig. 11 is obtained and then output to the nor gate logic circuit 13b 2.
Since the two input terminals of the nor gate logic circuit 13b2 input a low level signal and a high level signal respectively, the nor gate logic circuit 13b2 outputs a low level signal to the fourth inverter W4, and inputs a high level signal to the reset terminal R of the first D flip-flop 13b1 after the inversion processing of the fourth inverter W4.
For the first D flip-flop 13b1, when the reset terminal R inputs a high level signal, the reset processing is not performed for the time being, and therefore, the output terminal of the first D flip-flop 13b1 continues to output a low level signal, that is, the first flip-flop 13b continues to output a high level signal (that is, the second control signal mentioned above).
In this way, the first D flip-flop 13b1, the fourth inverter W4, the fifth inverter W5, the nor gate logic circuit 13b2, and the first delay circuit 13b3 cooperate with each other to realize the function of the first trigger structure 13b, which is favorable for realizing the function of the signal control unit 13, and realizing the heavy load detection, so as to realize the switching of the operation modes.
Specifically, in the embodiment of the present invention, as shown in fig. 8 and 9, the second trigger structure 13c includes: a second D flip-flop 13c1, a sixth inverter W6, a seventh inverter W7, and a second delay circuit 13c 2;
a control input end D of the second D flip-flop 13C1 is electrically connected with an output end of the first triggering structure 13b, a reference input end C is electrically connected with an output end of the sixth inverter W6, a reset end R is electrically connected with an output end of the seventh inverter W7, and an output end Q is electrically connected with the switching module 20;
an input terminal of the sixth inverter W6 is electrically connected to an output terminal of the second delay circuit 13c 2;
an input terminal of the seventh inverter W7 is electrically connected to an input terminal of the second delay circuit 13c 2;
the input terminal of the second delay circuit 13c2 is electrically connected to the frequency dividing unit 11;
the first delay circuit 13b3 is used for delaying a first time, and the second delay circuit 13c2 is used for delaying a second time, wherein the second time is less than the first time.
The operation principle of the second D flip-flop 13c1 is similar to that of the first D flip-flop 13b1, and it can be referred to the above specifically, and will not be described in detail here.
Next, the operation of the second triggering mechanism 13c will be described with reference to the timing diagrams shown in fig. 10 and 11, taking fig. 8 and 9 as an example.
By the delay action of the second delay circuit 13c2, the falling edge of the first pulse signal M1 (for example, a high level signal) can be delayed by a second time t2, and the first time t1 is greater than the second time t 2; and, at the end of the second time T2, the falling edge signal is inputted into the sixth inverter W6, converted into the rising edge signal by the inversion process of the sixth inverter W6, and inputted into the reference input terminal C of the first D flip- flop 13b 1; therefore, when the reference input terminal C of the first D flip-flop 13b1 acquires the rising edge signal output by the sixth inverter W6, then:
1. see the timing diagram shown in fig. 10.
If the control input end D of the second D flip-flop 13c1 does not acquire a high level signal (i.e., acquires a low level, as in S3), the output end Q of the second D flip-flop 13c1 outputs a low level signal (i.e., an disable signal), so that the switching module 20 does not switch the operating module, that is, the current load is in a light load state, and the switching power converter still operates in the PFM mode.
2. See the timing diagram shown in fig. 11.
If the control input D of the second D flip-flop 13c1 acquires a high signal (i.e., the aforementioned second control signal, as shown in S2 in fig. 11), the output Q of the second D flip-flop 13c1 may output a high signal; therefore, if the signal processing time of the sixth inverter W6 is neglected, from the end of the second time t2, the second trigger structure 13c outputs a high level signal (i.e., an enable signal, such as X in fig. 11), so that the switching module 20 performs the switching of the operating module, that is, the operating mode of the switching power converter is switched from the PFM mode to the PWM mode when the current load is in the heavy load state.
When a rising edge of the next cycle of the first pulse signal M1 (e.g., a high level signal) arrives, that is, when the first pulse signal M1 transitions from a low level signal to a high level signal, the high level signal is converted into a low level signal through the inversion process of the seventh inverter W7, and is input to the reset terminal R of the second D flip-flop 13c1, the second D flip-flop 13c1 is reset, so that the output terminal Q of the second D flip-flop 13c1 transitions from outputting a high level signal to outputting a low level signal, that is, if the signal processing time of the seventh inverter W7 is ignored, the second flip-flop 13c stops outputting the enable signal when the first pulse signal M1 transitions from a low level signal to a high level signal (as shown in fig. 11).
In this way, the second D flip-flop 13c1, the sixth inverter W6, the seventh inverter W7, and the second delay circuit 13c2 cooperate to realize the function of the second trigger structure 13c, which is favorable for realizing the function of the signal control unit 13 and the heavy load detection, so as to realize the switching of the operating mode.
It should be noted that, optionally, in the embodiment of the present invention, the switching power converter may further include other structures besides the detection module 10, the switching module 20, and the switching module 30 shown in fig. 2 and fig. 3, for example, but not limited to the structures of the D flip-flop 1, the D flip-flop 2, the low voltage comparator, and the high current threshold comparator in fig. 1, and as long as the functions of the switching power converter can be protected, the embodiments of the present invention also belong to the scope of the present invention.
The specific structure of the switching module may include: the PWM/PFM determining unit 7, the 2to 1MUX unit 5, and the logic adjusting unit 6 shown in fig. 1, of course, the specific structure of the switching module is not limited to be composed of the above three units, and other structures capable of implementing the switching module may also be adopted, as long as the functions of the switching module can be implemented, which all fall within the scope of the protection claimed in the embodiment of the present invention.
It should be further noted that, since the switching power converter may include other structures besides the detection module 10, the switching module 20 and the switching module 30 shown in fig. 2 and fig. 3, for example, the logic adjusting unit 6 shown in fig. 1, and the logic adjusting unit 6 is used to provide the gate turn-on signals for the transistor T1 and the transistor T2, optionally, in the embodiment of the present invention, not shown, when the switching power converter includes the logic adjusting unit, it may be further configured to:
the detection module can be electrically connected with the logic adjusting unit and is not electrically connected with the switch module;
that is, the logic adjusting unit provides the gate-on signal for the detection module, or the logic adjusting unit provides the last-stage driving signal of the gate-on signal for the detection module (the period of the signal is the same as that of the gate-on signal), so that the detection module determines whether the load is currently in the load state according to the gate-on signal, and the judgment of the load state is completed, thereby facilitating the switching of the working mode of the switching power converter.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims (10)

1. A switching power converter, comprising: the device comprises a detection module, a switching module and a switch module;
the switch module comprises a switch transistor, the detection module is electrically connected with a grid electrode of the switch transistor, and the detection module is also electrically connected with the switching module;
the detection module is used for:
when the load is determined to be in a heavy load state at present according to the gate opening signal input to the switching transistor, sending an enabling signal to the switching module so as to enable the switching module to be switched to a corresponding working mode;
the detection module comprises: the frequency dividing unit, the logic control unit and the signal control unit;
the input end of the frequency dividing unit is electrically connected with the grid electrode of the switching transistor, and the output end of the frequency dividing unit is electrically connected with the first input end of the logic control unit, and is used for: performing frequency division processing on the grid opening signal to obtain a first pulse signal;
the second input end of the logic control unit is electrically connected with the clock signal end, and the output end of the logic control unit is electrically connected with the input end of the signal control unit and used for: performing logic processing on the first pulse signal and a clock signal provided by the clock signal end to obtain a second pulse signal;
the output end of the signal control unit is electrically connected with the switching module and is used for: determining the number of the corresponding clock signals in the pulse period of the first pulse signal according to the second pulse signal, and defining the number as a first number; and when the first quantity is judged to be larger than a second preset value, sending the enabling signal to the switching module.
2. The switching power converter of claim 1, wherein the detection module is specifically configured to:
and determining the enabling signal according to the pulse period of the grid opening signal and the pulse period of the clock signal.
3. The switching power converter of claim 1, wherein the switching module is electrically connected to the load;
when the load is in the heavy load state, the pulse period of the grid opening signal is smaller than a first preset value; or when the load is in a light load state, the pulse period of the grid opening signal is not less than the first preset value.
4. The switching power converter of claim 1, wherein the frequency dividing unit comprises a frequency dividing circuit.
5. The switching power converter according to claim 4, wherein the switching transistor electrically connected to the detection module is an N-type transistor;
or, the switch transistor electrically connected with the detection module is a P-type transistor; the detection module further comprises: and the first inverter is arranged between the grid of the switching transistor and the frequency dividing unit.
6. The switching power converter according to claim 1, wherein the logic control unit comprises a nand gate logic circuit and a second inverter;
the first input end of the NAND gate logic circuit is electrically connected with the frequency dividing unit, the second input end of the NAND gate logic circuit is electrically connected with the clock signal end, and the output end of the NAND gate logic circuit is electrically connected with the input end of the second inverter;
and the output end of the second inverter is electrically connected with the signal control unit.
7. The switching power converter according to claim 1, wherein the signal control unit comprises: the trigger comprises a judgment structure, a first trigger structure and a second trigger structure;
the input end of the judging structure is electrically connected with the output end of the logic control unit, and the output end of the judging structure is electrically connected with the first input end of the first triggering structure and used for:
determining the first number from the second pulse signal; judging whether the first quantity is greater than the second preset value or not; if yes, outputting a first control signal; if not, stopping outputting the first control signal;
the second input end of the first trigger structure is electrically connected with the first constant voltage end, the third input end is electrically connected with the frequency dividing unit, and the output end is electrically connected with the first input end of the second trigger structure, so as to:
when the rising edge of the first control signal is not acquired, outputting a second control signal according to a first constant voltage provided by the first constant voltage end; carrying out reset processing according to the first pulse signal and the second control signal;
the second input end of the second trigger structure is electrically connected with the frequency dividing unit, and the output end of the second trigger structure is electrically connected with the switching module and is used for:
when the second control signal is received, the enabling signal is sent to the switching module according to the first pulse signal; and carrying out reset processing according to the first pulse signal.
8. The switching power converter according to claim 7, wherein the judging structure comprises a K-ary counter and a third inverter;
the K-system counter is provided with a reset end, and the third phase inverter is arranged between the reset end and the output end of the K-system counter.
9. The switching power converter of claim 7, wherein the first triggering mechanism comprises: the circuit comprises a first D trigger, a fourth inverter, a fifth inverter, a NOR gate logic circuit and a first delay circuit;
a reference input end of the first D trigger is electrically connected with an output end of the judging structure, a control input end of the first D trigger is electrically connected with the first constant voltage end, and an output end of the first D trigger is electrically connected with an input end of the fifth inverter;
the output end of the fifth inverter is electrically connected with the first input end of the NOR gate logic circuit;
the input end of the first delay circuit is electrically connected with the frequency dividing unit, and the output end of the first delay circuit is electrically connected with the second input end of the NOR gate logic circuit;
the output end of the NOR gate logic circuit is electrically connected with the input end of the fourth inverter;
and the output end of the fourth inverter is electrically connected with the reset end of the first D trigger.
10. The switching power converter of claim 9, wherein the second triggering mechanism comprises: the second D trigger, the sixth inverter, the seventh inverter and the second delay circuit;
the control input end of the second D trigger is electrically connected with the output end of the first trigger structure, the reference input end of the second D trigger is electrically connected with the output end of the sixth phase inverter, the reset end of the second D trigger is electrically connected with the output end of the seventh phase inverter, and the output end of the second D trigger is electrically connected with the switching module;
the input end of the sixth inverter is electrically connected with the output end of the second delay circuit;
the input end of the seventh inverter is electrically connected with the input end of the second delay circuit;
the input end of the second delay circuit is electrically connected with the frequency dividing unit;
the first delay circuit is used for delaying a first time, the second delay circuit is used for delaying a second time, and the second time is smaller than the first time.
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