CN104135790A - LED (Light-emitting Diode) dimming control circuit - Google Patents

Abstract

The invention discloses an LED (Light-emitting Diode) dimming control circuit. The switching frequency of an ON/OFF switch is calculated by means of a counting and dimming controller, three-step dimming is adopted, as for 100 percent brightness at a first step, a standard reference voltage provided by a reference voltage selector is adopted to adjust when a Power MOS (Metal Oxide Semiconductor) tube is switched off; as for 50 percent brightness at a second step, the duration of switching off the Power MOS is prolonged by a delayer; and as for 25percent brightness at a third step, the reference voltage is reduced and the duration of switching off the Power MOS is simultaneously prolonged so as to achieve the purpose of deeply controlling brightness. By means of the LED dimming control circuit, the anti-interference capability is greatly improved during deeply controlling brightness, moreover, LED stepped dimming can be performed by the current general ON/OFF switch, and the LED dimming control circuit has high generality and is wide in application.

Description

A kind of LED adjusting control circuit

Technical field

The present invention relates to LED adjusting control circuit, relate in particular to a kind of control circuit that carries out the light modulation of LED segmentation with ON/OFF switch.

Background technology

Along with the development of LED illumination, LED light regulating technology also makes rapid progress.ON/OFF switch dimming technology is to record ON/OFF number of conventional wall switch, select different LED output currents, realizes light modulation.

Referring to the LED driver in the ON/OFF switch dimming technology shown in Fig. 1, generally all adopt PowerMOS switch source series resistor to survey output current, by output current value feed back to controller inner with voltage reference relatively after, realize LED current constant.

In traditional LED dimming driver, conventionally change internal voltage reference and regulate LED electric current, thereby realize light modulation.There is following shortcoming in this control mode:

A., when light modulation to 25% is following, internal reference drops to low voltage.Now reference voltage is easily disturbed, and deviation is larger.

B. when light modulation, along with internal reference voltage drop, operating frequency can increase.The increase of operating frequency, can increase EMI and disturb, and increases the EMC cost of application scheme.

So research and develop a kind of in the time that light modulation is darker anti-interference strong, working stability LED adjusting control circuit be the technical problem of needing in the industry solution badly.

Summary of the invention

The present invention is the problems referred to above that will solve prior art, proposes one anti-interference strong, working stability LED adjusting control circuit in the time that light modulation is darker.

For solving the problems of the technologies described above, the technical scheme that the present invention proposes is a kind of LED adjusting control circuit of design, have connect the current input terminal of LED major loop, by the current output terminal of gallon resistance R 1 ground connection, between electric current input/output terminal, be connected in series successively the second metal-oxide-semiconductor and the first metal-oxide-semiconductor, connect the power conversion module of civil power, power conversion module provides lasting DC power supply and provide working power in the time of outside ON/OFF switch connection, and the gate pole of the second metal-oxide-semiconductor connects described working power; It also comprises: counting and light adjusting controller, connect described working power, and in order to calculate the on-off times of ON/OFF switch, send time delayed signal and adjust reference voltage signal according to on-off times; Zero current detector, connects the tie point of the second metal-oxide-semiconductor and the first metal-oxide-semiconductor, in order to survey in the TOFF time L1 electric current in (when the first and second not conductings of MOS) major loop, is to send zero current signal at 1 o'clock at L1 electric current; Delayer, its input respectively connection count and light adjusting controller is connected with zero current detector, its outlet side first with the input of (U202), first is connected described zero current signal with another input of door, time delayed signal and zero current signal simultaneously effectively time delayer send a delay pulse by first with door; Reference voltage selector, its input is connection standard reference voltage and low reference voltage respectively, and its output is selected an outputting standard reference voltage or low reference voltage according to described adjustment reference voltage signal; The first comparator, its reverse input end connects the output of described reference voltage selector, and its positive input connects described current output terminal; Rest-set flip-flop, its S end connects described delay pulse, and its R end connects the output of described the first comparator, and its output connects the gate pole of the first metal-oxide-semiconductor by the 4th not gate.

Described counting and light adjusting controller have the second comparator, first to 3d flip-flop, wherein the in-phase input end of the second comparator connects one end of the first resistance and the second resistance, working power described in another termination of the first resistance, the other end ground connection of the second resistance, the reverse input end of the second comparator connects the second comparative level, the output termination first of the second comparator is to the clock end of 3d flip-flop, working power described in the D termination of the first d type flip flop, the D end of Q termination second d type flip flop of the first d type flip flop, the D end of the Q termination 3d flip-flop of the second d type flip flop, the non-end of Q of the first d type flip flop is exported described time delayed signal by the first not gate, the non-end of Q of the second d type flip flop is exported described adjustment reference voltage signal by the second not gate, non-termination first reset terminal to 3d flip-flop of Q of 3d flip-flop.

Described zero current detector has the 3rd comparator, its reverse input end connects one end of the 3rd resistance and the 4th resistance, it inputs one end of termination the 5th resistance and the 6th resistance in the same way, an input of its output termination second and door, second exports described zero current signal with the output of door, the tie point of the second metal-oxide-semiconductor and the first metal-oxide-semiconductor described in another termination of the 3rd resistance, working power described in another termination of the 5th resistance, the other end ground connection of the 4th resistance and the 6th resistance, second with the output of rest-set flip-flop described in another input termination of door.

Described delayer comprises the charging current source being serially connected in successively between described DC power supply and ground, the first electronic switch, the second electronic switch, discharging current source, the wherein output of control termination first NAND gate of the first and second electronic switches, two inputs of the first NAND gate connect respectively described time delayed signal and zero current signal, the tie point of the first and second electronic switches connects one end of the first electric capacity and the reverse input end of the 3rd comparator, the other end ground connection of the first electric capacity, the in-phase input end of the 3rd comparator connects the first comparative level (V1), the input of output termination second NAND gate of the 3rd comparator, time delayed signal described in another input termination of the second NAND gate, the output of the second NAND gate is exported described delay pulse.

Described reference voltage selector comprises the 3rd electronic switch and quadrielectron switch, described adjustment reference voltage signal connects the control end of quadrielectron switch and connects the control end of the 3rd electronic switch by the first not gate, standard basis voltage described in the input termination of the 3rd electronic switch, low reference voltage described in the input termination of quadrielectron switch, the output of the third and fourth electronic switch also connects the described standard basis voltage of rear output or low reference voltage.

The magnitude of voltage of described low reference voltage is the half of the magnitude of voltage of standard basis voltage.

Compared with prior art, the present invention is in the time of the degree of depth light modulation when (be less than rated power 25%), not only regulated internal reference voltage but also regulated opening time of Power MOS switch, so internal reference voltage can not drop to too little value, operating frequency can not increase to too large value yet.Thereby driver antijamming capability is provided, and saves the EMC cost of application scheme.And the present invention can utilize comparatively general ON/OFF switch (switch panel of metope) at present to carry out the light modulation of LED segmentation, and highly versatile, uses extensively.

Brief description of the drawings

Fig. 1 is traditional LED driver current detection circuit schematic diagram;

Fig. 2 is principle of the invention block diagram;

Work wave when Fig. 3 is first paragraph brightness;

Work wave when Fig. 4 is second segment brightness;

Work wave when Fig. 5 is the 3rd section of brightness;

Fig. 6 is the circuit diagram of delayer in preferred embodiment of the present invention;

Fig. 7 is the sequential chart of delayer;

Fig. 8 is the circuit diagram of zero current detector in preferred embodiment of the present invention;

Fig. 9 is counting and the circuit diagram of light adjusting controller in preferred embodiment of the present invention;

Figure 10 is the circuit diagram of reference voltage selector in preferred embodiment of the present invention.

Embodiment

In order to make object of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the present invention is described in further detail.Should be appreciated that specific embodiment described herein, only for explaining the present invention, is not intended to limit the present invention.

In LED light adjusting circuit, there is power conversion module, civil power is transformed into direct current, be connected LED lamp at the positive pole (LED+) passing through in Fig. 1 or Fig. 2 with negative pole (LED-), between both positive and negative polarity, connect fly-wheel diode (D1) and the first inductance (L1), the adjusting control circuit of connecting between the tie point of D1 and L1 and ground.It can be also integrated chip that said adjusting control circuit can be made up of discrete component.In preferred embodiment of the present invention, adjusting control circuit is made to integrated chip.

The LED adjusting control circuit disclosing referring to Fig. 2 the present invention, it has the current input terminal DRN that connects LED major loop, by the current output terminal CS of gallon resistance R 1 ground connection, between electric current input/output terminal, be connected in series successively the second metal-oxide-semiconductor (also claiming Power MOS) Q2 and the first metal-oxide-semiconductor Q1, connect the power conversion module (not drawing in figure) of civil power, power conversion module provides lasting DC power supply VDD, and in the time of outside ON/OFF switch connection, provide working power VIN (when ON/OFF switch access failure, working power is without electricity), the gate pole of the second metal-oxide-semiconductor connects described working power, it also comprises: counting and light adjusting controller, connect described working power, in order to calculate the on-off times of ON/OFF switch, send time delayed signal (CTR_TOFF) and adjust reference voltage signal (CTR_REF) according to on-off times, zero current detector, the tie point (FB) of connection the second metal-oxide-semiconductor and the first metal-oxide-semiconductor, in order to survey main circuit current size, is to send zero current signal (ZCS) at 1 o'clock at institute's probe current, delayer, its input respectively connection count and light adjusting controller is connected with zero current detector, its outlet side first with an input of a U202, first is connected described zero current signal with another input of door, time delayed signal and zero current signal simultaneously effectively time delayer send a delay pulse by first with door, reference voltage selector, its input is connection standard reference voltage and low reference voltage respectively, and its output is selected an outputting standard reference voltage or low reference voltage according to described adjustment reference voltage signal, the first comparator U201, its reverse input end connects the output of described reference voltage selector, and its positive input connects described current output terminal, rest-set flip-flop U203, its S end connects described delay pulse, and its R end connects the output of described the first comparator, and its output connects the gate pole of the first metal-oxide-semiconductor by the 4th not gate U204.

This patent adopts source pole driving mode, can realize syllogic ON/OFF switching buck brightness adjustment control, and in preferred embodiment, first paragraph is 100% brightness, and second segment is 50% brightness, and the 3rd section is 25% brightness.

Working waveform figure when Fig. 3 shows first paragraph brightness, in the time of 100% brightness, LED driver is operated in critical current mode conduction mode, and LED starter internal reference voltage is VREF.In the time of Power MOS (Q1 and Q2) conducting (TON device), in Fig. 2, inductance L 1 electric current starts to increase:

$I_{L1}\left(t\right)=\underset{0}{\overset{T_{\mathrm{ON}}}{\∫}}\frac{V_{\mathrm{BUS}}-V_{\mathrm{LED}}}{L1}\mathrm{dt}$

Wherein VBUS is bus (DC-BUS) voltage.In the TON period, also flow through R1 by the electric current of L1.Along with the increase of L1 electric current, CS terminal voltage (R1*IR1) also increases, and in the time that VCS increases to VREF, Power MOS disconnects (being that TON finishes), and now inductive current is:

$I_{L1\_\mathrm{PEAK}}=\frac{V_{\mathrm{BUS}}-V_{\mathrm{LED}}}{L1}*T_{\mathrm{ON}}=\frac{\mathrm{VREF}}{R1}$

Because inductive current can not suddenly change, this electric current sustained diode 1 of flowing through, backflow bus, until electric current is reduced to zero.The zero current detector of LED driver detects after inductive current to zero, again makes Power MOS conducting, starts next switch periods, as shown in Figure 3.Because LED driver works in electric current critical conduction mode, the average current of LED is the half of L1 peak current:

$I_{\mathrm{LED}1}=\frac{1}{2}*I_{L1\_\mathrm{PEAK}1}=\frac{1}{2}*\frac{V_{\mathrm{BUS}}-V_{\mathrm{LED}}}{L1}*T_{\mathrm{ON}}=\frac{1}{2}*\frac{\mathrm{VREF}}{R1}$

Flow through flyback period of sustained diode 1 of definition inductive current is TFB, and now TOFF is TFB, and operating frequency is:

$f_{\mathrm{OP}1}=\frac{1}{T_{\mathrm{ON}1}+T_{\mathrm{OFF}1}}=\frac{1}{T_{\mathrm{ON}1}+T_{\mathrm{FB}1}}$

When carrying out after an ON/OFF operation, driver enters second segment luminance state.Internal reference voltage keeps VREF constant.But TOFF control module can increase the TDEAD time, TOFF total time is increased, as shown in Figure 4:

T _OFF＝T _DEAD+T _FB

Due to busbar voltage, L1 inductance value and internal reference voltage do not change, and the TON time is consistent during with first paragraph, the same when in each switch periods inductance, energy is with first paragraph.Now, the average current of LED:

$I_{\mathrm{LED}2}=\frac{1}{2}*I_{L1\_\mathrm{PEAK}2}\frac{T_{\mathrm{ON}2}+T_{\mathrm{FB}2}}{T_{\mathrm{ON}2}+T_{\mathrm{OFF}2}}=I_{\mathrm{LED}1}*\frac{T_{\mathrm{ON}2}+T_{\mathrm{FB}2}}{T_{\mathrm{ON}2}+T_{\mathrm{OFF}2}}=I_{\mathrm{LED}1}*\frac{T_{\mathrm{ON}2}+T_{\mathrm{FB}2}}{T_{\mathrm{ON}2}+T_{\mathrm{FB}2}+T_{\mathrm{DEAD}2}}$

In the time that TDEAD equals Power MOS ON time TON and TFB sum, the average current of LED is 50% of ILED1:

$I_{\mathrm{LED}2}=\frac{1}{2}*I_{\mathrm{LED}1}$

Second segment brightness is 50% of nominal brightness.Operating frequency also drops to the half of former operating frequency fOP1.

$f_{\mathrm{OP}2}=\frac{1}{T_{\mathrm{ON}2}+T_{\mathrm{FB}2}+T_{\mathrm{DEAD}2}}=\frac{1}{2*(T_{\mathrm{ON}1}+T_{\mathrm{FB}1})}=\frac{1}{2}*f_{\mathrm{OP}1}$

After ON/OFF operates again, driver enters the 3rd section of operating state.It is (1/2) * VREF that internal reference voltage controller will be adjusted reference voltage.Making TDEAD referring to Fig. 5 delayer is Power MOS ON time TON and TFB sum.Half while dropping to first paragraph due to reference voltage, the also drop by half of peak current IL1_PEAK of inductance L 1.Now, the average current of LED is:

$I_{\mathrm{LED}3}=\frac{1}{2}*I_{L1\_\mathrm{PEAK}3}*\frac{T_{\mathrm{ON}}+T_{\mathrm{FB}}}{T_{\mathrm{ON}}+T_{\mathrm{OFF}}}=\frac{1}{4}*I_{L1\_\mathrm{PEAK}1}*\frac{T_{\mathrm{ON}}+T_{\mathrm{FB}}}{T_{\mathrm{ON}}+T_{\mathrm{OFF}}}=\frac{1}{2}*I_{\mathrm{LED}1}*\frac{T_{\mathrm{ON}}+T_{\mathrm{FB}}}{T_{\mathrm{ON}}+T_{\mathrm{FB}}+T_{\mathrm{DEAD}}}$

Because TDEAD is Power MOS ON time TON and TFB sum, the average current of LED:

$I_{\mathrm{LED}3}=\frac{1}{2}*I_{\mathrm{LED}1}*\frac{T_{\mathrm{ON}}+T_{\mathrm{FB}}}{T_{\mathrm{ON}}+T_{\mathrm{FB}}+T_{\mathrm{DEAD}}}=\frac{1}{4}*I_{\mathrm{LED}1}$

While being first paragraph due to reference voltage 1/2, TON and TFB are reduced to original half, but TDEAD is just TON and TFB sum.Now operating frequency fOP3 will be consistent with first paragraph operating frequency.

$f_{\mathrm{OP}3}=\frac{1}{T_{\mathrm{ON}3}+T_{\mathrm{FB}3}+T_{\mathrm{DEAD}3}}=\frac{1}{2*(T_{\mathrm{ON}3}+T_{\mathrm{FB}3})}=\frac{1}{T_{\mathrm{ON}1}+T_{\mathrm{FB}1}}=f_{\mathrm{OP}1}$

This patent, in this three-stage dimming control circuit, when rated power 25% is arrived in light modulation: operating frequency excursion is little, only reduces to 50% in the time of second segment; Internal reference change in voltage is also less, only drops to the half of VREF.Can effectively improve the shortcoming in traditional dimming mode.

Referring to the circuit diagram of counting and light adjusting controller in the preferred embodiment shown in Fig. 9, described counting and light adjusting controller have the second comparator U901, first to 3d flip-flop, wherein the in-phase input end of the second comparator connects one end of the first resistance R 901 and the second resistance R 902, working power VIN described in another termination of the first resistance, the other end ground connection of the second resistance, the reverse input end of the second comparator meets the second comparative level V2 (V2 can be obtained by VDD dividing potential drop), the output termination first of the second comparator is to the clock end of 3d flip-flop, working power VDD described in the D termination of the first d type flip flop U902, the D end of the Q termination second d type flip flop U903 of the first d type flip flop, the D end of the Q termination 3d flip-flop U904 of the second d type flip flop, the non-end of Q of the first d type flip flop is exported described time delayed signal (CTR_TOFF) by the first not gate U906, the non-end of Q of the second d type flip flop is exported described adjustment reference voltage signal (CTR_REF) by the second not gate U905, non-termination first reset terminal to 3d flip-flop of Q of 3d flip-flop.

In the time that outside ON/OFF switch is connected for the first time, working power VIN powers on, and the second comparator U901 in-phase input end obtains a higher level, a high level of the second comparator output terminal output.Now, time delayed signal (CTR_TOFF) is low level, the delayer work that is not triggered; Reference voltage signal (CTR_REF) is low level simultaneously, reference voltage selector outputting standard reference voltage, 100% brightness of LED lamp.In the time of the power-off for the first time of outside ON/OFF switch, working power VIN power down, the second metal-oxide-semiconductor Q2 cut-off, LED lamp extinguishes.

In the time that outside ON/OFF switch is connected for the second time, working power VIN powers on, and the second comparator U901 exports high level again, and making time delayed signal (CTR_TOFF) is high level, delayer triggering work, the time lengthening of the first metal-oxide-semiconductor Q1 cut-off; Make to adjust reference voltage signal (CTR_REF) for low level, reference voltage selector outputting standard reference voltage, 50% brightness of LED lamp simultaneously.In the time of the power-off for the second time of outside ON/OFF switch, LED lamp extinguishes.

In the time that outside ON/OFF switch is connected for the third time, working power VIN powers on, and the second comparator U901 exports high level again, and making time delayed signal (CTR_TOFF) is high level, delayer triggering work, the time lengthening of the first metal-oxide-semiconductor Q1 cut-off; Make to adjust reference voltage signal (CTR_REF) is high level simultaneously, and reference voltage selector is exported low reference voltage, 25% brightness of LED lamp.In the time of the power-off for the third time of outside ON/OFF switch, LED lamp extinguishes.

Referring to the circuit diagram of zero current detector in the preferred embodiment shown in Fig. 8, it has the 3rd comparator U801, its reverse input end connects one end of the 3rd resistance R 803 and the 4th resistance R 804, it inputs one end of termination the 5th resistance R 801 and the 6th resistance R 802 in the same way, an input of its output termination second and door (U802), second exports described zero current signal ZCS with the output of door, the tie point FB of the second metal-oxide-semiconductor Q2 and the first metal-oxide-semiconductor Q1 described in another termination of the 3rd resistance, working power VIN described in another termination of the 5th resistance, the other end ground connection of the 4th resistance and the 6th resistance, second with the output of rest-set flip-flop described in another input termination of door.In the time that the electric current of L1 in major loop becomes zero, FB point voltage reduces, U801 output high potential (being ZCS high level), the delayer time delay that is triggered.

Referring to the circuit diagram of delayer in the preferred embodiment shown in Fig. 6, it comprises the charging current source Isource being serially connected in successively between described DC power supply VDD and ground, the first electronic switch S1, the second electronic switch S2, discharging current source Isink, the wherein output of the control termination first NAND gate U601 of the first and second electronic switches, two inputs of the first NAND gate connect respectively described time delayed signal and zero current signal, the tie point of the first and second electronic switches connects one end of the first capacitor C 1 and the reverse input end of the 3rd comparator U602, the other end ground connection of the first electric capacity, the in-phase input end of the 3rd comparator meets the first comparative level V1 (V1 can be obtained by VDD dividing potential drop), the input of the output termination second NAND gate U603 of the 3rd comparator, time delayed signal described in another input termination of the second NAND gate, the output of the second NAND gate is exported described delay pulse.In the time of Q1 conducting (TON), zero current signal (ZCS) is low level, and the first electric capacity starts charging; Q1 close have no progeny, zero current detector detect L1 electric current to zero before (being TFB), zero current signal (ZCS) be still low level, first electric capacity continue charge.Now, on electric capacity, voltage is greater than V1 voltage, and comparator U602 is output as high level.In the time that zero current detector detects L1 electric current to zero, zero current signal (ZCS) for high level, time delayed signal (CTR_TOFF) and zero current signal (ZCS) simultaneously effective (being all high level), NAND gate U601 output low level, control S1 closure, S2 disconnection, the first capacitor C 1 starts electric discharge.Now the current potential of input in the same way of comparator U602 is higher, U602 exports high level, time delayed signal (CTR_TOFF) is now high level, through the second NAND gate U603 output low level, this signal level is delivered to an input with door U202, another input of U202 connects described zero current signal, and the S end of the output termination rest-set flip-flop of U202 uses Q1 to continue to turn-off; U602 output low level after C1 current potential drops to V2 gradually, makes rest-set flip-flop upset, Q1 conducting.Be the TDEAD time discharge time of the first capacitor C 1.In the time that Isink is equal with Isource, the TDEAD time is TON and TFB sum, as shown in Figure 7.

Referring to the circuit diagram of reference voltage selector in the preferred embodiment shown in Figure 10, it comprises the 3rd electronic switch S3 and quadrielectron switch S 4, described adjustment reference voltage signal (CTR_REF) connects the control end of quadrielectron switch and connects the control end of the 3rd electronic switch by the first not gate U1001, standard basis voltage (VREF) described in the input termination of the 3rd electronic switch, low reference voltage (1/2VREF) described in the input termination of quadrielectron switch, the output of the third and fourth electronic switch also connects the described standard basis voltage of rear output or low reference voltage.Outputting standard reference voltage in the time adjusting reference voltage signal (CTR_REF) low level, exports low reference voltage while adjusting reference voltage signal high level like this.

In preferred embodiment, the magnitude of voltage of described low reference voltage is the half of the magnitude of voltage of standard basis voltage.

Above embodiment is only for illustrating, non-providing constraints.Anyly do not depart from the application's spirit and category, and equivalent modifications or change that it is carried out all should be contained among the application's claim scope.

Claims (6)

1. a LED adjusting control circuit, have connect the current input terminal of LED major loop, by the current output terminal of gallon resistance (R1) ground connection, between electric current input/output terminal, be connected in series successively the second metal-oxide-semiconductor (Q2) and the first metal-oxide-semiconductor (Q1), connect the power conversion module of civil power, power conversion module provides lasting DC power supply (VDD) and working power (VIN) is provided in the time of outside ON/OFF switch connection, the gate pole of the second metal-oxide-semiconductor connects described working power, characterized by further comprising:

Counting and light adjusting controller, connect described working power, in order to calculate the on-off times of ON/OFF switch, sends time delayed signal and adjust reference voltage signal according to on-off times;

Zero current detector, the tie point of connection the second metal-oxide-semiconductor and the first metal-oxide-semiconductor, in order to survey main circuit current size, is to send zero current signal at 1 o'clock at institute's probe current;

Delayer, its input respectively connection count and light adjusting controller is connected with zero current detector, its outlet side first with the input of (U202), first is connected described zero current signal with another input of door, time delayed signal and zero current signal simultaneously effectively time delayer send a delay pulse by first with door;

Reference voltage selector, its input is connection standard reference voltage and low reference voltage respectively, and its output is selected an outputting standard reference voltage or low reference voltage according to described adjustment reference voltage signal;

The first comparator (U201), its reverse input end connects the output of described reference voltage selector, and its positive input connects described current output terminal;

Rest-set flip-flop (U203), its S end connects described delay pulse, and its R end connects the output of described the first comparator, and its output connects the gate pole of the first metal-oxide-semiconductor by the 4th not gate (U204).

2. LED adjusting control circuit as claimed in claim 1, it is characterized in that: described counting and light adjusting controller have the second comparator (U901), first to 3d flip-flop, wherein the in-phase input end of the second comparator connects one end of the first resistance (R901) and the second resistance (R902), working power (VIN) described in another termination of the first resistance, the other end ground connection of the second resistance, the reverse input end of the second comparator connects the second comparative level (V2), the output termination first of the second comparator is to the clock end of 3d flip-flop, working power (VDD) described in the D termination of the first d type flip flop (U902), the D end of Q termination second d type flip flop (U903) of the first d type flip flop, the D end of the Q termination 3d flip-flop (U904) of the second d type flip flop, the non-end of Q of the first d type flip flop is exported described time delayed signal by the first not gate (U906), the non-end of Q of the second d type flip flop is exported described adjustment reference voltage signal by the second not gate (U905), non-termination first reset terminal to 3d flip-flop of Q of 3d flip-flop.

3. LED adjusting control circuit as claimed in claim 2, it is characterized in that: described zero current detector has the 3rd comparator (U801), its reverse input end connects one end of the 3rd resistance (R803) and the 4th resistance (R804), it inputs one end of termination the 5th resistance (R801) and the 6th resistance (R802) in the same way, an input of its output termination second and door (U802), second exports described zero current signal with the output of door, the tie point of the second metal-oxide-semiconductor (Q2) and the first metal-oxide-semiconductor (Q1) described in another termination of the 3rd resistance, working power (VIN) described in another termination of the 5th resistance, the other end ground connection of the 4th resistance and the 6th resistance, second with the output of rest-set flip-flop described in another input termination of door.

4. LED adjusting control circuit as claimed in claim 3, it is characterized in that: described delayer comprises the charging current source being serially connected in successively between described DC power supply (VDD) and ground, the first electronic switch (S1), the second electronic switch (S2), discharging current source, the wherein output of control termination first NAND gate (U601) of the first and second electronic switches, two inputs of the first NAND gate connect respectively described time delayed signal and zero current signal, the tie point of the first and second electronic switches connects one end of the first electric capacity (C1) and the reverse input end of the 3rd comparator (U602), the other end ground connection of the first electric capacity, the in-phase input end of the 3rd comparator connects the first comparative level (V1), the input of output termination second NAND gate (U603) of the 3rd comparator, time delayed signal described in another input termination of the second NAND gate, the output of the second NAND gate is exported described delay pulse.

5. LED adjusting control circuit as claimed in claim 4, it is characterized in that: described reference voltage selector comprises the 3rd electronic switch (S3) and quadrielectron switch (S4), described adjustment reference voltage signal connects the control end of quadrielectron switch and connects the control end of the 3rd electronic switch by the first not gate (U1001), standard basis voltage described in the input termination of the 3rd electronic switch, low reference voltage described in the input termination of quadrielectron switch, the output of the third and fourth electronic switch also connects the described standard basis voltage of rear output or low reference voltage.

6. LED adjusting control circuit as claimed in claim 5, is characterized in that: the magnitude of voltage of described low reference voltage is the half of the magnitude of voltage of standard basis voltage.