CN105356564A - Wireless energy receiving system - Google Patents
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Abstract
The invention provides a wireless energy receiving system, which is used for a wireless energy receiving end and includes a resonance module, a rectifier module, a control module and a driving module. The resonance module is used for receiving wireless energy and converting the received wireless energy into alternating voltage signals. The rectifier module is electrically connected to the resonance module, includes a plurality of field effect transistors and is used for performing rectification on the alternating voltage signals. The control module is electrically connected to the rectifier module, and is used for outputting a plurality of sequential control signals to control the plurality of field effect transistors in one-to-one correspondence. The driving module is electrically connected to the rectifier module and the control module, and is used for amplifying the plurality of sequential control signals to control the on-off states of the plurality of field effect transistors. The abovementioned wireless energy receiving system adopts the four high-voltage power field effect transistors to perform full-bridge rectification on the alternating voltage converted from the received wireless energy, thereby effectively improving conversion efficiency of a rectifier bridge.
Description
Technical field
The present invention relates to wireless charging system, particularly relate to a kind of wireless energy receiving system of full-bridge synchronous rectification.
Background technology
Wireless charging technology due to advantages such as convenient, safety, more and more use by main flow mobile phone production firm.There is the control mode of two kinds of main flows at present: magnetic induction and magnetic resonance.No matter adopt which kind of control mode, for receiving terminal, all need ac voltage signal to convert d. c. voltage signal to, charge to the battery of mobile phone.
But existing receiving terminal power unit, general four diodes as shown in Figure 1 that adopt carry out full-bridge rectification, add a step-down conversion chip to charging mobile phone battery; Or be adopt two diodes as shown in Figure 2 and two high-voltage power NMOS tube to carry out full-bridge rectification, add a step-down conversion chip to charging mobile phone battery.The former is with four diode rectifications, and due to the conduction voltage drop of diode, when input current is very large, the loss of four diodes can be very large; Although the latter instead of two diodes by two high-voltage power NMOS tube, still have the loss of two diodes.Meanwhile, these diodes and high-voltage power NMOS are discrete devices, are unfavorable for the integrated and miniaturized of receiving terminal power unit.Therefore be necessary to propose a kind of follow-on wireless energy receiving system to overcome above-mentioned defect.
Summary of the invention
The object of the invention is to, a kind of wireless energy receiving system is provided, effectively can improve rectification, the conversion efficiency of the wireless energy of reception.
To achieve these goals, the invention provides a kind of wireless energy receiving system, for wireless energy receiving terminal, comprise resonance modules, rectification module, control module and driver module.Described resonance modules is for receiving wireless energy and converting received wireless energy to ac voltage signal.Described rectification module is electrically connected on described resonance modules, comprises multiple field effect transistor, for carrying out rectification to described ac voltage signal.Described control module is electrically connected on described rectification module, for exporting multiple timing control signal, controls described multiple field effect transistor with one_to_one corresponding.Described driver module is electrically connected on described rectification module and described control module, for amplifying described multiple timing control signal, to control the on off state of described multiple field effect transistor.
Preferably, described wireless energy receiving system also comprises filtration module, is electrically connected on described rectification module, for carrying out filtering to the ac voltage signal after rectification.
Preferably, described rectification module comprises the first NMOS tube, second NMOS tube, 3rd NMOS tube and the 4th NMOS tube, the drain electrode of described first NMOS tube is electrically connected on the first output of described resonance modules, the source ground of described first NMOS tube, the grid of described first NMOS tube is electrically connected on described driver module, the drain electrode of described second NMOS tube is electrically connected on the second output of described resonance modules, the source ground of described second NMOS tube, the grid of described second NMOS tube is electrically connected on described driver module, the drain electrode of described 3rd NMOS tube is for exporting the alternating voltage after described rectification, the source electrode of described 3rd NMOS tube is electrically connected on the drain electrode of described second NMOS tube and the second output of described resonance modules, the grid of described 3rd NMOS tube is electrically connected on described driver module, the drain electrode of described 4th NMOS tube is electrically connected on the drain electrode of described 3rd NMOS tube, the source electrode of described 4th NMOS tube is electrically connected on the drain electrode of described first NMOS tube and the first output of described resonance modules, the grid of described 4th NMOS tube is electrically connected on described driver module.
Preferably, described rectification module also comprises the first electric capacity, second electric capacity, first diode and the second diode, one end of described first electric capacity is electrically connected on the first output of described resonance modules, the other end of described first electric capacity is electrically connected on the negative pole of described driver module and described first diode, the positive pole of described first diode is electrically connected on described driver module and the first reference voltage, one end of described second electric capacity is electrically connected on the second output of described resonance modules, the other end of described second electric capacity is electrically connected on the negative pole of described driver module and described second diode, the positive pole of described second diode is electrically connected on described driver module and described first reference voltage.
Preferably, described rectification module comprises the first NMOS tube, second NMOS tube, first PMOS and the second PMOS, the drain electrode of described first NMOS tube is electrically connected on the first output of described resonance modules, the source ground of described first NMOS tube, the grid of described first NMOS tube is electrically connected on described driver module, the drain electrode of described second NMOS tube is electrically connected on the second output of described resonance modules, the source ground of described second NMOS tube, the grid of described second NMOS tube is electrically connected on described driver module, the drain electrode of described first PMOS is electrically connected on the drain electrode of described second NMOS tube and the second output of described resonance modules, the source electrode of described first PMOS is for exporting the alternating voltage after described rectification, the grid of described first PMOS is electrically connected on described driver module, the drain electrode of described second PMOS is electrically connected on the drain electrode of described first NMOS tube and the first output of described resonance modules, the source electrode of described second PMOS is electrically connected on the source electrode of described first PMOS, the grid of described second PMOS is electrically connected on described driver module.
Preferably, described control module comprises the first sampling unit, the first comparing unit, the first arithmetic logic unit, the first voltage conversion unit, the second sampling unit, the second comparing unit, the second arithmetic logic unit and the second voltage conversion unit.Described first sampling unit is electrically connected on the first output of described resonance modules, and the alternating voltage for the first output to described resonance modules is sampled, to export the first sampled voltage.Described first comparing unit is electrically connected on described first sampling unit, for more described first sampled voltage and the first reference voltage, to export the first comparison signal, and for more described first sampled voltage and the second reference voltage, to export the second comparison signal, described first arithmetic logic unit is electrically connected on described first comparing unit, for exporting the first timing control signal and the 3rd timing control signal according to described first comparison signal, described second comparison signal.Described first voltage conversion unit is electrically connected on described first arithmetic logic unit, for carrying out level conversion to described 3rd timing control signal.Described second sampling unit is electrically connected on the second output of described resonance modules, and the alternating voltage for the second output to described resonance modules is sampled, to export the second sampled voltage.Described second comparing unit is electrically connected on described second sampling unit, for more described second sampled voltage and described first reference voltage, to export the 3rd comparison signal, and for more described second sampled voltage and described second reference voltage, to export the 4th comparison signal.Described second arithmetic logic unit is electrically connected on described second comparing unit, for exporting the second timing control signal and the 4th timing control signal according to described 3rd comparison signal, described 4th comparison signal.Described second voltage conversion unit is electrically connected on described second arithmetic logic unit, for carrying out level conversion to described 4th timing control signal.
Preferably, described first sampling unit comprises the first resistance, the 5th NMOS tube and the second resistance, one end of described first resistance is electrically connected on the first output of described resonance modules, the other end of described first resistance is electrically connected on the drain electrode of described 5th NMOS tube, the source electrode of described 5th NMOS tube is electrically connected on one end of described second resistance and described first comparing unit, the grid of described 5th NMOS tube is electrically connected on the internal electric source of described control module, the other end ground connection of described second resistance, described second sampling unit comprises the 3rd resistance, the 6th NMOS tube and the 4th resistance, one end of described 3rd resistance is electrically connected on the second output of described resonance modules, the other end of described 3rd resistance is electrically connected on the drain electrode of described 6th NMOS tube, the source electrode of described 6th NMOS tube is electrically connected on one end of described 4th resistance and described second comparing unit, the grid of described 6th NMOS tube is electrically connected on the internal electric source of described control module, the other end ground connection of described 4th resistance, described first comparing unit comprises the first hysteresis comparator, second hysteresis comparator, first inverter and the second inverter, the positive input of described first hysteresis comparator is electrically connected on one end of described second resistance, the reverse input end of described first hysteresis comparator is electrically connected on described first reference voltage, the output of described first hysteresis comparator is electrically connected on the input of described first inverter, the output of described first inverter is electrically connected on described first arithmetic logic unit, the reverse input end of described second hysteresis comparator is electrically connected on one end of described second resistance, the positive input of described second hysteresis comparator is electrically connected on described second reference voltage, the output of described second hysteresis comparator is electrically connected on the input of described second inverter, the output of described second inverter is electrically connected on described first arithmetic logic unit, described second comparing unit comprises the 3rd hysteresis comparator, 4th hysteresis comparator, 3rd inverter and the 4th inverter, the positive input of described 3rd hysteresis comparator is electrically connected on one end of described 4th resistance, the reverse input end of described 3rd hysteresis comparator is electrically connected on described first reference voltage, the output of described 3rd hysteresis comparator is electrically connected on the input of described 3rd inverter, the output of described 3rd inverter is electrically connected on described second arithmetic logic unit, the reverse input end of described 4th hysteresis comparator is electrically connected on one end of described 4th resistance, the positive input of described 4th hysteresis comparator is electrically connected on described second reference voltage, the output of described 4th hysteresis comparator is electrically connected on the input of described 4th inverter, the output of described 4th inverter is electrically connected on described second arithmetic logic unit.
Preferably, described control module comprises and also comprises enable unit, be electrically connected on described first arithmetic logic unit and described second arithmetic logic unit, for exporting the first enable signal or the second enable signal, alternately to control described first arithmetic logic unit and described second arithmetic logic unit work.
The present invention also provides a kind of wireless energy receiving system, for wireless charging receiving terminal, comprises resonance modules and voltage conversion chip.Described resonance modules is for receiving wireless energy and converting received wireless energy to ac voltage signal.Described voltage conversion chip is electrically connected on described resonance modules, and described voltage conversion chip comprises rectification module, control module and driver module.Described rectification module comprises multiple field effect transistor, for carrying out rectification to described ac voltage signal.Described control module, for exporting multiple timing control signal, controls described multiple field effect transistor with one_to_one corresponding.Described driver module is used for amplifying described multiple timing control signal, to control the on off state of described multiple field effect transistor.
Preferably, described wireless energy receiving system also comprises filtration module, is electrically connected on described voltage conversion chip, for carrying out filtering to the ac voltage signal after rectification.
Beneficial effect of the present invention: the invention provides a kind of wireless energy receiving system, four high-voltage power field effect transistor are adopted to carry out full-bridge rectification to the alternating voltage after the wireless energy conversion received, suitable technique can be adopted simultaneously, be integrated in converter chip, not only effectively improve the conversion efficiency of rectifier bridge, also improve the integrated level of chip, reduce production cost simultaneously.
In order to further understand feature of the present invention and technology contents, refer to following detailed description for the present invention and accompanying drawing, but accompanying drawing only provides reference and explanation use, is not used for being limited the present invention.
Accompanying drawing explanation
Fig. 1 is the full bridge rectifier of wireless charging receiving terminal in prior art one execution mode;
Fig. 2 is the full bridge rectifier of wireless charging receiving terminal in another execution mode of prior art;
Fig. 3 is the module map of wireless energy receiving system in an embodiment of the present invention;
Fig. 4 is the circuit diagram of wireless energy receiving system in an embodiment of the present invention;
Fig. 5 is the circuit diagram of wireless energy receiving system in another execution mode of the present invention;
Fig. 6 is the module map of control module in an embodiment of the present invention;
Fig. 7 is the circuit diagram of control module in an embodiment of the present invention;
Fig. 8 is the key node oscillogram in the circuit diagram of wireless energy receiving system in Fig. 4.
Embodiment
For further setting forth the technological means and effect thereof that the present invention takes, be described in detail below in conjunction with the preferred embodiments of the present invention and accompanying drawing thereof.
Fig. 3 is the module map of wireless energy receiving system 100 in an embodiment of the present invention.In the present embodiment, wireless energy receiving system 100 can be used in the receiving terminal of wireless charging, as supported on the handheld terminal of wireless charging.Wireless energy receiving system 100 comprises resonance modules 1, rectification module 2, control module 3 and driver module 4.Resonance modules 1 is for the wireless energy that receives wireless charging transmitting terminal and send and convert received wireless energy to ac voltage signal.Rectification module 2 is electrically connected on resonance modules 1, and rectification module 2 comprises multiple field effect transistor, is preferably 4 field effect transistor, and form full bridge rectifier, rectification module 2 carries out rectification for the ac voltage signal exported resonance modules 1.Control module 3 is electrically connected on rectification module 2, and control module 3, for exporting multiple timing control signal, controls conducting or the cut-off of multiple field effect transistor that rectification module 2 comprises with one_to_one corresponding.Driver module 4 is electrically connected on rectification module 2 and control module 3, because field effect transistor conducting needs the cut-in voltage of certain voltage value, and the control signal magnitude of voltage that control module 3 exports is less than normal, driver module 4 amplifies for the multiple timing control signals exported control module 3, to control the on off state of multiple field effect transistor.
Please refer to Fig. 4, as to further improvement of the present invention, wireless energy receiving system 100 also comprises filtration module 5, filtration module 5 is electrically connected on rectification module 2, filtration module 5, for carrying out filtering to the ac voltage signal after rectification module 2 rectification, charges to handheld device to export charging voltage.Filtration module 5 can use filter capacitor to realize filtering.
In an embodiment of the present invention, resonance modules 1 comprises coil coil, the first electric capacity C1, the second electric capacity C2.One end of coil coil is electrically connected on one end of the first electric capacity C1, and the other end of coil coil is electrically connected on one end of the second electric capacity C2, and the other end of the second electric capacity C2 is electrically connected on the other end of the first electric capacity C1.In the present embodiment, the other end of the first electric capacity C1 is as the first output terminals A C1 of resonance modules 1.The other end of coil coil is as the second output terminals A C2 of resonance modules 1.
In an embodiment of the present invention, rectification module 2 comprises the first NMOS tube Q1, the second NMOS tube Q2, the 3rd NMOS tube Q3 and the 4th NMOS tube Q4, the 3rd electric capacity BC1, the 4th electric capacity BC2, the first diode D1 and the second diode D2.The drain electrode of the first NMOS tube Q1 is electrically connected on the first output terminals A C1 of resonance modules 1, the source ground of the first NMOS tube Q1, and the grid of the first NMOS tube Q1 is electrically connected on driver module 4.The drain electrode of the second NMOS tube Q2 is electrically connected on the second output terminals A C2 of described resonance modules, the source ground of the second NMOS tube Q2, and the grid of the second NMOS tube Q2 is electrically connected on driver module 2.The drain electrode of the 3rd NMOS tube Q3 is electrically connected on filtration module 5, the drain electrode of the 3rd NMOS tube Q3 is for exporting the alternating voltage after rectification, the source electrode of the 3rd NMOS tube Q3 is electrically connected on the drain electrode of the second NMOS tube Q2 and the second output terminals A C2 of resonance modules, and the grid of the 3rd NMOS tube Q3 is electrically connected on driver module 4.The drain electrode of the 4th NMOS tube Q4 is electrically connected on the drain electrode of the 3rd NMOS tube Q3, and the source electrode of the 4th NMOS tube Q4 is electrically connected on the drain electrode of the first NMOS tube Q1 and the first output terminals A C1 of resonance modules 1, and the grid of the 4th NMOS tube Q4 is electrically connected on driver module 4.One end of 3rd electric capacity BC1 is electrically connected on the first output terminals A C1 of resonance modules 1, the other end of the 3rd electric capacity BC1 is electrically connected on the negative pole of driver module 4 and the first diode D1, the positive pole of the first diode D1 is electrically connected on driver module 4 and the first reference voltage V 1, one end of 4th electric capacity BC2 is electrically connected on the second output terminals A C2 of resonance modules 1, the other end of the 4th electric capacity BC2 is electrically connected on the negative pole of driver module 4 and the second diode D2, and the positive pole of the second diode D2 is electrically connected on driver module 4 and the first reference voltage V 1.First diode D1 and the second diode D2 is clamping action, ensure when the first output terminals A C1 or the second output terminals A C2 is negative, the voltage of the driver module 4 of the 3rd NMOS tube Q3 or the 4th NMOS tube Q4 can maintain V1 and deduct on the magnitude of voltage of a diode forward conduction voltage drop.Here also can with other device, the diode that such as triode connects or Darlington transistor realize the function of the first diode D1 and the second diode D2.First NMOS tube Q1, the second NMOS tube Q2, the 3rd NMOS tube Q3 and the 4th NMOS tube Q4 can adopt the NMOS tube of high-voltage power.
3rd electric capacity BC1 and the 4th electric capacity BC2 object are to ensure that the 3rd NMOS tube Q3 and the 4th NMOS tube Q4 can normally.Be greater than source voltage Vsource add a turn-on threshold voltage Vth because the condition of high-voltage power NMOS tube conducting is grid voltage Vgate.When the first output terminals A C1 or the second output terminals A C2 becomes positive voltage, because the 3rd electric capacity BC1 and the 4th electric capacity BC2 both end voltage can not be suddenlyd change, so the grid voltage of the 3rd NMOS tube Q3 or the 4th NMOS tube Q4 is V1-Vf+Vac1 or V1-Vf+Vac2 to the maximum.V1 is set as 5V ~ 6V, and Vf is generally 0.6V, and Vth is generally 0.7V, so the 3rd NMOS tube Q3 and the 4th NMOS tube Q4 can conducting completely.
For example, suppose that the peak value of input current is Ipk, so half period effective value is approximately Irms=0.5*Ipk, and mean value is approximately Iavg=0.32*Ipk, the conducting resistance of the first NMOS tube Q1 is assumed to 70mohm, and so in half period, the conduction loss of the first NMOS tube is:
Ploss_hvn＝2*Irms*Irms*Rdson＝0.035*Ipk*Ipk(W)
The conduction voltage drop of general rectifier diode is Vf=0.6V, if substitute the first NMOS tube Q1 with rectifier diode, so in half period, the conduction loss of rectifier diode is:
Ploss_dio＝2*Iavg*Vf＝0.384*Ipk(W)
Suppose Ipk=2A, so Ploss_hvn=0.14W, Ploss_dio=0.77W, clearly use the conduction loss of conduction loss much smaller than diode of the first NMOS tube Q1 of high-voltage power model.
Please refer to Fig. 5, it is the circuit diagram of the wireless energy receiving system 100 of the another kind of execution mode substantially identical with Fig. 4, in an embodiment of the present invention, rectification module 2 comprises the first NMOS tube Q1, the second NMOS tube Q2, the first PMOS Q5 and the second PMOS Q6, the drain electrode of the first NMOS tube Q1 is electrically connected on the first output terminals A C1 of resonance modules 1, the source ground of the first NMOS tube Q1, the grid of the first NMOS tube Q1 is electrically connected on driver module 4.The drain electrode of the second NMOS tube Q2 is electrically connected on the second output terminals A C2 of resonance modules 1, the source ground of the second NMOS tube Q2, and the grid of the second NMOS tube Q2 is electrically connected on driver module 4.The drain electrode of the first PMOS Q5 is electrically connected on the source electrode of the drain electrode of the second NMOS tube Q2 and the second output terminals A C2 of resonance modules 1, the first PMOS Q5 for exporting the alternating voltage after rectification, and the grid of the first PMOS Q5 is electrically connected on driver module 4.The drain electrode of the second PMOS Q6 is electrically connected on the drain electrode of the first NMOS tube Q1 and the first output terminals A C1 of resonance modules 1, and the source electrode of the second PMOS Q6 is electrically connected on the source electrode of the first PMOS Q5, and the grid of the second PMOS Q6 is electrically connected on driver module 4.
It should be noted that, because driver module 4 is used to the conducting of four field effect transistor driven in rectification module 2, therefore driver module 4 can comprise four independently driver elements, and each driver element one_to_one corresponding drives each field effect transistor.In the present embodiment, each driver element comprises buffer.
Please refer to Fig. 6, Fig. 7, in an embodiment of the present invention, control module 3 comprises the first sampling unit 31, second sampling unit 32, first comparing unit 33, second comparing unit 34, first arithmetic logic unit 35, second arithmetic logic unit 36, first voltage conversion unit 37 and the second voltage conversion unit 38.First sampling unit 31 is electrically connected on the first output terminals A C1 of resonance modules 1, and the alternating voltage for the first output terminals A C1 to resonance modules 1 is sampled, to export the first sampled voltage.First comparing unit 33 is electrically connected on the first sampling unit 31, for comparing the first sampled voltage and first reference voltage V 1 of the first sampling unit 31 output, to export the first comparison signal, and for compare first sampling unit 31 export the first sampled voltage and the second reference voltage V 2, to export the second comparison signal.First arithmetic logic unit 35 is electrically connected on the first comparing unit 33, for exporting the first timing control signal and the 3rd timing control signal according to the first comparison signal, the second comparison signal.First voltage transitions 37 unit is electrically connected on the first arithmetic logic unit 35, for carrying out level conversion to the 3rd timing control signal.Second sampling unit 32 is electrically connected on the second output terminals A C2 of resonance modules 1, and the alternating voltage for the second output terminals A C2 to resonance modules 1 is sampled, to export the second sampled voltage.Second comparing unit 34 is electrically connected on the second sampling unit 32, second comparing unit 34 is for comparing the second sampled voltage and the first reference voltage V 1, to export the 3rd comparison signal, and for comparing the second sampled voltage and the second reference voltage V 2, to export the 4th comparison signal.Second arithmetic logic unit 36 is electrically connected on the second comparing unit 34, for exporting the second timing control signal and the 4th timing control signal according to the 3rd comparison signal, the 4th comparison signal.Second voltage conversion unit 38 is electrically connected on the second arithmetic logic unit 36, for carrying out level conversion to the 4th timing control signal.
First sampling unit 31 comprises the first resistance R1, the 5th NMOS tube HVN1 and the second resistance R2.One end of first resistance R1 is electrically connected on the first output terminals A C1 of resonance modules 1, the other end of the first resistance R1 is electrically connected on the drain electrode of the 5th NMOS tube HVN1, the source electrode of the 5th NMOS tube HVN1 is electrically connected on one end and first comparing unit 33 of the second resistance R2, the grid of the 5th NMOS tube HVN1 is electrically connected on the internal electric source of control module 3, the other end ground connection of the second resistance R2.Second sampling unit 32 comprises the 3rd resistance R3, the 6th NMOS tube HVN2 and the 4th resistance R4, one end of 3rd resistance R3 is electrically connected on the second output terminals A C2 of resonance modules 1, the other end of the 3rd resistance R3 is electrically connected on the drain electrode of the 6th NMOS tube HVN2, the source electrode of the 6th NMOS tube HVN2 is electrically connected on one end and second comparing unit 34 of the 4th resistance R4, the grid of the 6th NMOS tube HVN2 is electrically connected on the internal electric source of control module 3, the other end ground connection of the 4th resistance R4.First comparing unit 33 comprises the first hysteresis comparator HYS1, second hysteresis comparator HYS2, first inverter and the second inverter, the positive input of the first hysteresis comparator HYS1 is electrically connected on one end of the second resistance R2, the reverse input end of the first hysteresis comparator HYS1 is electrically connected on the first reference voltage V 1, the output of the first hysteresis comparator HYS1 is electrically connected on the input of the first inverter, the output of the first inverter is electrically connected on the first arithmetic logic unit 35, the reverse input end of the second hysteresis comparator HYS2 is electrically connected on one end of the second resistance R2, the positive input of the second hysteresis comparator HYS2 is electrically connected on the second reference voltage V 2, the output of the second hysteresis comparator HYS2 is electrically connected on the input of the second inverter, the output of the second inverter is electrically connected on the first arithmetic logic unit 35.Second comparing unit 34 comprises the 3rd hysteresis comparator HYS3, the 4th hysteresis comparator HYS4, the 3rd inverter and the 4th inverter.The positive input of the 3rd hysteresis comparator HYS3 is electrically connected on one end of the 4th resistance R4, the reverse input end of the 3rd hysteresis comparator HYS3 is electrically connected on the first reference voltage V 1, the output of the 3rd hysteresis comparator HYS3 is electrically connected on the input of the 3rd inverter, the output of the 3rd inverter is electrically connected on the second arithmetic logic unit 36, the reverse input end of the 4th hysteresis comparator HYS4 is electrically connected on one end of the 4th resistance R4, the positive input of the 4th hysteresis comparator HYS4 is electrically connected on the second reference voltage V 2, the output of the 4th hysteresis comparator HYS4 is electrically connected on the input of the 4th inverter, the output of the 4th inverter is electrically connected on the second arithmetic logic unit 36.In the present embodiment, the first resistance R1, the 3rd resistance R3 can be ESD (Electro-Staticdischarge, Electro-static Driven Comb) resistance, and the second resistance R2, the 4th resistance R4 are weak pull-down resistance.5th NMOS tube HVN1, the 6th NMOS tube HVN2 are high pressure NMOS pipe.
Control module 3 comprises and also comprises enable unit 39, enable unit 39 is electrically connected on the first arithmetic logic unit 35 and the second arithmetic logic unit 36, enable unit 39 is for exporting the first enable signal or the second enable signal, so that alternately control first arithmetic logic unit 35 and the second arithmetic logic unit 36 work, thus realize as the second NMOS tube Q2 and the 4th NMOS tube Q4 conducting, the first NMOS tube Q1 and the 3rd NMOS tube Q3 is in cut-off state; When the first NMOS tube Q1 and the 3rd NMOS tube Q3 is in conducting state, the second NMOS tube Q2 and the 4th NMOS tube Q4 is in cut-off state, so just can effectively avoid NMOS tube Q1, Q2, Q3, Q4 open simultaneously, cause rectifier bridge short circuit, burn metal-oxide-semiconductor.In like manner, the control principle of the first NMOS tube Q1 in Fig. 5, the second NMOS tube Q2, the first PMOS Q5 and the second PMOS Q6 is also substantially similar.
Carry out citing to the circuit theory of control module in an embodiment of the present invention 3 below to describe, be described for the circuit module that the first sampling unit 31, first comparing unit 33, first arithmetic logic unit 35 and the first voltage conversion unit 37 are formed.Suppose that the initial state of circuit is the first NMOS tube Q1, the second NMOS tube Q2, the 3rd NMOS tube Q3, the 4th NMOS tube Q4 Close All.When the first output terminals A C1 is low, time the second output terminals A C2 is high, electric current can be charged to filter capacitor by the parasitic body diode of the first NMOS tube Q1 and the 3rd NMOS tube Q3.Now the voltage of the first output terminals A C1 is approximately the pressure drop of a diode, approximately-0.7V, set the comparative voltage V1=-0.2V ~-0.3V of the first hysteresis comparator HYS1, so the first hysteresis comparator HYS1 will export high level, after the first inverter, become low level.First logical operation module 35 detect that the first inverter exports low level after, lock this state, the first timing control signal and the 3rd timing control signal uprised, the first NMOS tube Q1 and the 3rd NMOS tube Q3 conducting simultaneously.Now the voltage of the first output terminals A C1 is approximately Vac1=-Iin*Rdsq1, can be much little than the pressure drop of diode current flow.When input current Iin slowly diminishes, the negative voltage of the first output terminals A C1 also can slowly diminish, and when supposing Iin=10mA here, Vac1=-Iin*Rdsq1, this magnitude of voltage is as the cut-ff voltage of the first NMOS tube Q1 and the 3rd NMOS tube Q3.As Iin<10mA, the second hysteresis comparator HYS2 exports high level, becomes low level through the second inverter.After first logical operation module 35 detects the low level that the second inverter exports, lock this state, simultaneously the first timing control signal and the 3rd timing control signal step-down, first NMOS tube Q1 and the 3rd NMOS tube Q3 ends, after this remaining small area analysis is by the body diode afterflow by the first NMOS tube Q1 and the 3rd NMOS tube Q3 parasitism, charges to filter capacitor.Next cycle, the first output terminals A C1 is high, and the second output terminals A C2 is low, opens or end the second NMOS tube Q2 and the 4th NMOS tube Q4 according to substantially identical principle.
It should be noted that, rectification module 2, control module 3 and driver module 4 can be integrated in BUCK chip or in LDO chip, can improve wireless receiving circuit integrated level like this, and wiring is simple, reduces production cost simultaneously.Therefore, also describe a kind of wireless energy receiving system 100 in an embodiment of the present invention, comprise resonance modules 1 and voltage conversion chip 6, voltage conversion chip 6 can be the chip of the voltage conversion function such as BUCK chip or LDO chip.Resonance modules 1 is for receiving wireless energy and converting received wireless energy to ac voltage signal.Voltage conversion chip 6 is electrically connected on resonance modules 1, and voltage conversion chip 6 inside comprises rectification unit, control unit and driver element.Rectification unit comprises multiple field effect transistor, carries out rectification for the ac voltage signal exported resonance modules 1.Control unit, for exporting multiple timing control signal, controls multiple field effect transistor with one_to_one corresponding.Driver element is used for amplifying multiple timing control signal, to control the on off state of the plurality of field effect transistor.In the present embodiment, wireless energy receiving system 100 can be realized by certain integrated technique, and its principle is identical with above-mentioned wireless energy receiving system principle, does not repeat them here.
Figure 8 shows that the key node oscillogram in the wireless energy receiving system circuit diagram shown in Fig. 4.Vac1 and Vac2 is the voltage waveform of the first output terminals A C1 and the second output terminals A C2 2 respectively, and they are that phase place is contrary, the alternating voltage that amplitude is identical; Iac1 and Iac2 is the current waveform that the first output terminals A C1 and the second output terminals A C2 2 flow out, and they are that phase place is contrary, the alternating current that amplitude is identical.VRECT is the direct voltage after the first output terminals A C1 and the second output terminals A C2 full-bridge rectification.When there is negative voltage in the first output terminals A C1, just have negative current and flow through the first NMOS tube Q1, when detecting that Vac1 is greater than set point, there is a high level narrow spaces in the first inverter, trigger the first timing control signal to uprise, 3rd timing control signal also uprises, then this state is locked, until Iac1 electric current is reduced to set point, there is a high level narrow spaces in the second inverter, trigger the first timing control signal step-down, the 3rd timing control signal also step-down, then this state is locked.Afterwards, the first output terminals A C1 becomes positive voltage, and the second output terminals A C2 becomes negative voltage.After experience one section of Dead Time Toverlap, then start the negative voltage detecting the second output terminals A C2.When there is negative pressure in the second output terminals A C2, just have negative current and flow through the second NMOS tube Q2, when detecting that Vac2 is greater than set point, there is a high level narrow spaces in the 3rd inverter, trigger the second timing control signal to uprise, 4th timing control signal also uprises, and then this state is locked, until Iac2 electric current is reduced to set point, there is a high level narrow spaces in the 4th inverter, trigger the second timing control signal step-down, the 4th timing control signal also step-down, then this state is locked.So, the above-mentioned action of continuous repetitive cycling of each cycle.
In sum, wireless energy receiving system provided by the invention, four high-voltage power field effect transistor are adopted to carry out full-bridge rectification to the alternating voltage after the wireless energy conversion received, suitable technique can be adopted simultaneously, be integrated in converter chip, not only effectively improve the conversion efficiency of rectifier bridge, also improve the integrated level of chip, reduce production cost simultaneously.
The above, for the person of ordinary skill of the art, can make other various corresponding change and distortion according to technical scheme of the present invention and technical conceive, and all these change and be out of shape the protection range that all should belong to the claims in the present invention.
Claims (10)
1. a wireless energy receiving system, for wireless charging receiving terminal, is characterized in that, comprising:
Resonance modules, for receiving wireless energy and converting received wireless energy to ac voltage signal;
Rectification module, is electrically connected on described resonance modules, comprises multiple field effect transistor, for carrying out rectification to described ac voltage signal;
Control module, is electrically connected on described rectification module, for exporting multiple timing control signal, controls described multiple field effect transistor with one_to_one corresponding; And
Driver module, is electrically connected on described rectification module and described control module, for amplifying described multiple timing control signal, to control the on off state of described multiple field effect transistor.
2. wireless energy receiving system as claimed in claim 1, is characterized in that, also comprise filtration module, be electrically connected on described rectification module, for carrying out filtering to the ac voltage signal after rectification.
3. wireless energy receiving system as claimed in claim 1, it is characterized in that, described rectification module comprises the first NMOS tube, second NMOS tube, 3rd NMOS tube and the 4th NMOS tube, the drain electrode of described first NMOS tube is electrically connected on the first output of described resonance modules, the source ground of described first NMOS tube, the grid of described first NMOS tube is electrically connected on described driver module, the drain electrode of described second NMOS tube is electrically connected on the second output of described resonance modules, the source ground of described second NMOS tube, the grid of described second NMOS tube is electrically connected on described driver module, the drain electrode of described 3rd NMOS tube is for exporting the alternating voltage after described rectification, the source electrode of described 3rd NMOS tube is electrically connected on the drain electrode of described second NMOS tube and the second output of described resonance modules, the grid of described 3rd NMOS tube is electrically connected on described driver module, the drain electrode of described 4th NMOS tube is electrically connected on the drain electrode of described 3rd NMOS tube, the source electrode of described 4th NMOS tube is electrically connected on the drain electrode of described first NMOS tube and the first output of described resonance modules, the grid of described 4th NMOS tube is electrically connected on described driver module.
4. wireless energy receiving system as claimed in claim 3, it is characterized in that, described rectification module also comprises the first electric capacity, second electric capacity, first diode and the second diode, one end of described first electric capacity is electrically connected on the first output of described resonance modules, the other end of described first electric capacity is electrically connected on the negative pole of described driver module and described first diode, the positive pole of described first diode is electrically connected on described driver module and the first reference voltage, one end of described second electric capacity is electrically connected on the second output of described resonance modules, the other end of described second electric capacity is electrically connected on the negative pole of described driver module and described second diode, the positive pole of described second diode is electrically connected on described driver module and described first reference voltage.
5. wireless energy receiving system as claimed in claim 1, it is characterized in that, described rectification module comprises the first NMOS tube, second NMOS tube, first PMOS and the second PMOS, the drain electrode of described first NMOS tube is electrically connected on the first output of described resonance modules, the source ground of described first NMOS tube, the grid of described first NMOS tube is electrically connected on described driver module, the drain electrode of described second NMOS tube is electrically connected on the second output of described resonance modules, the source ground of described second NMOS tube, the grid of described second NMOS tube is electrically connected on described driver module, the drain electrode of described first PMOS is electrically connected on the drain electrode of described second NMOS tube and the second output of described resonance modules, the source electrode of described first PMOS is for exporting the alternating voltage after described rectification, the grid of described first PMOS is electrically connected on described driver module, the drain electrode of described second PMOS is electrically connected on the drain electrode of described first NMOS tube and the first output of described resonance modules, the source electrode of described second PMOS is electrically connected on the source electrode of described first PMOS, the grid of described second PMOS is electrically connected on described driver module.
6. wireless energy receiving system as claimed in claim 1, it is characterized in that, described control module comprises:
First sampling unit, is electrically connected on the first output of described resonance modules, and the alternating voltage for the first output to described resonance modules is sampled, to export the first sampled voltage;
First comparing unit, is electrically connected on described first sampling unit, for more described first sampled voltage and the first reference voltage, to export the first comparison signal, and for more described first sampled voltage and the second reference voltage, to export the second comparison signal;
First arithmetic logic unit, is electrically connected on described first comparing unit, for exporting the first timing control signal and the 3rd timing control signal according to described first comparison signal, described second comparison signal;
First voltage conversion unit, is electrically connected on described first arithmetic logic unit, for carrying out level conversion to described 3rd timing control signal;
Second sampling unit, is electrically connected on the second output of described resonance modules, and the alternating voltage for the second output to described resonance modules is sampled, to export the second sampled voltage;
Second comparing unit, be electrically connected on described second sampling unit, for more described second sampled voltage and described first reference voltage, to export the 3rd comparison signal, and for more described second sampled voltage and described second reference voltage, to export the 4th comparison signal;
Second arithmetic logic unit, is electrically connected on described second comparing unit, for exporting the second timing control signal and the 4th timing control signal according to described 3rd comparison signal, described 4th comparison signal; And
Second voltage conversion unit, is electrically connected on described second arithmetic logic unit, for carrying out level conversion to described 4th timing control signal.
7. wireless energy receiving system as claimed in claim 6, it is characterized in that, described first sampling unit comprises the first resistance, the 5th NMOS tube and the second resistance, one end of described first resistance is electrically connected on the first output of described resonance modules, the other end of described first resistance is electrically connected on the drain electrode of described 5th NMOS tube, the source electrode of described 5th NMOS tube is electrically connected on one end of described second resistance and described first comparing unit, the grid of described 5th NMOS tube is electrically connected on the internal electric source of described control module, the other end ground connection of described second resistance, described second sampling unit comprises the 3rd resistance, the 6th NMOS tube and the 4th resistance, one end of described 3rd resistance is electrically connected on the second output of described resonance modules, the other end of described 3rd resistance is electrically connected on the drain electrode of described 6th NMOS tube, the source electrode of described 6th NMOS tube is electrically connected on one end of described 4th resistance and described second comparing unit, the grid of described 6th NMOS tube is electrically connected on the internal electric source of described control module, the other end ground connection of described 4th resistance, described first comparing unit comprises the first hysteresis comparator, second hysteresis comparator, first inverter and the second inverter, the positive input of described first hysteresis comparator is electrically connected on one end of described second resistance, the reverse input end of described first hysteresis comparator is electrically connected on described first reference voltage, the output of described first hysteresis comparator is electrically connected on the input of described first inverter, the output of described first inverter is electrically connected on described first arithmetic logic unit, the reverse input end of described second hysteresis comparator is electrically connected on one end of described second resistance, the positive input of described second hysteresis comparator is electrically connected on described second reference voltage, the output of described second hysteresis comparator is electrically connected on the input of described second inverter, the output of described second inverter is electrically connected on described first arithmetic logic unit, described second comparing unit comprises the 3rd hysteresis comparator, 4th hysteresis comparator, 3rd inverter and the 4th inverter, the positive input of described 3rd hysteresis comparator is electrically connected on one end of described 4th resistance, the reverse input end of described 3rd hysteresis comparator is electrically connected on described first reference voltage, the output of described 3rd hysteresis comparator is electrically connected on the input of described 3rd inverter, the output of described 3rd inverter is electrically connected on described second arithmetic logic unit, the reverse input end of described 4th hysteresis comparator is electrically connected on one end of described 4th resistance, the positive input of described 4th hysteresis comparator is electrically connected on described second reference voltage, the output of described 4th hysteresis comparator is electrically connected on the input of described 4th inverter, the output of described 4th inverter is electrically connected on described second arithmetic logic unit.
8. wireless energy receiving system as claimed in claim 6, it is characterized in that, described control module comprises and also comprises enable unit, be electrically connected on described first arithmetic logic unit and described second arithmetic logic unit, for exporting the first enable signal or the second enable signal, alternately to control described first arithmetic logic unit and described second arithmetic logic unit work.
9. a wireless energy receiving system, for wireless charging receiving terminal, is characterized in that, comprising:
Resonance modules, for receiving wireless energy and converting received wireless energy to ac voltage signal; And
Voltage conversion chip, is electrically connected on described resonance modules, and described voltage conversion chip comprises:
Rectification module, comprises multiple field effect transistor, for carrying out rectification to described ac voltage signal;
Control module, for exporting multiple timing control signal, controls described multiple field effect transistor with one_to_one corresponding; And
Driver module, for amplifying described multiple timing control signal, to control the on off state of described multiple field effect transistor.
10. wireless energy receiving system as claimed in claim 9, is characterized in that, also comprise filtration module, be electrically connected on described voltage conversion chip, for carrying out filtering to the ac voltage signal after rectification.
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| CN109861566A (en) * | 2019-03-28 | 2019-06-07 | 南京和若源电气有限公司 | A kind of circuit of synchronous rectification, synchronous rectification method and wireless charging device |
| CN111756098A (en) * | 2019-03-28 | 2020-10-09 | 拉碧斯半导体株式会社 | Power receiving device |
| CN113193753A (en) * | 2020-01-13 | 2021-07-30 | 北京新能源汽车股份有限公司 | Synchronous rectifying device and receiving end module of wireless charging system |
| CN118264135A (en) * | 2024-04-24 | 2024-06-28 | 四川杰莱美科技有限公司 | Rectifying circuit based on circuit signal control and electronic device |
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