CN105337483A

CN105337483A - Device for preventing current from flowing backwards

Info

Publication number: CN105337483A
Application number: CN201410386535.7A
Authority: CN
Inventors: 宗节保; 曹青; 欧阳艳红; 彭轶; 黄建华; 张金涛; 刘飞云
Original assignee: ZTE Corp
Current assignee: ZTE Corp
Priority date: 2014-08-07
Filing date: 2014-08-07
Publication date: 2016-02-17
Also published as: WO2016019642A1

Abstract

The invention provides a device for preventing current from flowing backwards. The device comprises a sampling circuit, a comparison circuit, an isolation circuit and a driving circuit, wherein the sampling circuit is connected with a power input end of an isolation power circuit, the comparison circuit is connected with the sampling circuit, the isolation circuit is connected with the comparison circuit, the driving circuit is connected with the isolation circuit, the sampling circuit is used for sampling a power input voltage of the isolation power circuit in real time and outputting a voltage signal obtained through sampling to the comparison circuit, the isolation power circuit is provided with a plurality of synchronous rectification metal-oxide-semiconductor (MOS) tubes, the comparison circuit is used for comparing the voltage signal with a predetermined reference voltage and outputting a control signal according to a comparison result, the isolation circuit is sued for receiving the control signal of the comparison circuit and transmitting the control signal to the driving circuit, and the driving circuit is used for controlling the switch-on or switch-off of the plurality of synchronous rectification MOS tubes of the isolation power circuit and is further connected with the isolation power circuit. Therefore, reverse current accumulation of an inductor is prevented to cause avalanche breakdown and damage of the MOS tubes.

Description

A kind of device preventing current flowing backwards

Technical field

The present invention relates to electric and electronic technical field, particularly relate to a kind of device preventing current flowing backwards.

Background technology

Along with the development of the technology such as computer, communication and integrated circuit, also more and more higher to the requirement of Switching Power Supply, high power density, small size and high efficiency are current development trends.In order to reach this target of high conversion efficiency, existing Switching Power Supply generally adopts synchronous rectification, but problem also produces thereupon.In Switching Power Supply, when inputting quick power down, output fills with energy toward input is counter, outputting inductance produces and continues cumulative negative current, now synchronous rectifier turns off, and the reverse current on inductance, owing to not having continuous current circuit, directly charges to the parasitic capacitance of field effect transistor metal-oxide-semiconductor, when anti-filling energy is enough large time, can there is avalanche breakdown and damage in metal-oxide-semiconductor.At present, a lot of Switching Power Supply utilizes input undervoltage resist technology to solve this problem, but the method response speed is slow, and the anti-filling duration is large compared with the long inductance reverse current that causes, thus damages synchronous rectifier.In Switching Power Supply, the unusual switch machine of power supply, and thunderbolt, surge etc. all likely cause Switching Power Supply to input quick power down.

In sum, Problems existing is that Switching Power Supply input undervoltage is protected for the quick power down low-response of input, and inductance accumulation backward energy without bleed-off circuit, thus damages synchronous rectifier.

Summary of the invention

The object of the present invention is to provide a kind of device preventing current flowing backwards, solve the protection of Switching Power Supply input undervoltage for the quick power down low-response of input, inductance accumulation backward energy without bleed-off circuit, thus damages the problem of synchronous rectifier.

In order to solve the problems of the technologies described above, a kind of device preventing current flowing backwards that the embodiment of the present invention provides, wherein, comprising: the sample circuit be connected with the power input of insulating power supply circuit, the comparison circuit be connected with described sample circuit, the buffer circuit be connected with described comparison circuit and the drive circuit be connected with described buffer circuit; Wherein

Described sample circuit, for the power input voltage of insulating power supply circuit described in real-time sampling, and the voltage signal obtained of sampling is exported to described comparison circuit, wherein said insulating power supply circuit has multiple devices;

Described comparison circuit, for more described voltage signal and predetermined reference voltage, and exports a control signal according to comparative result;

Described buffer circuit, for receiving the control signal of described comparison circuit, and passes to described drive circuit;

Described drive circuit, for controlling opening or turning off of described multiple devices of described insulating power supply circuit according to described control signal, described drive circuit is also connected to described insulating power supply circuit.

Further, described sample circuit comprises:

First resistance R2, the second resistance R3 and the first electric capacity C2;

Wherein, one end of described second resistance R3 is connected to the input of described insulating power supply circuit, one end of described first resistance R2 is connected with one end of described first electric capacity C2, the other end of described second resistance R3 is connected to one end of described first resistance R2, and the other end of described second resistance R3 is also connected to an input of described sample circuit;

The other end of described first resistance R2 and the other end grounding connection of described first electric capacity C2.

Further, described comparison circuit comprises: the comparator D1 with positive input terminal, negative input end and output, the other end of described second resistance R3 is connected to the negative input end of described comparator D1, described predetermined reference voltage inputs the positive input terminal of described comparator D1, the output of described comparator D1 is connected to described buffer circuit, exports control signal described in.

Further, described buffer circuit comprises: have the first former limit and the optical coupler of the first secondary, the first former limit circuit be connected with the first former limit of described optical coupler and the first secondary circuit be connected with the first secondary of described optical coupler;

Wherein said first former limit circuit comprises: the 3rd resistance R4, the first diode VD1, the 4th resistance R5, the second electric capacity C3, the first MOS transistor VT9, the 5th resistance R6 and the 6th resistance R7;

Wherein, one end of described 3rd resistance R4 is connected with the output of described comparator D1, and the other end of described 3rd resistance R4 is connected with the input of described first diode VD1;

One end of described 4th resistance R5 is connected with one end of described second electric capacity C3, and the output of described first diode VD1 is connected to one end of described 4th resistance R5, the other end of described 4th resistance R5 and the other end grounding connection of described second electric capacity C3;

One end of described 4th resistance R5 is also connected to the grid of described first MOS transistor VT9;

The source ground of described first MOS transistor VT9 is connected to the other end of described second electric capacity C3;

The drain electrode of described first MOS transistor VT9 is connected to the output on the first former limit of described optical coupler;

One end of described 5th resistance R6 is connected with one end of the 6th resistance R7, and one end of described 5th resistance R6 is also connected to internal power source voltage VCC, the other end of described 5th resistance R6 is connected with the other end of the 6th resistance R7, and the other end of described 5th resistance R6 is also connected to the input on the first former limit of described optical coupler;

Wherein said first secondary circuit comprises: the 7th resistance R8, the 8th resistance R9, the 9th resistance R10, the 3rd electric capacity C4, the first triode VT10, the 4th electric capacity C5, the tenth resistance R11;

Wherein, a termination supply voltage VDD of described 7th resistance R8, the described other end of the 7th resistance R8 is connected with the input of the first secondary of described optical coupler;

One end of described 8th resistance R9 is connected to the output of the first secondary of described optical coupler;

One end of described 3rd electric capacity C4 is also connected to the output of the first secondary of described optical coupler;

The other end of described 8th resistance R9 is connected with one end of described 9th resistance R10, the other end of described 9th resistance R10 and the other end grounding connection of described 3rd electric capacity C4;

The other end of described 8th resistance R9 is also connected to the base stage of described first triode VT10, and the grounded emitter of described first triode VT10 connects;

Between the collector electrode that described 4th electric capacity C5 and described tenth resistance R11 is parallel to described first triode VT10 and ground, one end of described 4th electric capacity C5 is connected with one end of described tenth resistance R11, the collector electrode of described first triode VT10 is connected to one end of described 4th electric capacity C5, the other end of described 4th electric capacity C5 and the other end grounding connection of described tenth resistance R11;

The collector electrode of described first triode VT10 is also connected to the control signal input of described drive circuit.

Further, the described first former limit of described optical coupler is described first secondary of light-emitting diode and described optical coupler is phototriode.

Further, described drive circuit comprises: the driver D3 with control signal input and drive singal output, wherein said drive singal output is connected to described insulating power supply circuit, and described drive singal output comprises: the first drive end DRIVE1 and the second drive end DRIVE2.

Further, described insulating power supply circuit comprises: the transformer with the second former limit and the second secondary;

The the second former limit circuit be connected with described second former limit, and the described power input of described second former limit circuit is connected to described sample circuit;

The second secondary circuit be connected with described second secondary, and the grid of the devices of described second secondary circuit, be connected with the described drive singal output of described driver.

Further, described second former limit circuit comprises: the second MOS transistor VT21, the 3rd MOS transistor VT22, the 4th MOS transistor VT23 and the 5th MOS transistor VT24;

Wherein said second MOS transistor VT21, described 3rd MOS transistor VT22, described 4th MOS transistor VT23 and described 5th MOS transistor VT24 form full-bridge topologies, the grid of described second MOS transistor VT21 and the grid of described 5th MOS transistor VT24, all with one end sub-connection of extraneous driving chip; The grid of described 3rd MOS transistor VT22 and the grid of described 4th MOS transistor VT23, be all connected with the another terminal of extraneous driving chip;

The drain electrode of described second MOS transistor VT21 is connected to the positive pole of described power input voltage;

The source electrode of described second MOS transistor VT21 is connected to the drain electrode of described 4th MOS transistor VT23;

The drain electrode of described 4th MOS transistor VT23 is also connected to the one end on the second former limit of the first transformer T21;

The source electrode of described 4th MOS transistor VT23 is connected to the negative pole of described power input voltage;

The source electrode of described 4th MOS transistor VT23 is also connected on the source electrode of described 5th MOS transistor VT24;

The drain electrode of described 5th MOS transistor VT24 is connected to the other end on the second former limit of described first transformer T21;

The drain electrode of described 5th MOS transistor VT24 is also connected to the source electrode of described 3rd MOS transistor VT22;

The drain electrode of described 3rd MOS transistor VT22 is connected to the drain electrode of described second MOS transistor VT21;

Described second secondary circuit comprises:

6th MOS transistor VT25, the 7th MOS transistor VT26, the 8th MOS transistor VT27, the 9th MOS transistor VT28, the 11 resistance R21, the first inductance L 21 and the 5th electric capacity C21;

Wherein said 6th MOS transistor VT25, described 7th MOS transistor VT26, described 8th MOS transistor VT27 and described 9th MOS transistor VT28 form full-bridge topologies, and the described first drive end DRIVE1 of the grid of described 6th MOS transistor VT25 and the grid of described 9th MOS transistor VT28 and described driver or described second drive end DRIVE2 selects a drive singal output and is connected; Grid and the grid of described 7th MOS transistor VT26 of described 8th MOS transistor VT27 are connected with another drive singal output of described driver;

The drain electrode of described 7th MOS transistor VT26 is connected on the source electrode of described 6th MOS transistor VT25;

The drain electrode of described 6th MOS transistor VT25 is connected to the drain electrode of described 8th MOS transistor VT27, and the drain electrode of described 8th MOS transistor VT27 is also connected on one end of described first inductance L 21;

The other end of described first inductance L 21 is connected to one end of described 5th electric capacity C21, described 5th electric capacity C21 is in parallel with described 11 resistance R21, one end of described 5th electric capacity C21 is connected with one end of described 11 resistance R21, the other end of described 11 resistance R21 is connected with the other end of described 5th electric capacity C21, and the other end of described 5th electric capacity C21 is also connected on the source electrode of described 9th MOS transistor VT28, the two ends output voltage of described 11 resistance R21;

The drain electrode of described 9th MOS transistor VT28 is connected to the source electrode of described 8th MOS transistor VT27;

The drain electrode of described 9th MOS transistor VT28 is also connected to one end of second secondary of described first transformer T21; The source electrode of described 9th MOS transistor VT28 is connected on the source electrode of described 7th MOS transistor VT26;

The drain electrode of described 7th MOS transistor VT26 is also connected to the other end of second secondary of described first transformer T21.

Further, described second former limit circuit comprises: the tenth MOS transistor VT31, the 11 MOS transistor VT32, the 6th electric capacity C31 and the 7th electric capacity C32;

Wherein said tenth MOS transistor VT31, described 11 MOS transistor VT32, described 6th electric capacity C31 and described 7th electric capacity C32 form half-bridge topology, the grid of described tenth MOS transistor VT31 is connected with the another terminal of extraneous driving chip with one end sub-connection of extraneous driving chip, the grid of described 11 MOS transistor VT32;

Described 6th electric capacity C31 one end is connected with one end of described 7th electric capacity C32, and described 6th electric capacity C31 one end is also connected to the one end on the second former limit of the second transformer T31, the other end of described 6th electric capacity C31 is connected to the positive pole of described power input voltage, and the other end of described 7th electric capacity C32 is connected to the negative pole of described power input voltage;

The drain electrode of described tenth MOS transistor VT31 is connected to described 6th electric capacity C31 one end, the source electrode of described tenth MOS transistor VT31 is connected to the drain electrode of described 11 MOS transistor VT32, the drain electrode of described 11 MOS transistor VT32 is also connected to the other end on the second former limit of described second transformer T31, and the source electrode of described 11 MOS transistor VT32 is connected to the other end of described 7th electric capacity C32;

Described second secondary circuit comprises: the 12 MOS transistor VT33, the 13 MOS transistor VT34, the 8th electric capacity C33, the 12 resistance R31 and the second inductance L 31;

Wherein, the grid of described 13 MOS transistor VT34 is connected to the described first drive end DRIVE1 of described driver or described second drive end DRIVE2 and selects a drive singal output and connect;

The grid of described 12 MOS transistor VT33 is connected to another drive singal output of described driver;

The source electrode of described 12 MOS transistor VT33 is connected on the source electrode of described 13 MOS transistor VT34, and the drain electrode of described 12 MOS transistor VT33 is connected to one end of second secondary of the second transformer T31;

The drain electrode of described 13 MOS transistor VT34 is connected to the other end of second secondary of described second transformer T31, the source electrode of described 13 MOS transistor VT34 is connected to described 8th electric capacity C33 one end, described 8th electric capacity C33 one end is also connected to described 12 resistance R31 one end, at the two ends output voltage of described 12 resistance R31;

Described 12 resistance R31 and described 8th electric capacity C33 is in parallel, and the other end of described 8th electric capacity C33 and the other end of described 12 resistance R31 are connected to one end of described second inductance L 31;

The other end of described second inductance L 31 is connected on second secondary of described second transformer T31.

Further, described second former limit circuit comprises:

14 MOS transistor VT41, the 15 MOS transistor VT42, the 9th electric capacity C41 and the tenth electric capacity C42;

Wherein, described 14 MOS transistor VT41, described 15 MOS transistor VT42, described 9th electric capacity C41 and described tenth electric capacity C42 form active clamp topological structure, the grid of described 14 MOS transistor VT41 is connected with the another terminal of extraneous driving chip with one end sub-connection of extraneous driving chip, the grid of described 15 MOS transistor VT42;

One end of described 9th electric capacity C41 is connected to the positive pole of described power input voltage, and is connected to the one end on the second former limit of the 3rd transformer T41;

The described 9th electric capacity C41 other end is connected to the negative pole of described power input voltage;

The other end of described 9th electric capacity C41 is also connected to the source electrode of described 14 MOS transistor VT41;

The drain electrode of described 14 MOS transistor VT41 is connected to one end of described tenth electric capacity C42, and the other end of described tenth electric capacity C42 is connected to the other end on the second former limit of described 3rd transformer T41;

The drain electrode of described 15 MOS transistor VT42 is also connected to the other end on the second former limit of described 3rd transformer T41;

The source electrode of described 15 MOS transistor VT42 is also connected on the source electrode of described 14 MOS transistor VT41;

Described second secondary circuit comprises: the 16 MOS transistor VT43, the 17 MOS transistor VT44, the 11 electric capacity C43, the 13 resistance R41 and the 3rd inductance L 41;

The grid of described 16 MOS transistor VT43 is connected to the described first drive end DRIVE1 of the described drive singal output of described driver or described second drive end DRIVE2 and selects a drive singal output and connect;

The grid of described 17 MOS transistor VT44 is connected to another drive singal output of described driver;

The source electrode of described 16 MOS transistor VT43 is connected to one end of second secondary of described 3rd transformer T41, and the drain electrode of described 16 MOS transistor VT43 is connected to one end of described 3rd inductance L 41;

The other end of described 3rd inductance L 41 is connected with one end of described 13 resistance R41, described 13 resistance R41 and described 11 electric capacity C43 is in parallel, described 13 resistance R41 one end is also connected with one end of described 11 electric capacity C43, the other end of described 13 resistance R41 is also connected with the other end of described 11 electric capacity C43, and the other end of described 11 electric capacity C43 is connected on the source electrode of described 17 MOS transistor VT44, the two ends output voltage of described 13 resistance R41;

The source electrode of described 17 MOS transistor VT44 is connected to the other end of second secondary of described 3rd transformer T41, and the drain electrode of described 17 MOS transistor VT44 is also connected to one end of described 3rd inductance L 41.

Further, described second former limit circuit comprises: the 18 MOS transistor VT51, the 19 MOS transistor VT52, the 12 electric capacity C51 and the 13 electric capacity C52;

Wherein, described 18 MOS transistor VT51, described 19 MOS transistor VT52, described 12 electric capacity C51 and described 13 electric capacity C52 form active clamp circuit, the grid of described 18 MOS transistor VT51 is connected with the another terminal of extraneous driving chip with one end sub-connection of extraneous driving chip, the grid of described 19 MOS transistor VT52;

Described 12 electric capacity C51 one end is connected to the positive pole of described power input voltage;

The other end of described 12 electric capacity C51 is connected to the negative pole of described power input voltage;

One end of described 13 electric capacity C52 is connected to one end of described 12 electric capacity C51, and one end of described 13 electric capacity C52 is also connected to the one end on the second former limit of the 4th transformer T51;

The other end of described 13 electric capacity C52 is connected to the drain electrode of described 18 MOS transistor VT51;

The source electrode of described 18 MOS transistor VT51 is connected to the other end on the second former limit of the 4th transformer T51;

The source electrode of described 18 MOS transistor (VT51) also connects the drain electrode of described 19 MOS transistor VT52;

The source electrode of described 19 MOS transistor VT52 is connected on the described 12 electric capacity C51 other end;

Described second secondary circuit comprises: the 20 MOS transistor VT53, the 21 MOS transistor VT54, the 14 electric capacity C53, the 14 resistance R51 and the 4th inductance L 51;

The grid of described 20 MOS transistor VT53 is connected to the described first drive end DRIVE1 of the described drive singal output of described driver or described second drive end DRIVE2 and selects a drive singal output and connect;

The grid of described 21 MOS transistor VT54 is connected to another drive singal output of described driver;

The source electrode of described 20 MOS transistor VT53 is connected to one end of second secondary of described 4th transformer T51, and the drain electrode of described 20 MOS transistor VT53 is connected to one end of described 4th inductance L 51;

The other end of one end of described 4th inductance L 51 is connected with described 14 resistance R51 one end, described 14 resistance R51 and described 14 electric capacity C53 is in parallel, described 14 resistance R51 one end is also connected with one end of described 14 electric capacity C53, the other end of described 14 resistance R51 is also connected with the other end of described 14 electric capacity C53, and the other end of described 14 electric capacity C53 is connected on the source electrode of described 21 MOS transistor VT54, the two ends output voltage of described 14 resistance R51;

The source electrode of described 21 MOS transistor VT54 is connected to the other end of second secondary of described 4th transformer T51, and the drain electrode of described 21 MOS transistor VT54 is also connected to one end of described 4th inductance L 51.

The beneficial effect of technique scheme of the present invention is as follows:

In the solution of the present invention, by the power input voltage of sample circuit input Real-time Collection insulating power supply circuit, output outputs voltage signal to the input of comparison circuit, another input input reference voltage of comparison circuit, output then exports control signal according to comparative result, control signal is delivered to secondary by buffer circuit from former limit, is controlled turning on and off of the devices of insulating power supply circuit by drive circuit.Such sample circuit is to the input voltage real-time sampling of insulating power supply circuit, when the quick power down of input voltage, can react rapidly, comparison circuit exports the secondary devices that control signal turns off insulating power supply circuit fast, thus prevents inductance accumulation reverse current to cause metal-oxide-semiconductor avalanche breakdown damage.

Accompanying drawing explanation

Fig. 1 is that under the quick power down of input of the present invention, circuit diagram is filled with in counnter attack;

Fig. 2 is the circuit theory diagrams of the first embodiment of the present invention;

Fig. 3 is the circuit theory diagrams of the second embodiment of the present invention;

Fig. 4 is the circuit theory diagrams of the third embodiment of the present invention;

Fig. 5 is the circuit theory diagrams of the fourth embodiment of the present invention;

Fig. 6 is the circuit theory diagrams of the fifth embodiment of the present invention;

Fig. 7 is the circuit theory diagrams of the sixth embodiment of the present invention.

Description of reference numerals:

1-sample circuit, 2-comparison circuit, 3-buffer circuit, 4-drive circuit, 5-insulating power supply circuit.

Embodiment

For making the technical problem to be solved in the present invention, technical scheme and advantage clearly, be described in detail below in conjunction with the accompanying drawings and the specific embodiments.

The present invention is directed to the protection of prior art breaker in middle power supply input undervoltage for the quick power down low-response of input, inductance accumulation backward energy damages the problem of synchronous rectifier without bleed-off circuit, a kind of device preventing current flowing backwards is provided, by the input voltage real-time sampling of sample circuit to insulating power supply circuit, when the quick power down of input voltage, can react rapidly, comparison circuit exports the secondary devices that control signal turns off insulating power supply circuit, not only prevent inductance accumulation reverse current and cause metal-oxide-semiconductor avalanche breakdown damage, and be beneficial to the reliability improving product, thus increase competitiveness and the attraction of product.

The device preventing current flowing backwards of the embodiment of the present invention as shown in Figure 1, wherein, comprising: the sample circuit 1 be connected with the power input of insulating power supply circuit 5, the comparison circuit 2 be connected with described sample circuit 1, the buffer circuit 3 be connected with described comparison circuit 2 and the drive circuit 4 be connected with described buffer circuit 3; Wherein

Described sample circuit 1, for the power input voltage of insulating power supply circuit 5 described in real-time sampling, and the voltage signal obtained of sampling is exported to described comparison circuit 2, wherein said insulating power supply circuit 5 has multiple devices;

Described comparison circuit 2, for more described voltage signal and predetermined reference voltage, and exports a control signal according to comparative result;

The device that wherein above-mentioned comparison circuit 2 adopts can be comparator, also can be operational amplifier or also can be rapid computations amplifier; but be not limited only to comparator, operational amplifier or rapid computations amplifier; any circuit that can realize the input voltage vin sampled and predetermined reference voltage Vref compare all belongs to protection scope of the present invention, in this citing that differs.

Wherein above-mentioned predetermined reference voltage Vref is referred to and to be determined by debugging, does not produce magnitude of voltage for the purpose of continuous reverse current or as far as possible little reverse current by inductance.

Described buffer circuit 3, for receiving the control signal of described comparison circuit 2, and passes to described drive circuit 4;

Described drive circuit 4, for controlling opening or turning off of described multiple devices of described insulating power supply circuit 5 according to described control signal, described drive circuit 4 is also connected to described insulating power supply circuit 5.

Wherein above-mentioned buffer circuit 3 adopt device can be optical coupler; or also can be isolator; but be not limited to optical coupler and isolator; anyly can realize device control signal being delivered to secondary from the former limit of buffer circuit 3; all belong to protection scope of the present invention, in this citing that differs.

Wherein above-mentioned insulating power supply circuit 5 comprises and has the synchronous rectification MOS transistor of former limit circuit and the synchronous rectification MOS transistor of secondary circuit.

The real-time sampling circuit 1 of input voltage can by electric resistance partial pressure to input voltage vin real-time sampling, one of them input of comparison circuit 2 is inputed to after capacitor filtering, another input is predetermined reference voltage Vref, comparison circuit 2 can compare the input voltage vin sampled and predetermined reference voltage Vref, output signal is delivered to secondary by buffer circuit 3 from former limit, is controlled turning on and off of the secondary devices of insulating power supply circuit 5 by drive circuit 4.

As shown in Figure 2, the described of the embodiment of the present invention prevents in the device of current flowing backwards, and described sample circuit 1 comprises:

Wherein, one end of described second resistance R3 is connected to the input of described insulating power supply circuit 5, one end of described first resistance R2 is connected with one end of described first electric capacity C2, the other end of described second resistance R3 is connected to one end of described first resistance R2, and the other end of described second resistance R3 is also connected to an input of described sample circuit 1.

As shown in Figure 2, the described of the embodiment of the present invention prevents in the device of current flowing backwards, described comparison circuit 2 comprises: the comparator D1 with positive input terminal, negative input end and output, the other end of described second resistance R3 is connected to the negative input end of described comparator D1, described predetermined reference voltage inputs the positive input terminal of described comparator D1, the output of described comparator D1 is connected to described buffer circuit 3, exports control signal described in.

As shown in Figure 2, the embodiment of the present invention prevent in the device of current flowing backwards, described buffer circuit 3 comprises: have the first former limit and the optical coupler of the first secondary, the first former limit circuit be connected with the first former limit of described optical coupler and the first secondary circuit be connected with the first secondary of described optical coupler;

Wherein described first secondary of above-mentioned optical coupler can be described first former limit be light-emitting diode and described optical coupler is phototriode; Described first secondary of also can be described first former limit be light-emitting diode and described optical coupler is photodiode; certainly only illustrate more than; anyly can realize any device that control signal can be realized to be delivered to from the former limit of buffer circuit 3 secondary; all belong to protection scope of the present invention, in this citing that differs.The described first former limit of the preferred described optical coupler of the embodiment of the present invention is described first secondary of light-emitting diode and described optical coupler is phototriode.

The collector electrode of described first triode VT10 be also connected to described drive circuit control signal input;

The drive singal output that wherein above-mentioned driver D3 exports is connected to described insulating power supply circuit 5, and by least one road drive singal output output drive signal, wherein said driver can have each drive singal output in multi-channel drive signal output can control the required circuit driven, such as shown in Fig. 2, described drive singal output comprises the first drive end and the second drive end, the secondary of described insulating power supply circuit 5 is four MOS transistor, and described four MOS transistor are divided into two groups of conductings, then incite somebody to action wherein one group of MOS transistor, be connected with drive singal output arbitrary in the first drive end or the second drive end, another organizes MOS transistor, is connected with another drive singal output remaining, and the circuit completing drived control connects.

As shown in Figure 2, the embodiment of the present invention prevent in the device of current flowing backwards, described drive circuit 4 comprises: the driver D3 with control signal input and drive singal output, wherein said drive singal output is connected to described insulating power supply circuit 5, and described drive singal output comprises: the first drive end DRIVE1 and the second drive end DRIVE2.

The described of the embodiment of the present invention prevents in the device of current flowing backwards, and described insulating power supply circuit 5 comprises: the transformer with the second former limit and the second secondary;

The the second former limit circuit be connected with described second former limit, and the described power input of described second former limit circuit is connected to described sample circuit 1;

The second secondary circuit be connected with described second secondary, and the grid of multiple metal-oxide-semiconductor circuit of the synchronous rectification of described second secondary circuit, be connected with the described drive singal output of described driver.

As shown in Figure 2, the first embodiment of the present invention prevent in the device of current flowing backwards, described second former limit circuit comprises: described second former limit circuit comprises: the second MOS transistor VT21, the 3rd MOS transistor VT22, the 4th MOS transistor VT23 and the 5th MOS transistor VT24;

Described second secondary circuit comprises:

The circuit of Fig. 2 is that circuit is filled with in counnter attack the present invention described in Fig. 1 inputted under quick power down, be applied in the insulating power supply of former limit full-bridge topologies secondary full-bridge synchronous rectification, comprise synchronous rectifier (the 6th MOS transistor VT25, the 7th MOS transistor VT26, the 8th MOS transistor VT27 and the 9th MOS transistor VT28), the 11 resistance R21, the first inductance L 21 and the 5th electric capacity C21 and counnter attack and fill with circuit.

Specific works principle is be described in detail the circuit working principle of the preferred embodiment of the invention for Fig. 2:

When input voltage vin power down, especially large capacitive load is with, under load output no-load condition, control chip duty ratio can not open the voltage compensating drop, or duty ratio has reached the maximum duty cycle of chip, the now negative current (in Fig. 2 arrow shown in) that produces at metal-oxide-semiconductor freewheeling period of the voltage at outputting inductance two ends, also excitation of having no way under situation is opened on former limit is to forward current, thus when causing next freewheeling period, negative current value on inductance increases, simultaneously along with input voltage declines more, this situation can be more severe, add up down, negative current on inductance can be increasing.In order to suppress this situation, in the present embodiment, real-time sampling circuit 1 is by the first resistance R2 and the second resistance R3 dividing potential drop Gather and input voltage Vin, when lower than predetermined reference voltage Vref, operational amplifier D1 action, export high level signal FS, this signal is by being input to the grid of the first MOS transistor VT9 after the 3rd resistance R4 and the first diode VD1, then the first MOS transistor VT9 conducting, thus isolation optical coupler D2 conducting, export the base stage of high level signal SHUT to the first triode VT10, first triode VT10 conducting, drag down the Enable Pin signal ENABLE of driver D3, this driver output is caused to be turned off to the drive singal first drive end DRIVE1 of secondary and the second drive end DRIVE2, 6th MOS transistor VT25 of secondary devices, 7th MOS transistor VT26, 8th MOS transistor VT27, 9th MOS transistor VT28 turns off, first drive end DRIVE1 of drive singal or the second drive end DRIVE2 terminal are selected the 6th MOS transistor VT25 of a drive singal output and rectification metal-oxide-semiconductor and the 9th MOS transistor VT28 and are connected, another drive singal output is connected with the 7th MOS transistor VT26 and the 8th MOS transistor VT27.Because the point turning off setting just turns off devices when inductance does not produce additional negative current or negative current is less; now less on inductance reverse current energy is weak; be unlikely to cause devices stress to exceed standard; thus reach under input power-down conditions; the object of protection devices, improves the reliability of power supply.

As shown in Figure 3, the second embodiment of the present invention prevent in the device of current flowing backwards, described second former limit circuit comprises: the tenth MOS transistor VT31, the 11 MOS transistor VT32, the 6th electric capacity C31 and the 7th electric capacity C32;

With the difference of the first embodiment be: it is that half-bridge topology secondary adopts in the insulating power supply of all-wave synchronous rectification that the second embodiment is applied to former limit, and the course of work of the course of work and the first embodiment is similar.

As shown in Figure 4, the third embodiment of the present invention prevent in the device of current flowing backwards, described second former limit circuit comprises:

With the difference of the first embodiment be: it is that active clamp topology secondary adopts in the insulating power supply of synchronous rectification that the 3rd embodiment is applied to former limit.

As shown in Figure 5, the fourth embodiment of the present invention prevent in the device of current flowing backwards, described second former limit circuit comprises: the 18 MOS transistor VT51, the 19 MOS transistor VT52, the 12 electric capacity C51 and the 13 electric capacity C52;

With the difference of the 3rd embodiment circuit theory diagrams be: the 4th embodiment clamp capacitor is flyback clamper, and the 3rd embodiment clamp capacitor is boost clamper, and both former limits are all active clamp topology, and secondary circuit is all synchronous rectification.

As shown in Figure 6, the fifth embodiment of the present invention prevent in the device of current flowing backwards, the second former limit circuit of described insulating power supply circuit 5 and the second secondary circuit;

Described second former limit circuit comprises: the 22 MOS transistor VT61, the 23 MOS transistor VT62, the 15 electric capacity C61 and the 16 electric capacity C62;

Wherein said 22 MOS transistor VT61, described 23 MOS transistor VT62, described 15 electric capacity C61 and described 16 electric capacity C62 form half-bridge topology, the grid of described 22 MOS transistor VT61 is connected with the another terminal of extraneous driving chip with one end sub-connection of extraneous driving chip, the grid of described 23 MOS transistor VT62;

Described 15 electric capacity C61 is connected to the positive pole of described power input voltage, the described 15 electric capacity C61 other end is connected to the one end on the second former limit of the 5th transformer T61, and the other end of described 15 electric capacity C61 is connected with one end of described 16 electric capacity C62, the other end of described 16 electric capacity C62 is connected to the negative pole of described power input voltage;

The drain electrode of described 22 MOS transistor VT61 is connected to one end of described 15 electric capacity C61, the source electrode of described 22 MOS transistor VT61 is connected to the drain electrode of described 23 MOS transistor VT62, the drain electrode of described 23 MOS transistor VT62 is also connected to the other end on the second former limit of described 5th transformer T61, and the source electrode of described 23 MOS transistor VT62 is connected to the other end of described 16 electric capacity C62;

Described second secondary circuit comprises: the 24 MOS transistor VT63, the 25 MOS transistor VT64, the 26 MOS transistor VT65, the 27 MOS transistor VT66, the 15 resistance R61, the 5th inductance L the 61 and the 17 electric capacity C63;

Wherein said 24 MOS transistor VT63, described 25 MOS transistor VT64, described 26 MOS transistor VT65 and described 27 MOS transistor VT66 form full-bridge topologies, and the described first drive end DRIVE1 of the grid of described 24 MOS transistor VT63 and the grid of described 27 MOS transistor VT66 and described driver or described second drive end DRIVE2 selects a drive singal output and is connected; Grid and the grid of described 25 MOS transistor VT64 of described 26 MOS transistor VT65 are connected with another drive singal output of described driver;

The drain electrode of described 25 MOS transistor VT64 is connected on the source electrode of described 24 MOS transistor VT63;

The drain electrode of described 24 MOS transistor VT63 is connected to the drain electrode of described 26 MOS transistor VT65, and the drain electrode of described 26 MOS transistor VT65 is also connected on one end of described 5th inductance L 61;

The other end of described 5th inductance L 61 is connected to one end of described 17 electric capacity C63, described 17 electric capacity C63 is in parallel with described 15 resistance R61, one end of described 17 electric capacity C63 is also connected with one end of described 15 resistance R61, the other end of described 17 electric capacity C63 is connected with the other end of described 15 resistance R61, and the other end of described 17 electric capacity C63 is also connected on the source electrode of described 27 MOS transistor VT66, at the two ends output voltage of described 15 resistance R61;

The drain electrode of described 27 MOS transistor VT66 is connected to the source electrode of described 26 MOS transistor VT65;

The drain electrode of described 27 MOS transistor VT66 is also connected to one end of second secondary of described 5th transformer T61;

The source electrode of described 27 MOS transistor VT66 is connected on the source electrode of described 25 MOS transistor VT64;

The drain electrode of described 25 MOS transistor VT64 is also connected to the other end of described second secondary of described 5th transformer T61.

With the difference of the second embodiment circuit theory diagrams be: the second embodiment secondary adopts all-wave synchronous rectification, and the 5th embodiment secondary adopts full-bridge synchronous rectification, both are all half-bridge topology in former limit.

As shown in Figure 7, the sixth embodiment of the present invention prevent in the device of current flowing backwards, second former limit circuit of described insulating power supply circuit 5 and the second secondary circuit, described second former limit circuit comprises: the 28 MOS transistor VT71, the 29 MOS transistor VT72, the 30 MOS transistor VT73 and the 31 MOS transistor VT74;

Wherein the 28 MOS transistor VT71, the 29 MOS transistor VT72, the 30 MOS transistor VT73 and the 31 MOS transistor VT74 form full-bridge topologies, the grid of described 28 MOS transistor VT71 and the grid of described 31 MOS transistor VT74, all with one end sub-connection of extraneous driving chip; The grid of described 29 MOS transistor VT72 and the grid of described 30 MOS transistor VT73, be all connected with the another terminal of extraneous driving chip;

The drain electrode of described 28 MOS transistor VT71 is connected to the positive pole of described power input voltage;

The source electrode of described 28 MOS transistor VT71 is connected to the drain electrode of described 30 MOS transistor VT73;

The drain electrode of described 30 MOS transistor VT73 is also connected to the one end on the second former limit of the 6th transformer T71;

The source electrode of described 30 MOS transistor VT73 is connected to the negative pole of described power input voltage;

The source electrode of described 30 MOS transistor VT73 is also connected on the source electrode of described 31 MOS transistor VT74;

The drain electrode of described 31 MOS transistor VT74 is connected to the other end on the second former limit of described 6th transformer T71;

The drain electrode of described 31 MOS transistor VT74 is also connected to the source electrode of described 29 MOS transistor VT72;

The drain electrode of described 29 MOS transistor VT72 is connected to the drain electrode of described 28 MOS transistor VT71;

Described second secondary circuit comprises: the 32 MOS transistor VT75, the 33 MOS transistor VT76, the 18 electric capacity C71, the 16 resistance R71 and the 6th inductance L 71;

Wherein, the grid of described 33 MOS transistor VT76 is connected to the described first drive end DRIVE1 of described driver or described second drive end DRIVE2 and selects a drive singal output and connect;

The grid of described 32 MOS transistor VT75 is connected to another drive singal output of described driver;

The source electrode of described 32 MOS transistor VT75 is connected on the source electrode of described 33 MOS transistor VT76, and the drain electrode of described 32 MOS transistor VT75 is connected to one end of second secondary of described 6th transformer T71;

The drain electrode of described 33 MOS transistor VT76 is connected to the other end of described second secondary of described 6th transformer T71, the source electrode of described 33 MOS transistor VT76 is connected to one end of described 18 electric capacity C71, one end of described 18 electric capacity C71 is also connected to described 16 resistance R71 one end, at the two ends output voltage of described 16 resistance R71;

Described 16 resistance R71 and described 18 electric capacity C71 is in parallel, and the other end of described 18 electric capacity C71 and the other end of described 16 resistance R71 are connected to one end of described 6th inductance L 71;

The other end of described 6th inductance L 71 is connected on second secondary of described 6th transformer T71.

With the difference of the first embodiment circuit theory diagrams be: the first embodiment secondary adopts full-bridge synchronous rectification, and the 6th embodiment secondary adopts all-wave synchronous rectification, both are all full-bridge topologies in former limit.

Given this, the device preventing current flowing backwards of the present invention, when input voltage power down, can react rapidly, comparison circuit 2 exports the secondary devices that control signal turns off insulating power supply circuit 5 fast, not only prevent inductance accumulation reverse current like this and cause metal-oxide-semiconductor avalanche breakdown damage, and be conducive to the reliability improving product, thus add competitiveness and the attraction of product.

The above is the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the prerequisite not departing from principle of the present invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.

Claims

1. one kind prevents the device of current flowing backwards, it is characterized in that, comprising: the sample circuit be connected with the power input of insulating power supply circuit, the comparison circuit be connected with described sample circuit, the buffer circuit be connected with described comparison circuit and the drive circuit be connected with described buffer circuit; Wherein

2. the device preventing current flowing backwards according to claim 1, is characterized in that, described sample circuit comprises:

First resistance (R2), the second resistance (R3) and the first electric capacity (C2);

Wherein, one end of described second resistance (R3) is connected to the input of described insulating power supply circuit, one end of described first resistance (R2) is connected with one end of described first electric capacity (C2), the other end of described second resistance (R3) is connected to one end of described first resistance (R2), and the other end of described second resistance (R3) is also connected to an input of described sample circuit;

The other end of described first resistance (R2) and the other end grounding connection of described first electric capacity (C2).

3. the device preventing current flowing backwards according to claim 2, it is characterized in that, described comparison circuit comprises: the comparator (D1) with positive input terminal, negative input end and output, the other end of described second resistance (R3) is connected to the negative input end of described comparator (D1), described predetermined reference voltage inputs the positive input terminal of described comparator (D1), the output of described comparator (D1) is connected to described buffer circuit, exports control signal described in.

4. the device preventing current flowing backwards according to claim 3, it is characterized in that, described buffer circuit comprises: have the first former limit and the optical coupler of the first secondary, the first former limit circuit be connected with the first former limit of described optical coupler and the first secondary circuit be connected with the first secondary of described optical coupler;

Wherein said first former limit circuit comprises: the 3rd resistance (R4), the first diode (VD1), the 4th resistance (R5), the second electric capacity (C3), the first MOS transistor (VT9), the 5th resistance (R6) and the 6th resistance (R7);

Wherein, one end of described 3rd resistance (R4) is connected with the output of described comparator (D1), and the other end of described 3rd resistance (R4) is connected with the input of described first diode (VD1);

One end of described 4th resistance (R5) is connected with one end of described second electric capacity (C3), the output of described first diode (VD1) is connected to one end of described 4th resistance (R5), the described other end of the 4th resistance (R5) and the other end grounding connection of described second electric capacity (C3);

One end of described 4th resistance (R5) is also connected to the grid of described first MOS transistor (VT9);

The source ground of described first MOS transistor (VT9) is connected to the other end of described second electric capacity (C3);

The drain electrode of described first MOS transistor (VT9) is connected to the output on the first former limit of described optical coupler;

One end of described 5th resistance (R6) is connected with one end of the 6th resistance (R7), and one end of described 5th resistance (R6) is also connected to internal power source voltage (VCC), the other end of described 5th resistance (R6) is connected with the other end of the 6th resistance (R7), and the other end of described 5th resistance (R6) is also connected to the input on the first former limit of described optical coupler;

Wherein said first secondary circuit comprises: the 7th resistance (R8), the 8th resistance (R9), the 9th resistance (R10), the 3rd electric capacity (C4), the first triode (VT10), the 4th electric capacity (C5), the tenth resistance (R11);

Wherein, a termination supply voltage (VDD) of described 7th resistance (R8), the other end of described 7th resistance (R8) is connected with the input of the first secondary of described optical coupler;

One end of described 8th resistance (R9) is connected to the output of the first secondary of described optical coupler;

One end of described 3rd electric capacity (C4) is also connected to the output of the first secondary of described optical coupler;

The other end of described 8th resistance (R9) is connected with one end of described 9th resistance (R10), the other end of described 9th resistance (R10) and the other end grounding connection of described 3rd electric capacity (C4);

The other end of described 8th resistance (R9) is also connected to the base stage of described first triode (VT10), and the grounded emitter of described first triode (VT10) connects;

Between the collector electrode that described 4th electric capacity (C5) and described tenth resistance (R11) are parallel to described first triode (VT10) and ground, one end of described 4th electric capacity (C5) is connected with one end of described tenth resistance (R11), the collector electrode of described first triode (VT10) is connected to one end of described 4th electric capacity (C5), the other end of described 4th electric capacity (C5) and the other end grounding connection of described tenth resistance (R11);

The collector electrode of described first triode (VT10) is also connected to the control signal input of described drive circuit.

5. the device preventing current flowing backwards according to claim 4, is characterized in that, the described first former limit of described optical coupler is described first secondary of light-emitting diode and described optical coupler is phototriode.

6. the device preventing current flowing backwards according to claim 4, it is characterized in that, described drive circuit comprises: the driver (D3) with control signal input and drive singal output, wherein said drive singal output is connected to described insulating power supply circuit, and described drive singal output comprises: the first drive end (DRIVE1) and the second drive end (DRIVE2).

7. the device preventing current flowing backwards according to claim 6, is characterized in that, described insulating power supply circuit comprises: the transformer with the second former limit and the second secondary;

8. the device preventing current flowing backwards according to claim 7, it is characterized in that, described second former limit circuit comprises: the second MOS transistor (VT21), the 3rd MOS transistor (VT22), the 4th MOS transistor (VT23) and the 5th MOS transistor (VT24);

Wherein said second MOS transistor (VT21), described 3rd MOS transistor (VT22), described 4th MOS transistor (VT23) and described 5th MOS transistor (VT24) form full-bridge topologies, the grid of described second MOS transistor (VT21) and the grid of described 5th MOS transistor (VT24), all with one end sub-connection of extraneous driving chip; The grid of described 3rd MOS transistor (VT22) and the grid of described 4th MOS transistor (VT23), be all connected with the another terminal of extraneous driving chip;

The drain electrode of described second MOS transistor (VT21) is connected to the positive pole of described power input voltage;

The source electrode of described second MOS transistor (VT21) is connected to the drain electrode of described 4th MOS transistor (VT23);

The drain electrode of described 4th MOS transistor (VT23) is also connected to the one end on the second former limit of the first transformer (T21);

The source electrode of described 4th MOS transistor (VT23) is connected to the negative pole of described power input voltage;

The source electrode of described 4th MOS transistor (VT23) is also connected on the source electrode of described 5th MOS transistor (VT24);

The drain electrode of described 5th MOS transistor (VT24) is connected to the other end on the second former limit of described first transformer (T21);

The drain electrode of described 5th MOS transistor (VT24) is also connected to the source electrode of described 3rd MOS transistor (VT22);

The drain electrode of described 3rd MOS transistor (VT22) is connected to the drain electrode of described second MOS transistor (VT21);

Described second secondary circuit comprises:

6th MOS transistor (VT25), the 7th MOS transistor (VT26), the 8th MOS transistor (VT27), the 9th MOS transistor (VT28), the 11 resistance (R21), the first inductance (L21) and the 5th electric capacity (C21);

Wherein said 6th MOS transistor (VT25), described 7th MOS transistor (VT26), described 8th MOS transistor (VT27) and described 9th MOS transistor (VT28) form full-bridge topologies, and the grid of described 6th MOS transistor (VT25) is selected a drive singal output with the grid of described 9th MOS transistor (VT28) with described first drive end (DRIVE1) of described driver or described second drive end (DRIVE2) and is connected; Grid and the described grid of the 7th MOS transistor (VT26) of described 8th MOS transistor (VT27) are connected with another drive singal output of described driver;

The drain electrode of described 7th MOS transistor (VT26) is connected on the source electrode of described 6th MOS transistor (VT25);

The drain electrode of described 6th MOS transistor (VT25) is connected to the drain electrode of described 8th MOS transistor (VT27), and the drain electrode of described 8th MOS transistor (VT27) is also connected on one end of described first inductance (L21);

The other end of described first inductance (L21) is connected to one end of described 5th electric capacity (C21), described 5th electric capacity (C21) is in parallel with described 11 resistance (R21), one end of described 5th electric capacity (C21) is connected with one end of described 11 resistance (R21), the other end of described 11 resistance (R21) is connected with the other end of described 5th electric capacity (C21), and the other end of described 5th electric capacity (C21) is also connected on the source electrode of described 9th MOS transistor (VT28), the two ends output voltage of described 11 resistance (R21),

The drain electrode of described 9th MOS transistor (VT28) is connected to the source electrode of described 8th MOS transistor (VT27);

The drain electrode of described 9th MOS transistor (VT28) is also connected to one end of the second secondary of described first transformer (T21);

The source electrode of described 9th MOS transistor (VT28) is connected on the source electrode of described 7th MOS transistor (VT26);

The drain electrode of described 7th MOS transistor (VT26) is also connected to the other end of the second secondary of described first transformer (T21).

9. the device preventing current flowing backwards according to claim 7, it is characterized in that, described second former limit circuit comprises: the tenth MOS transistor (VT31), the 11 MOS transistor (VT32), the 6th electric capacity (C31) and the 7th electric capacity (C32);

Wherein said tenth MOS transistor (VT31), described 11 MOS transistor (VT32), described 6th electric capacity (C31) and described 7th electric capacity (C32) form half-bridge topology, the grid of described tenth MOS transistor (VT31) is connected with the another terminal of extraneous driving chip with one end sub-connection of extraneous driving chip, the grid of described 11 MOS transistor (VT32);

Described 6th electric capacity (C31) one end is connected with one end of described 7th electric capacity (C32), and described 6th electric capacity (C31) one end is also connected to the one end on the second former limit of the second transformer (T31), the other end of described 6th electric capacity (C31) is connected to the positive pole of described power input voltage, and the other end of described 7th electric capacity (C32) is connected to the negative pole of described power input voltage;

The drain electrode of described tenth MOS transistor (VT31) is connected to described 6th electric capacity (C31) one end, the source electrode of described tenth MOS transistor (VT31) is connected to the drain electrode of described 11 MOS transistor (VT32), the drain electrode of described 11 MOS transistor (VT32) is also connected to the other end on the second former limit of described second transformer (T31), and the source electrode of described 11 MOS transistor (VT32) is connected to the other end of described 7th electric capacity (C32);

Described second secondary circuit comprises: the 12 MOS transistor (VT33), the 13 MOS transistor (VT34), the 8th electric capacity (C33), the 12 resistance (R31) and the second inductance (L31);

Wherein, the grid of described 13 MOS transistor (VT34) is connected to described first drive end (DRIVE1) of described driver or described second drive end (DRIVE2) and selects a drive singal output and connect;

The grid of described 12 MOS transistor (VT33) is connected to another drive singal output of described driver;

The source electrode of described 12 MOS transistor (VT33) is connected on the source electrode of described 13 MOS transistor (VT34), and the drain electrode of described 12 MOS transistor (VT33) is connected to one end of the second secondary of the second transformer (T31);

The drain electrode of described 13 MOS transistor (VT34) is connected to the other end of the second secondary of described second transformer (T31), the source electrode of described 13 MOS transistor (VT34) is connected to described 8th electric capacity (C33) one end, described 8th electric capacity (C33) one end is also connected to described 12 resistance (R31) one end, at the two ends output voltage of described 12 resistance (R31);

Described 12 resistance (R31) and described 8th electric capacity (C33) parallel connection, the other end of described 8th electric capacity (C33) and the other end of described 12 resistance (R31) are connected to one end of described second inductance (L31);

The other end of described second inductance (L31) is connected on the second secondary of described second transformer (T31).

10. the device preventing current flowing backwards according to claim 7, is characterized in that, described second former limit circuit comprises:

14 MOS transistor (VT41), the 15 MOS transistor (VT42), the 9th electric capacity (C41) and the tenth electric capacity (C42);

Wherein, described 14 MOS transistor (VT41), described 15 MOS transistor (VT42), described 9th electric capacity (C41) and described tenth electric capacity (C42) form active clamp topological structure, the grid of described 14 MOS transistor (VT41) is connected with the another terminal of extraneous driving chip with one end sub-connection of extraneous driving chip, the grid of described 15 MOS transistor (VT42); One end of described 9th electric capacity (C41) is connected to the positive pole of described power input voltage, and is connected to the one end on the second former limit of the 3rd transformer (T41);

Described 9th electric capacity (C41) other end is connected to the negative pole of described power input voltage;

The other end of described 9th electric capacity (C41) is also connected to the source electrode of described 14 MOS transistor (VT41);

The drain electrode of described 14 MOS transistor (VT41) is connected to one end of described tenth electric capacity (C42), and the other end of described tenth electric capacity (C42) is connected to the other end on the second former limit of described 3rd transformer (T41);

The drain electrode of described 15 MOS transistor (VT42) is also connected to the other end on the second former limit of described 3rd transformer (T41);

The source electrode of described 15 MOS transistor (VT42) is also connected on the source electrode of described 14 MOS transistor (VT41);

Described second secondary circuit comprises: the 16 MOS transistor (VT43), the 17 MOS transistor (VT44), the 11 electric capacity (C43), the 13 resistance (R41) and the 3rd inductance (L41);

The grid of described 16 MOS transistor (VT43) is connected to described first drive end (DRIVE1) of the described drive singal output of described driver or described second drive end (DRIVE2) and selects a drive singal output and connect;

The grid of described 17 MOS transistor (VT44) is connected to another drive singal output of described driver;

The source electrode of described 16 MOS transistor (VT43) is connected to one end of the second secondary of described 3rd transformer (T41), and the drain electrode of described 16 MOS transistor (VT43) is connected to one end of described 3rd inductance (L41);

The other end of described 3rd inductance (L41) is connected with one end of described 13 resistance (R41), described 13 resistance (R41) and described 11 electric capacity (C43) parallel connection, described 13 resistance (R41) one end is also connected with one end of described 11 electric capacity (C43), the other end of described 13 resistance (R41) is also connected with the other end of described 11 electric capacity (C43), and the other end of described 11 electric capacity (C43) is connected on the source electrode of described 17 MOS transistor (VT44), the two ends output voltage of described 13 resistance (R41),

The source electrode of described 17 MOS transistor (VT44) is connected to the other end of the second secondary of described 3rd transformer (T41), and the drain electrode of described 17 MOS transistor (VT44) is also connected to one end of described 3rd inductance (L41).

11. devices preventing current flowing backwards according to claim 7, it is characterized in that, described second former limit circuit comprises: the 18 MOS transistor (VT51), the 19 MOS transistor (VT52), the 12 electric capacity (C51) and the 13 electric capacity (C52);

Wherein, described 18 MOS transistor (VT51), described 19 MOS transistor (VT52), described 12 electric capacity (C51) and described 13 electric capacity (C52) form active clamp circuit, the grid of described 18 MOS transistor (VT51) is connected with the another terminal of extraneous driving chip with one end sub-connection of extraneous driving chip, the grid of described 19 MOS transistor (VT52);

Described 12 electric capacity (C51) one end is connected to the positive pole of described power input voltage;

The other end of described 12 electric capacity (C51) is connected to the negative pole of described power input voltage;

One end of described 13 electric capacity (C52) is connected to one end of described 12 electric capacity (C51), and one end of described 13 electric capacity (C52) is also connected to the one end on the second former limit of the 4th transformer (T51);

The other end of described 13 electric capacity (C52) is connected to the drain electrode of described 18 MOS transistor (VT51);

The source electrode of described 18 MOS transistor (VT51) is connected to the other end on the second former limit of the 4th transformer (T51);

The source electrode of described 18 MOS transistor (VT51) also connects the drain electrode of described 19 MOS transistor (VT52);

The source electrode of described 19 MOS transistor (VT52) is connected on described 12 electric capacity (C51) other end;

Described second secondary circuit comprises: the 20 MOS transistor (VT53), the 21 MOS transistor (VT54), the 14 electric capacity (C53), the 14 resistance (R51) and the 4th inductance (L51);

The grid of described 20 MOS transistor (VT53) is connected to described first drive end (DRIVE1) of the described drive singal output of described driver or described second drive end (DRIVE2) and selects a drive singal output and connect;

The grid of described 21 MOS transistor (VT54) is connected to another drive singal output of described driver;

The source electrode of described 20 MOS transistor (VT53) is connected to one end of the second secondary of described 4th transformer (T51), and the drain electrode of described 20 MOS transistor (VT53) is connected to one end of described 4th inductance (L51);

The other end of described 4th inductance (L51) is connected with one end of described 14 resistance (R51), described 14 resistance (R51) and described 14 electric capacity (C53) parallel connection, described 14 resistance (R51) one end is also connected with one end of described 14 electric capacity (C53), the other end of described 14 resistance (R51) is also connected with the other end of described 14 electric capacity (C53), and the other end of described 14 electric capacity (C53) is connected on the source electrode of described 21 MOS transistor (VT54), the two ends output voltage of described 14 resistance (R51),

The source electrode of described 21 MOS transistor (VT54) is connected to the other end of the second secondary of described 4th transformer (T51), and the drain electrode of described 21 MOS transistor (VT54) is also connected to one end of described 4th inductance (L51).