CN109240408A - SiCMOSFET gate drive voltage control circuit and its control method - Google Patents
SiCMOSFET gate drive voltage control circuit and its control method Download PDFInfo
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- CN109240408A CN109240408A CN201811288609.8A CN201811288609A CN109240408A CN 109240408 A CN109240408 A CN 109240408A CN 201811288609 A CN201811288609 A CN 201811288609A CN 109240408 A CN109240408 A CN 109240408A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/569—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection
Abstract
The invention discloses SiCMOSFET gate drive voltage control circuit, including fpga chip, fpga chip are connected separately with gate-drive grade, current detection circuit, voltage detecting circuit.The invention also discloses the gate drive voltage control methods of SiCMOSFET, this method through the invention the first technical solution SiCMOSFET gate drive voltage control circuit realize voltage control, it is specifically included in SiCMOSFET gate drive voltage control circuit and accesses SiCMOSFET, and fpga chip is connected with switch, when switch is turned on and off, fpga chip control gate-drive grade exports different gate drive voltages, keeps SiCMOSFET fully on or SiCMOSFET is complete switched off.The present invention can effectively inhibit the problems such as overshoot occurred in high-power SiCMOSFET frequency applications, oscillation, EMI.
Description
Technical field
The invention belongs to SiCMOSFET actuation techniques fields, are related to SiCMOSFET gate drive voltage control circuit, also
It is related to the gate drive voltage control method of SiCMOSFET.
Background technique
With the rapid development of power electronic technique, more and more applications put forward new requirements power equipment, such as
Higher electric current and voltage, higher power density and higher efficiency.With higher switching frequency, higher thermal conductivity, more
With the characteristics of high operation temperature and lower switch and conduction loss, SiCMOSFET is expected to be gradually available for meeting these requirements.So
And it is switched fast to cross caused by speed and parasitic antenna and penetrates, vibrates and electromagnetic interference (EMI) is its widely applied crucial barrier
Hinder.The above problem solves usually in terms of three: 1) slowing down switching speed.Switching speed is reduced by increasing gate electrode resistance
Can substantially reduced switch stress, oscillation, inhibit EMI.But the reduction of switching speed can bring more switching losses, extend
Switch time.2) increase RC buffer circuit.Inhibiting switch stress using RC buffer circuit is a kind of common methods, however, larger
Electrical stress can marry again on RC circuit.On the other hand, large volume of RC absorbing circuit increases energy loss, reduces
System effectiveness.3) optimize topology layout.Optimised devices encapsulation and reduction loop of power circuit stray inductance are most important two methods.
But new encapsulation technology higher cost and marketization time is longer.In addition, structure is complicated for loop of power circuit in high-power system
It is not easy to optimize.
Summary of the invention
The object of the present invention is to provide SiCMOSFET gate drive voltage control circuits, solve existing high-power
Overshoot, oscillation, EMI and switching loss problem in SiCMOSFET frequency applications.
It is a further object of the present invention to provide the gate drive voltage control methods of SiCMOSFET.
The first technical solution of the present invention is that SiCMOSFET gate drive voltage control circuit, feature exists
In, including fpga chip, fpga chip be connected separately with gate-drive grade, current detection circuit, voltage detecting circuit；
Current detection circuit includes the rise-time of current detection circuit connecting with fpga chip and the detection of electric current failing edge
Circuit, voltage detecting circuit include and the sequentially connected comparator CP of fpga chip3With resistive-capacitive voltage divider circuit.
The characteristics of the first technical solution of the invention, also resides in,
Rise-time of current detection circuit includes triode T1, the collector and emitter of triode is connected separately with resistance R3
With resistance R4, triode T1Collector be also connected with comparator CP2, triode T1With comparator CP2Between be in series with resistance, than
Compared with device CP2It is connect again with fpga chip, triode T1Base earth, triode T1Base stage and emitter between be connected with two
Pole pipe D2；
Electric current failing edge detection circuit includes and the sequentially connected comparator CP of fpga chip1With proportion divider circuit.
Gate-drive grade includes two the first gate drivers and the second gate driver, and the first gate driver is connected with
Gate electrode resistance, fpga chip are connect with the input terminal of the first gate driver and the second gate driver respectively, and the first gate pole
The supply voltage of driver is higher than the supply voltage of the second gate driver.
The model of first gate driver and the second gate driver is IXDN609SIA.
The first technical solution of the present invention is the gate drive voltage control method of SiCMOSFET, this method
The SiCMOSFET gate drive voltage control circuit of the first technical solution realizes voltage control through the invention, specifically includes
Following steps:
The output end of first gate driver is connected by the gate pole of gate electrode resistance and SiCMOSFET, the second gate pole drives
The output end of dynamic device and the auxiliary source electrode of SiCMOSFET connect, the input terminal and resistance R of proportion divider circuit4With
The power source of SiCMOSFET connects, and the drain-source pole connection of the SiCMOSFET of resistive-capacitive voltage divider circuit, fpga chip accesses PWM
Signal；
When the pwm signal of access is PWM open signal, fpga chip controls gate-drive grade and exports the first gate-drive
Voltage charges to SiCMOSFET gate pole, and SiCMOSFET gate voltage rises and reaches the threshold voltage V of SiCMOSFETTH,
When current detection circuit detects that circuital current is begun to ramp up, comparator CP2It generates the first level signal and believes the first level
Number it is sent to fpga chip, fpga chip is from receiving the first level signal by delay time t1, fpga chip control
Gate-drive grade exports the second driving voltage and charges to SiCMOSFET gate pole, when voltage detecting circuit detects
When the drain-source voltage of SiCMOSFET drops to less than 10% busbar voltage, comparator CP3Generate the second electric frequency signal simultaneously
Fpga chip is sent by second electrical level signal, fpga chip controls gate-drive grade and exports third gate drive voltage, third
Gate drive voltage is identical as the first gate drive voltage, at this point, SiCMOSFET is fully on；First gate drive voltage is
Just, and the first gate drive voltage is equal with the voltage value of the first gate driver, and the second gate drive voltage is positive, and
Second gate drive voltage is equal to the voltage difference of the first gate driver supply voltage and the second gate driver supply voltage；
When the pwm signal of access is PWM cut-off signals, fpga chip controls gate-drive grade and exports the 4th gate-drive
Voltage, the 4th gate drive voltage are negative, and SiCMOSFET gate voltage declines and reaches Miller platform voltage VMiller, work as voltage
When detection circuit detects that circuit voltage rises above 10% busbar voltage, comparator CP3Generate third level signal simultaneously
Fpga chip is sent by third level signal, fpga chip is from receiving second electrical level signal by delay time t2Afterwards,
Fpga chip controls gate-drive grade and exports the 5th gate drive voltage, and the 5th gate drive voltage is 0V, and circuit voltage continues
Rise, when circuit voltage is equal with busbar voltage, circuital current decline, when current detection circuit detects that circuital current is 0,
Comparator CP1It generates the 4th level signal and sends fpga chip for the 4th level signal, fpga chip controls gate-drive
Grade the 6th gate drive voltage of output, the 6th gate drive voltage is identical as the 4th gate drive voltage, at this point, SiCMOSFET
It complete switches off.
The characteristics of second of technical solution of the invention, also resides in,
Delay time t1With delay time t2Meet following formula respectively:
In formula (5) and formula (6), ton,1When being the rising that gate-drive grade exports the first gate drive voltage circuital current
Between, toff,2It is the fall time of circuital current when gate-drive grade exports four gate drive voltages, EonIndicate SiCMOSFET
Energy loss in turn on process, EoffIndicate the energy loss in SiCMOSFET turn off process, IrrIndicate that SiCMOSFET is complete
Current over pulse value in turn on process, VosVoltage overshoot value during expression SiCMOSFET is complete switched off,
In formula (7) and formula (8), LloopIt is the stray inductance in loop of power circuit, VDSIndicate that the drain-source of SiCMOSFET is extremely electric
Pressure, t indicate the time,Indicate the slope of the drain-source voltage waveform of SiCMOSFET, LsFor auxiliary source electrode and power source
Between parasitic inductance, ILIndication circuit load current, when SiCMOSFET is fully on, circuit load electric current and circuit electricity
It flows equal, since the slope variation bring energy loss of the drain-source voltage of SiCMOSFET is not obvious, therefore is regarded as
Definite value, VDCIndicate busbar voltage, σsIndicate the ratio of overvoltage and busbar voltage, QrrIndicate the Reverse recovery electricity of SiCMOSFET
Lotus, K indication circuit current waveform slope, and
Circuital current waveform slope K is not definite value, is calculated to simplify, and only considers the variation of present current waveform slope,
It is according to current equivalence principle, the K of variation is equivalent at constant slope K and K ', K and K ' it respectively indicates, it may be assumed that
In formula (11), K1、K2The waveform of circuital current when to export the first gate drive voltage, the second gate drive voltage
Slope, in formula (12), K3、K4The waveform of circuital current is oblique when to export the 4th gate drive voltage, five gate drive voltages
Rate.
The invention has the advantages that SiCMOSFET gate drive voltage control circuit of the present invention is simple and efficient,
In SiCMOSFET switching process, according to detection circuit feedback signal, lesser gate-drive electricity is used in electric current and voltage stage
The problems such as pressing, effectively inhibiting the overshoot occurred in high-power SiCMOSFET frequency applications, oscillation, EMI, the present invention
The gate drive voltage control method of SiCMOSFET, the SiCMOSFET gate drive voltage of this method through the invention control electricity
Voltage control is realized on road, provides powerful guarantee the characteristics of SiCMOSFET frequency applications to give full play to.
Detailed description of the invention
Fig. 1 is the circuit diagram of SiCMOSFET gate drive voltage control circuit of the present invention.
In figure, 1.FPGA chip, 2. gate-drive grades, 3. current detection circuits, 4. voltage detecting circuits.
Specific embodiment
The present invention is described in detail with Figure of description With reference to embodiment.
SiCMOSFET gate drive voltage control circuit of the present invention, including fpga chip 1, fpga chip 1 are connected separately with
Gate-drive grade 2, current detection circuit 3, voltage detecting circuit 4；
Current detection circuit 3 includes the rise-time of current detection circuit connecting with fpga chip 1 and the inspection of electric current failing edge
Slowdown monitoring circuit, voltage detecting circuit 4 include and the sequentially connected comparator CP of fpga chip 13With resistive-capacitive voltage divider circuit.
Rise-time of current detection circuit includes triode T1, the collector and emitter of triode is connected separately with resistance R3
With resistance R4, triode T1Collector be also connected with comparator CP2, triode T1With comparator CP2Between be in series with resistance, than
Compared with device CP2It is connect again with fpga chip 1, triode T1Base earth, triode T1Base stage and emitter between be connected with two
Pole pipe D2；
Electric current failing edge detection circuit includes and the sequentially connected comparator CP of fpga chip 11With proportion divider circuit.
Gate-drive grade includes two the first gate drivers and the second gate driver, the first gate driver and second
The model of gate driver is IXDN609SIA, and the first gate driver is connected with gate electrode resistance, and fpga chip 1 is respectively with
The connection of the input terminal of one gate driver and the second gate driver, and the supply voltage of the first gate driver is higher than second
The supply voltage of driver.
The gate drive voltage control method of SiCMOSFET of the present invention, the SiCMOSFET that this method passes through aforementioned present invention
Gate drive voltage control circuit realizes voltage control, specifically includes the following steps:
The output end of first gate driver is connected by the gate pole of gate electrode resistance and SiCMOSFET, the second gate pole drives
The output end of dynamic device and the auxiliary source electrode of SiCMOSFET connect, the input terminal and resistance R of proportion divider circuit4With
The power source of SiCMOSFET connects, and the drain-source pole connection of the SiCMOSFET of resistive-capacitive voltage divider circuit, fpga chip 1 accesses PWM
Signal；
When the pwm signal of access is PWM open signal, fpga chip 1 controls gate-drive grade 2 and exports the drive of the first gate pole
Dynamic voltage charges to SiCMOSFET gate pole, and SiCMOSFET gate voltage rises and reaches the threshold voltage of SiCMOSFET
VTH, when current detection circuit 3 detects that circuital current is begun to ramp up, comparator CP2Generate the first level signal and by first electricity
Ordinary mail number is sent to fpga chip 1, and fpga chip 1 is from receiving the first level signal by delay time t1, FPGA core
Piece 1 controls the second driving voltage of output of gate-drive grade 2 and charges to SiCMOSFET gate pole, when voltage detecting circuit 4 detects
When dropping to less than 10% busbar voltage to the drain-source voltage of SiCMOSFET, comparator CP3Generate the second electric frequency signal
And fpga chip 1 is sent by second electrical level signal, fpga chip 1 controls gate-drive grade 2 and exports third gate drive voltage,
Third gate drive voltage is identical as the first gate drive voltage, at this point, SiCMOSFET is fully on；First gate-drive electricity
Pressure is positive, and the first gate drive voltage is equal with the voltage value of the first gate driver, and the second gate drive voltage is
Just, and the second gate drive voltage be equal to the first gate driver supply voltage and the second gate driver supply voltage voltage
Difference；
When the pwm signal of access is PWM cut-off signals, fpga chip 1 controls gate-drive grade 2 and exports the drive of the 4th gate pole
Dynamic voltage, the 4th gate drive voltage are negative, and SiCMOSFET gate voltage declines and reaches Miller platform voltage VMiller, work as electricity
When pressure detection circuit 4 detects that circuit voltage rises above 10% busbar voltage, comparator CP3Generate third level signal
And fpga chip 1 is sent by third level signal, fpga chip 1 is from receiving second electrical level signal by delay time t2
Afterwards, fpga chip 1 controls gate-drive grade 2 and exports the 5th gate drive voltage, and the 5th gate drive voltage is 0V, circuit voltage
Continue to rise, when circuit voltage is equal with busbar voltage, circuital current decline, current detection circuit 3 detects circuital current
When being 0, comparator CP1It generates the 4th level signal and sends fpga chip 1 for the 4th level signal, fpga chip 1 controls
Gate-drive grade 2 exports the 6th gate drive voltage, and the 6th gate drive voltage is identical as the 4th gate drive voltage, at this point,
SiCMOSFET is complete switched off.
Delay time t1With delay time t2Meet following formula respectively:
In formula (5) and formula (6), ton,1When being the rising of circuital current when gate-drive grade exports the first gate drive voltage
Between, toff,2It is the fall time of circuital current when gate-drive grade exports four gate drive voltages, EonIndicate SiCMOSFET
Energy loss in turn on process, EoffIndicate the energy loss in SiCMOSFET turn off process, IrrIndicate that SiCMOSFET is complete
Current over pulse value in turn on process, VosVoltage overshoot value during expression SiCMOSFET is complete switched off,
In formula (7) and formula (8), LloopIt is the stray inductance in loop of power circuit, VDSIndicate that the drain-source of SiCMOSFET is extremely electric
Pressure, t indicate the time,Indicate the slope of the drain-source voltage waveform of SiCMOSFET, LsFor auxiliary source electrode and power source
Between parasitic inductance, ILIndication circuit load current, when SiCMOSFET is fully on, circuit load electric current and circuit electricity
It flows equal, since the slope variation bring energy loss of the drain-source voltage of SiCMOSFET is not obvious, therefore is regarded as
Definite value, VDCIndicate busbar voltage, σsIndicate the ratio of overvoltage and busbar voltage, QrrIndicate the Reverse recovery electricity of SiCMOSFET
Lotus, K indication circuit current waveform slope, and
。
Circuital current waveform slope K is not definite value, it is calculated to simplify, only considers the variation of present current waveform slope,
It is according to current equivalence principle, the K of variation is equivalent at constant slope K and K ', K and K ' it respectively indicates, it may be assumed that
In formula (11), K1、K2The waveform of circuital current when to export the first gate drive voltage, the second gate drive voltage
Slope, in formula (12), K3、K4The waveform of circuital current is oblique when to export the 4th gate drive voltage, five gate drive voltages
Rate.
Embodiment:
The gate drive voltage control method of the present embodiment SiCMOSFET, this method pass through aforementioned present invention
SiCMOSFET gate drive voltage control circuit realizes voltage control, wherein the first gate driver supply voltage is 20V, the
Two gate driver supply voltages are 5V, specifically includes the following steps:
The output end of first gate driver is connected by the gate pole of gate electrode resistance and SiCMOSFET, the second gate pole drives
The output end of dynamic device and the auxiliary source electrode of SiCMOSFET connect, the input terminal and resistance R of proportion divider circuit4With
The power source of SiCMOSFET connects, and the drain-source pole connection of the SiCMOSFET of resistive-capacitive voltage divider circuit, fpga chip 1 accesses PWM
Signal；
When the pwm signal of access is PWM open signal, fpga chip 1 controls+20V pairs of 2 output of gate-drive grade
SiCMOSFET gate pole charges, and SiCMOSFET gate voltage rises and reaches the threshold voltage V of SiCMOSFETTH, electric current inspection
When slowdown monitoring circuit 3 detects that circuital current is begun to ramp up, comparator CP2It generates the first level signal and sends the first level signal
To fpga chip 1 is arrived, fpga chip 1 is from receiving the first level signal by delay time t1=70ns, fpga chip 1 are controlled
The first gate driver output+20V, the second gate driver output+5V is made, that is, exports+15V pairs of gate drive voltage
SiCMOSFET gate pole charges, when voltage detecting circuit 4 detects that the drain-source voltage of SiCMOSFET drops to less than
When 10% busbar voltage, comparator CP3It generates the second electric frequency signal and sends fpga chip 1 for second electrical level signal,
The the first gate driver output+20V of control of fpga chip 1, the second gate driver output 0V, i.e. output gate drive voltage+
20V, at this point, SiCMOSFET is fully on；
When the pwm signal of access be PWM cut-off signals when, fpga chip 1 control the first gate driver export 0V, second
Gate driver exports 5V, i.e. output gate drive voltage -5V discharges to SiCMOSFET gate pole, SiCMOSFET gate pole electricity
Pressure begins to decline from 20V and reaches Miller platform voltage VMiller, when voltage detecting circuit 4 detects that circuit voltage rises to greatly
When 10% busbar voltage, comparator CP3It generates third level signal and sends fpga chip 1 for third level signal,
Fpga chip 1 is from receiving second electrical level signal by delay time t2After=110ns, fpga chip 1 controls the first gate pole
Driver exports 0V, and the second gate driver exports 0V, i.e. output gate drive voltage 0V puts SiCMOSFET gate pole
Electricity, circuit voltage continue to rise, and when circuit voltage is equal with busbar voltage, circuital current decline, current detection circuit 3 is detected
To circuital current be 0 when, comparator CP1It generates the 4th level signal and sends fpga chip 1, FPGA for the 4th level signal
Chip 1 controls the first gate driver and exports 0V, and the second gate driver exports 5V, i.e. output gate drive voltage -5V, this
When, SiCMOSFET is complete switched off.
Claims (7)
1.SiCMOSFET gate drive voltage control circuit, which is characterized in that including fpga chip (1), the fpga chip
(1) gate-drive grade (2), current detection circuit (3), voltage detecting circuit (4) are connected separately with；
The current detection circuit (3) includes the rise-time of current detection circuit connecting with fpga chip (1) and electric current decline
Along detection circuit, the voltage detecting circuit (4) includes and the sequentially connected comparator CP of fpga chip (1)3And resistive-capacitive voltage divider
Circuit.
2. SiCMOSFET gate drive voltage control circuit according to claim 1, which is characterized in that on the electric current
Rising along detection circuit includes triode T1, the collector and emitter of the triode is connected separately with resistance R3With resistance R4, institute
State triode T1Collector be also connected with comparator CP2, the triode T1With comparator CP2Between be in series with resistance, it is described
Comparator CP2It is connect again with fpga chip (1), the triode T1Base earth, the triode T1Base stage and emitter
Between be connected with diode D2；
The electric current failing edge detection circuit includes and the sequentially connected comparator CP of fpga chip (1)1With proportion divider circuit.
3. SiCMOSFET gate drive voltage control circuit according to claim 1, which is characterized in that the gate pole drives
Dynamic grade includes two the first gate drivers and the second gate driver, and first gate driver is connected with gate electrode resistance,
The fpga chip (1) connect with the input terminal of the first gate driver and the second gate driver respectively, and the first gate pole drives
The supply voltage of dynamic device is higher than the supply voltage of the second gate driver.
4. SiCMOSFET gate drive voltage control circuit according to claim 3, which is characterized in that described first
The model of driver and the second gate driver is IXDN609SIA.
The gate drive voltage control method of 5.SiCMOSFET, this method pass through SiCMOSFET described in claim 1-4
Pole driving voltage controlling circuit realizes voltage control, which is characterized in that specifically includes the following steps:
The output end of first gate driver is connected by the gate pole of gate electrode resistance and SiCMOSFET, described second
The output end of driver and the auxiliary source electrode of SiCMOSFET connect, the input terminal and resistance R of the proportion divider circuit4?
It is connect with the power source of SiCMOSFET, the drain-source pole connection of the SiCMOSFET of the resistive-capacitive voltage divider circuit, the FPGA core
Piece (1) accesses pwm signal；
When the pwm signal of access is PWM open signal, the fpga chip (1) control gate-drive grade (2) output the
One gate drive voltage charges to SiCMOSFET gate pole, and SiCMOSFET gate voltage rises and reaches SiCMOSFET's
Threshold voltage VTH, when the current detection circuit (3) detects that circuital current is begun to ramp up, comparator CP2Generate the first level
Signal simultaneously sends the first level signal to fpga chip (1), fpga chip (1) from receiving the first level signal by
Delay time t1, fpga chip (1) control gate-drive grade (2) export the second driving voltage SiCMOSFET gate pole is filled
Electricity, when voltage detecting circuit (4) detects that the drain-source voltage of SiCMOSFET drops to less than 10% busbar voltage, than
Compared with device CP3It generates the second electric frequency signal and sends second electrical level signal to fpga chip (1), fpga chip (1) controls gate pole
Driving stage (2) exports third gate drive voltage, and third gate drive voltage is identical as the first gate drive voltage, at this point,
SiCMOSFET is fully on；First gate drive voltage is positive, and the confession of the first gate drive voltage and the first gate driver
Piezoelectric voltage value is equal, and the second gate drive voltage is positive, and the second gate drive voltage is equal to the first gate driver power supply electricity
The voltage difference of pressure and the second gate driver supply voltage；
When the pwm signal of access is PWM cut-off signals, the fpga chip (1) control gate-drive grade (2) output the
Four gate drive voltages, the 4th gate drive voltage are negative, and SiCMOSFET gate voltage declines and reaches Miller platform electricity
Press VMiller, when voltage detecting circuit (4) detects that circuit voltage rises above 10% busbar voltage, comparator CP3It produces
Raw third level signal simultaneously sends third level signal to fpga chip (1), and fpga chip (1) receives second electrical level letter certainly
Number rise pass through delay time t2Afterwards, fpga chip (1) control gate-drive grade (2) exports the 5th gate drive voltage, and described the
Five gate drive voltages are 0V, and circuit voltage continues to rise, when circuit voltage is equal with busbar voltage, circuital current decline,
When current detection circuit (3) detects that circuital current is 0, comparator CP1Generate the 4th level signal and by the 4th level signal
It is sent to fpga chip (1), fpga chip (1) control gate-drive grade (2) the 6th gate drive voltage of output, described 6th
Pole driving voltage is identical as the 4th gate drive voltage, at this point, SiCMOSFET is complete switched off.
6. SiCMOSFET gate drive voltage control circuit according to claim 5, which is characterized in that when the delay
Between t1With delay time t2Meet following formula respectively:
In formula (5) and formula (6), ton,1It is the rise time that gate-drive grade exports the first gate drive voltage circuital current,
toff,2It is the fall time that gate-drive grade exports the 4th gate drive voltage circuital current, EonIndicate that SiCMOSFET was connected
Energy loss in journey, EoffIndicate the energy loss in SiCMOSFET turn off process, IrrIndicate the fully on mistake of SiCMOSFET
Current over pulse value in journey, VosVoltage overshoot value during expression SiCMOSFET is complete switched off,
In formula (7) and formula (8), LloopIt is the stray inductance in loop of power circuit, VDSIndicate the drain-source voltage of SiCMOSFET, t
Indicate the time,Indicate the slope of the drain-source voltage waveform of SiCMOSFET, LsBetween auxiliary source electrode and power source
Parasitic inductance, ILIndication circuit load current, when SiCMOSFET is fully on, circuit load electric current and circuital current phase
Deng, since the slope variation bring energy loss of the drain-source voltage of SiCMOSFET is not obvious, therefore it is regarded as definite value,
VDCIndicate busbar voltage, σsIndicate the ratio of overvoltage and busbar voltage, QrrIndicate the reverse recovery charge of SiCMOSFET, K table
Show circuital current waveform slope, and
7. SiCMOSFET gate drive voltage control circuit according to claim 6, which is characterized in that the circuit electricity
Flowing waveform slope K is not definite value, it is calculated to simplify, only considers the variation of present current waveform slope, according to current equivalence original
Then, the K of variation is equivalent at constant slope K and K ', K and K ' it respectively indicates, it may be assumed that
In formula (11), K1、K2The waveform slope of circuital current when to export the first gate drive voltage, the second gate drive voltage,
In formula (12), K3、K4The waveform slope of circuital current when to export the 4th gate drive voltage, five gate drive voltages.
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| CN111865054A (en) * | 2020-06-23 | 2020-10-30 | 华源智信半导体(深圳)有限公司 | Dynamic driving method and circuit based on grid voltage detection and switch converter |
| WO2021129421A1 (en) * | 2019-12-24 | 2021-07-01 | 中车永济电机有限公司 | Drive apparatus for sic power device, and traction system |
| CN116647219A (en) * | 2023-04-27 | 2023-08-25 | 北京芯可鉴科技有限公司 | IGBT driving circuit, method for driving IGBT and chip |
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| CN101617471A (en) * | 2006-09-13 | 2009-12-30 | 剑桥企业有限公司 | The control method of power semiconductor and circuit |
| CN101174788A (en) * | 2007-10-22 | 2008-05-07 | 株洲南车时代电气股份有限公司 | Cut-out overvoltage protection circuit of electric voltage driving type power semiconductor device |
| US9293284B1 (en) * | 2011-11-22 | 2016-03-22 | Lockheed Martin Corporation | Soft-switching gate control |
| CN106130522A (en) * | 2016-07-14 | 2016-11-16 | 南京航空航天大学 | A kind of SiC MOSFET gradual change level driving circuit being applicable to DC solid-state power controller and method |
| CN108092493A (en) * | 2017-12-26 | 2018-05-29 | 南京工程学院 | A kind of SiC MOSFET series circuits |
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| WO2021129421A1 (en) * | 2019-12-24 | 2021-07-01 | 中车永济电机有限公司 | Drive apparatus for sic power device, and traction system |
| CN111865054A (en) * | 2020-06-23 | 2020-10-30 | 华源智信半导体(深圳)有限公司 | Dynamic driving method and circuit based on grid voltage detection and switch converter |
| CN111865054B (en) * | 2020-06-23 | 2022-02-11 | 华源智信半导体(深圳)有限公司 | Dynamic driving method and circuit based on grid voltage detection and switch converter |
| CN116647219A (en) * | 2023-04-27 | 2023-08-25 | 北京芯可鉴科技有限公司 | IGBT driving circuit, method for driving IGBT and chip |
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