CN109240408B - SicMOSFET gate drive voltage control circuit and control method thereof - Google Patents

SicMOSFET gate drive voltage control circuit and control method thereof Download PDF

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CN109240408B
CN109240408B CN201811288609.8A CN201811288609A CN109240408B CN 109240408 B CN109240408 B CN 109240408B CN 201811288609 A CN201811288609 A CN 201811288609A CN 109240408 B CN109240408 B CN 109240408B
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杨媛
文阳
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Xian University of Technology
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    • G05—CONTROLLING; REGULATING
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    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
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    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
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    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G05F1/569—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection

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Abstract

The invention discloses a SiCMOSFET gate drive voltage control circuit which comprises an FPGA chip, wherein the FPGA chip is respectively connected with a gate drive stage, a current detection circuit and a voltage detection circuit. The invention also discloses a method for controlling the gate driving voltage of the SicMOSFET, which realizes voltage control through the SicMOSFET gate driving voltage control circuit in the first technical scheme of the invention. The invention can effectively inhibit the problems of overshoot, oscillation, EMI and the like in the high-frequency application of the high-power SiCSMOSFET.

Description

SicMOSFET gate drive voltage control circuit and control method thereof
Technical Field
The invention belongs to the technical field of SiCMOS (silicon-based metal oxide semiconductor field effect transistor) drive, relates to a SiCMOS gate drive voltage control circuit and further relates to a gate drive voltage control method of a SiCMOS gate.
Background
With the rapid development of power electronics technology, more and more applications place new demands on power equipment, such as higher current and voltage, higher power density, and higher efficiency. Sicmosfets are expected to be increasingly used to meet these requirements, featuring higher switching frequencies, higher thermal conductivity, higher operating temperatures and lower switching and conduction losses. However, fast switching speeds and spurious component induced overruns, oscillations and electromagnetic interference (EMI) are key obstacles to their widespread use. The above problems are generally solved from three aspects: 1) slowing down the switching speed. By increasing the gate resistance to reduce the switching speed, the switching stress and oscillation can be obviously reduced, and the EMI can be inhibited. However, the reduction in switching speed causes more switching losses and increases the switching time. 2) An RC buffer circuit is added. It is a common method to use an RC snubber circuit to suppress the switching stress, however, the large electrical stress is transferred to the RC circuit. On the other hand, the larger size of the RC absorption circuit increases energy loss, reducing system efficiency. 3) And optimizing the structural layout. Optimizing the device package and reducing the power loop stray inductance are the two leading approaches. However, new packaging techniques are costly and have a long time to market. In addition, in high power systems, the power loop structure is complex and not easily optimized.
Disclosure of Invention
The invention aims to provide a SiCSMOSFET gate drive voltage control circuit, which solves the problems of overshoot, oscillation, EMI and switching loss in the high-frequency application of the conventional high-power SiCSMOSFET.
Another object of the present invention is to provide a method for controlling gate driving voltage of a SiCMOSFET.
The first technical scheme adopted by the invention is that the SicMOSFET gate drive voltage control circuit is characterized by comprising an FPGA chip, wherein the FPGA chip is respectively connected with a gate drive stage, a current detection circuit and a voltage detection circuit;
the current detection circuit comprises a current rising edge detection circuit and a current falling edge detection circuit which are both connected with the FPGA chip, and the voltage detection circuit comprises a comparator CP sequentially connected with the FPGA chip3And a resistance-capacitance voltage division circuit.
The first technical solution of the present invention is also characterized in that,
the current rising edge detection circuit comprises a triode T1The collector and emitter of the triode are respectively connected with a resistor R3And a resistance R4Triode T1The collector of the circuit is also connected with a comparator CP2Triode T1And comparator CP2A resistor and a comparator CP are connected in series between2And a triode T connected with the FPGA chip1The base electrode of the triode T is grounded1A diode D is connected between the base electrode and the emitter electrode2；
The current falling edge detection circuit comprises a comparator CP sequentially connected with the FPGA chip1And a proportional voltage divider circuit.
The gate driving stage comprises two first gate drivers and two second gate drivers, the first gate drivers are connected with gate resistors, the FPGA chip is respectively connected with the input ends of the first gate drivers and the input ends of the second gate drivers, and the supply voltage of the first gate drivers is higher than that of the second gate drivers.
The first gate driver and the second gate driver are both type IXDN609 SIA.
The invention adopts a first technical scheme that a gate drive voltage control method of a SicMOSFET realizes voltage control through a SicMOSFET gate drive voltage control circuit in the first technical scheme of the invention, and specifically comprises the following steps:
the output end of the first gate driver is connected with the gate pole of the SicMOSFET through a gate resistance, the output end of the second gate driver is connected with the auxiliary source electrode of the SicMOSFET, and the input end of the proportional voltage division circuit and the resistor R are connected4Are all combined withThe power source electrode of the SiCMOS is connected, the drain-source electrode of the SiCMOS of the resistance-capacitance voltage division circuit is connected, and the FPGA chip is connected with the PWM signal;
when the accessed PWM signal is a PWM opening signal, the FPGA chip controls the gate drive stage to output a first gate drive voltage to charge the gate of the SicMOSFET, and the gate voltage of the SicMOSFET rises and reaches the threshold voltage V of the SicMOSFETTHWhen the current detection circuit detects that the circuit current starts to rise, the comparator CP2Generating a first level signal and sending the first level signal to the FPGA chip, wherein the FPGA chip delays the first level signal by a delay time t1The FPGA chip controls the gate drive stage to output a second drive voltage to charge the gate of the SicMOSFET, and when the voltage detection circuit detects that the drain-source voltage of the SicMOSFET is reduced to less than 10% of the bus voltage, the comparator CP3Generating a second electrical frequency signal and sending the second electrical level signal to the FPGA chip, wherein the FPGA chip controls the gate driving stage to output a third gate driving voltage, the third gate driving voltage is the same as the first gate driving voltage, and at the moment, the SiCMOSFET is completely conducted; the first gate drive voltage is positive, the value of the first gate drive voltage is equal to the value of the power supply voltage of the first gate driver, the second gate drive voltage is positive, and the second gate drive voltage is equal to the voltage difference between the power supply voltage of the first gate driver and the power supply voltage of the second gate driver;
when the accessed PWM signal is a PWM turn-off signal, the FPGA chip controls the gate drive stage to output a fourth gate drive voltage, the fourth gate drive voltage is negative, the gate voltage of the SiCMOSFET is reduced and reaches the voltage V of the Miller platformMillerWhen the voltage detection circuit detects that the circuit voltage rises to a bus voltage greater than 10%, the comparator CP3Generating a third level signal and sending the third level signal to the FPGA chip, wherein the FPGA chip delays the second level signal by a delay time t2Then, the FPGA chip controls the gate drive stage to output a fifth gate drive voltage, the fifth gate drive voltage is 0V, the circuit voltage continues to rise, when the circuit voltage is equal to the bus voltage, the circuit current drops, and when the current detection circuit detects that the circuit current is 0, the comparator CP1And generating a fourth level signal and sending the fourth level signal to the FPGA chip, wherein the FPGA chip controls the gate driving stage to output a sixth gate driving voltage, the sixth gate driving voltage is the same as the fourth gate driving voltage, and at the moment, the SiCMOSFET is completely switched off.
The second technical solution of the present invention is also characterized in that,
delay time t1And a delay time t2Respectively satisfy the following formulas:
Figure BDA0001849606430000041
Figure BDA0001849606430000042
in formulae (5) and (6), ton,1Is the rise time, t, of the current of the gate driving stage outputting the first gate driving voltageoff,2Is the fall time of the circuit current when the gate drive stage outputs the fourth gate drive voltage, EonRepresents the energy loss during the conduction of the SiCSMOSFET, EoffRepresents the energy loss during the turn-off of the SiCSMOSFET, IrrRepresents the current overshoot value V in the complete conduction process of the SiMOSFETosRepresenting the voltage overshoot value during the complete turn-off of the SiCMOSFET,
Figure BDA0001849606430000043
Figure BDA0001849606430000044
in the formulae (7) and (8), LloopIs the stray inductance, V, in the power loopDSRepresenting the drain-source voltage of the SiCMOSFET, t represents time,
Figure BDA0001849606430000045
represents the slope of the drain-source voltage waveform, L, of the SiCSMOSFETsIs parasitic inductance between the auxiliary source and the power source, ILRepresents a circuit load current equal to the circuit current when the SiCSMOSFET is fully turned on, and the energy loss due to the change in the slope of the drain-source voltage of the SiCSMOSFET is not significant, and therefore is considered to be a constant value, VDCRepresenting bus voltage, σsRepresenting the ratio of overvoltage to bus voltage, QrrRepresents the reverse recovery charge of the SiCSMOSFET, K represents the slope of the current waveform of the circuit, and
Figure BDA0001849606430000051
Figure BDA0001849606430000052
the slope K of the current waveform of the circuit is not a fixed value, in order to simplify calculation, only the change of the slope of the current waveform of the current is considered, and the changed K is equivalent to constant slopes K and K ', and K' are respectively expressed according to a current equivalent principle, namely:
Figure BDA0001849606430000053
Figure BDA0001849606430000054
in the formula (11), K1、K2In order to output the first gate driving voltage and the second gate driving voltage, the slope of the current waveform of the circuit is expressed by K in equation (12)3、K4The slope of the waveform of the circuit current is obtained when the fourth gate driving voltage and the fifth gate driving voltage are output.
The control method has the advantages that the SiCMOSFET gate driving voltage control circuit is simple and efficient, in the switching process of the SiCMOSFET, according to the feedback signal of the detection circuit, the smaller gate driving voltage is used in the current and voltage stages, and the problems of overshoot, oscillation, EMI and the like in the high-frequency application of the high-power SiCMOSFET are effectively inhibited.
Drawings
FIG. 1 is a circuit diagram of a SiCSMOSFET gate drive voltage control circuit of the present invention.
In the figure, 1, an FPGA chip, 2, a gate driving stage, 3, a current detection circuit and 4, a voltage detection circuit are provided.
Detailed Description
The invention is described in detail below with reference to specific embodiments and the accompanying drawings.
The SiCMOS gate drive voltage control circuit comprises an FPGA chip 1, wherein the FPGA chip 1 is respectively connected with a gate drive stage 2, a current detection circuit 3 and a voltage detection circuit 4;
the current detection circuit 3 comprises a current rising edge detection circuit and a current falling edge detection circuit which are both connected with the FPGA chip 1, and the voltage detection circuit 4 comprises a comparator CP sequentially connected with the FPGA chip 13And a resistance-capacitance voltage division circuit.
The current rising edge detection circuit comprises a triode T1The collector and emitter of the triode are respectively connected with a resistor R3And a resistance R4Triode T1The collector of the circuit is also connected with a comparator CP2Triode T1And comparator CP2A resistor and a comparator CP are connected in series between2And a triode T connected with the FPGA chip 11The base electrode of the triode T is grounded1A diode D is connected between the base electrode and the emitter electrode2；
The current falling edge detection circuit comprises a comparator CP sequentially connected with the FPGA chip 11And a proportional voltage divider circuit.
The gate driver stage comprises two first gate drivers and two second gate drivers, the models of the first gate drivers and the second gate drivers are IXDN609SIA, the first gate drivers are connected with gate resistors, the FPGA chip 1 is respectively connected with the input ends of the first gate drivers and the second gate drivers, and the supply voltage of the first gate drivers is higher than that of the second gate drivers.
The invention discloses a method for controlling gate drive voltage of a SicMOSFET, which realizes voltage control through the SicMOSFET gate drive voltage control circuit, and specifically comprises the following steps:
the output end of the first gate driver is connected with the gate pole of the SicMOSFET through a gate resistance, the output end of the second gate driver is connected with the auxiliary source electrode of the SicMOSFET, and the input end of the proportional voltage division circuit and the resistor R are connected4The power source electrodes of the SiCMOS are connected, the drain-source electrodes of the SiCMOS of the resistance-capacitance voltage division circuit are connected, and the FPGA chip 1 is connected with a PWM signal;
when the accessed PWM signal is a PWM opening signal, the FPGA chip 1 controls the gate drive stage 2 to output a first gate drive voltage to charge the gate of the SicMOSFET, and the gate voltage of the SicMOSFET rises and reaches the threshold voltage V of the SicMOSFETTHWhen the current detection circuit 3 detects that the circuit current starts to rise, the comparator CP2Generating a first level signal and sending the first level signal to the FPGA chip 1, wherein the FPGA chip 1 delays the first level signal by a delay time t1The FPGA chip 1 controls the gate drive stage 2 to output a second drive voltage to charge the gate of the SicMOSFET, and when the voltage detection circuit 4 detects that the drain-source voltage of the SicMOSFET is reduced to be less than 10% of the bus voltage, the comparator CP3Generating a second electrical frequency signal and sending the second electrical frequency signal to the FPGA chip 1, wherein the FPGA chip 1 controls the gate driving stage 2 to output a third gate driving voltage, the third gate driving voltage is the same as the first gate driving voltage, and at the moment, the SiCMOSFET is completely switched on; the first gate drive voltage is positive, the value of the first gate drive voltage is equal to the value of the power supply voltage of the first gate driver, the second gate drive voltage is positive, and the second gate drive voltage is equal to the voltage difference between the power supply voltage of the first gate driver and the power supply voltage of the second gate driver;
when the accessed PWM signal is a PWM turn-off signal, the FPGA chip 1 controls the gate drive stage 2 to output a fourth gate drive voltage, the fourth gate drive voltage is negative, the gate voltage of the SiCMOSFET is reduced and reaches the voltage V of the Miller platformMillerWhen voltage is detectedWhen the circuit 4 detects that the circuit voltage rises to the bus voltage of more than 10%, the comparator CP3Generating a third level signal and sending the third level signal to the FPGA chip 1, wherein the FPGA chip 1 delays the second level signal by a delay time t2Then, the FPGA chip 1 controls the gate drive stage 2 to output a fifth gate drive voltage, the fifth gate drive voltage is 0V, the circuit voltage continues to rise, when the circuit voltage is equal to the bus voltage, the circuit current drops, and the current detection circuit 3 detects that the circuit current is 0, the comparator CP1And generating a fourth level signal and sending the fourth level signal to the FPGA chip 1, wherein the FPGA chip 1 controls the gate driving stage 2 to output a sixth gate driving voltage, the sixth gate driving voltage is the same as the fourth gate driving voltage, and at the moment, the SiCSMOSFET is completely turned off.
Delay time t1And a delay time t2Respectively satisfy the following formulas:
Figure BDA0001849606430000081
Figure BDA0001849606430000082
in formulae (5) and (6), ton,1Is the rise time, t, of the circuit current when the gate drive stage outputs the first gate drive voltageoff,2Is the fall time of the circuit current when the gate drive stage outputs the fourth gate drive voltage, EonRepresents the energy loss during the conduction of the SiCSMOSFET, EoffRepresents the energy loss during the turn-off of the SiCSMOSFET, IrrRepresents the current overshoot value V in the complete conduction process of the SiMOSFETosRepresenting the voltage overshoot value during the complete turn-off of the SiCMOSFET,
Figure BDA0001849606430000083
Figure BDA0001849606430000084
in the formulae (7) and (8), LloopIs the stray inductance, V, in the power loopDSRepresenting the drain-source voltage of the SiCMOSFET, t represents time,
Figure BDA0001849606430000085
represents the slope of the drain-source voltage waveform, L, of the SiCSMOSFETsIs parasitic inductance between the auxiliary source and the power source, ILRepresents a circuit load current equal to the circuit current when the SiCSMOSFET is fully turned on, and the energy loss due to the change in the slope of the drain-source voltage of the SiCSMOSFET is not significant, and therefore is considered to be a constant value, VDCRepresenting bus voltage, σsRepresenting the ratio of overvoltage to bus voltage, QrrRepresents the reverse recovery charge of the SiCSMOSFET, K represents the slope of the current waveform of the circuit, and
Figure BDA0001849606430000086
Figure BDA0001849606430000087
Figure BDA0001849606430000091
the slope K of the current waveform of the circuit is not constant, in order to simplify calculation, only the change of the slope of the current waveform is considered, and the changed K is equivalent to constant slopes K and K 'according to the current equivalence principle, wherein the constant slopes K and K' are respectively expressed as follows:
Figure BDA0001849606430000092
Figure BDA0001849606430000093
in the formula (11), K1、K2In order to output the first gate driving voltage and the second gate driving voltage, the slope of the current waveform of the circuit is expressed by K in equation (12)3、K4The slope of the waveform of the circuit current is obtained when the fourth gate driving voltage and the fifth gate driving voltage are output.
Example (b):
in the method for controlling the gate driving voltage of the SiCMOSFET of this embodiment, the method implements voltage control by the above-mentioned gate driving voltage control circuit of the SiCMOSFET of the present invention, wherein the first gate driver has a supply voltage of 20V, and the second gate driver has a supply voltage of 5V, and specifically includes the following steps:
the output end of the first gate driver is connected with the gate pole of the SicMOSFET through a gate resistance, the output end of the second gate driver is connected with the auxiliary source electrode of the SicMOSFET, and the input end of the proportional voltage division circuit and the resistor R are connected4The power source electrodes of the SiCMOS are connected, the drain-source electrodes of the SiCMOS of the resistance-capacitance voltage division circuit are connected, and the FPGA chip 1 is connected with a PWM signal;
when the accessed PWM signal is a PWM opening signal, the FPGA chip 1 controls the gate driving stage 2 to output +20V to charge the gate of the SicMOSFET, and the gate voltage of the SicMOSFET rises and reaches the threshold voltage V of the SicMOSFETTHWhen the current detection circuit 3 detects that the circuit current starts to rise, the comparator CP2Generating a first level signal and sending the first level signal to the FPGA chip 1, wherein the FPGA chip 1 delays the first level signal by a delay time t1When the voltage detection circuit 4 detects that the drain-source voltage of the SicMOSFET is reduced to less than 10% of the bus voltage, the comparator CP3Generating a second electrical frequency signal and sending the second electrical level signal to the FPGA chip 1, wherein the FPGA chip 1 controls the first gate driver to output +20V, the second gate driver outputs 0V, namely, the gate driving voltage is output +20V, and at the moment, the SiCMOSFET is completely conducted;
when the accessed PWM signal is a PWM turn-off signal, the FPGA chip 1 controls the first gate driver to output 0V, the second gate driver outputs 5V, namely, the gate driving voltage is output to be-5V to discharge the gate of the SicMOSFET, and the gate voltage of the SicMOSFET is 20VBegins to fall and reaches the Miller plateau voltage VMillerWhen the voltage detection circuit 4 detects that the circuit voltage rises to the bus voltage of more than 10%, the comparator CP3Generating a third level signal and sending the third level signal to the FPGA chip 1, wherein the FPGA chip 1 delays the second level signal by a delay time t2After 110ns, the FPGA chip 1 controls the first gate driver to output 0V, and the second gate driver to output 0V, that is, the gate driver outputs 0V to discharge the gate of the SiCMOSFET, the circuit voltage continues to rise, when the circuit voltage is equal to the bus voltage, the circuit current drops, and when the current detection circuit 3 detects that the circuit current is 0, the comparator CP1And generating a fourth level signal and sending the fourth level signal to the FPGA chip 1, wherein the FPGA chip 1 controls the first gate driver to output 0V, the second gate driver outputs 5V, namely, the gate driving voltage is output to be-5V, and at the moment, the SiCSMOSFET is completely turned off.

Claims (5)

  1. The SiCMOS gate drive voltage control circuit is characterized by comprising an FPGA chip (1), wherein the FPGA chip (1) is respectively connected with a gate drive stage (2), a current detection circuit (3) and a voltage detection circuit (4);
    the current detection circuit (3) comprises a current rising edge detection circuit and a current falling edge detection circuit which are connected with the FPGA chip (1), and the voltage detection circuit (4) comprises a comparator CP sequentially connected with the FPGA chip (1)3And a resistance-capacitance voltage divider circuit;
    the current rising edge detection circuit comprises a triode T1Said triode T1Is connected with a resistor R3Said triode T1Is connected with a resistor R4Said triode T1The collector of the circuit is also connected with a comparator CP2Said triode T1And comparator CP2A resistor is connected in series between the two, and the comparator CP2And is connected with an FPGA chip (1), and the triode T1The base of the triode T is grounded, and the triode T1A diode D is connected between the base electrode and the emitter electrode2；
    The current falling edge detection circuitThe circuit comprises a comparator CP sequentially connected with the FPGA chip (1)1And a proportional voltage divider circuit;
    the gate driving stage comprises a first gate driver and a second gate driver, the output end of the first gate driver is connected with the gate of the SiC MOSFET through a gate resistor, the output end of the second gate driver is connected with the auxiliary source of the SiC MOSFET, and the input end of the proportional voltage division circuit and the resistor R are connected4Are all connected with the power source electrode of the SiC MOSFET, the resistance-capacitance voltage division circuit is connected with the drain electrode of the SiC MOSFET, and the resistor R4The other end passes through a diode D2The FPGA chip (1) is connected with the input ends of the first gate driver and the second gate driver respectively, and the power supply voltage of the first gate driver is higher than that of the second gate driver.
  2. 2. The SiC MOSFET gate drive voltage control circuit of claim 1, wherein the first gate driver and the second gate driver are each of type IXDN609 SIA.
  3. A gate drive voltage control method of a SiC MOSFET, which implements voltage control by the SiC MOSFET gate drive voltage control circuit of claim 1, comprising the steps of:
    the output end of the first gate driver is connected with the gate electrode of the SiC MOSFET through a gate electrode resistor, the output end of the second gate driver is connected with the auxiliary source electrode of the SiC MOSFET, and the input end of the proportional voltage division circuit and the resistor R are connected4Are all connected with the power source electrode of the SiC MOSFET, the resistance-capacitance voltage division circuit is connected with the drain electrode of the SiC MOSFET, and the resistor R4The other end passes through a diode D2The FPGA chip (1) is grounded and is connected with a PWM signal;
    when the accessed PWM signal is a PWM opening signal, the FPGA chip (1) controls the gate drive stage (2) to output a first gate drive voltage to charge the gate of the SiC MOSFET, and the gate voltage of the SiC MOSFET rises and reaches the threshold voltage V of the SiC MOSFETTHThe current detecting electricityWhen way (3) detects that the circuit current starts to rise, comparator CP2Generating a first level signal and sending the first level signal to the FPGA chip (1), wherein the FPGA chip (1) delays the first level signal for a delay time t1The FPGA chip (1) controls the gate drive stage (2) to output a second drive voltage to charge the gate of the SiC MOSFET, and when the voltage detection circuit (4) detects that the drain-source voltage of the SiC MOSFET is reduced to be less than 10% of the bus voltage, the comparator CP3Generating a second level signal and sending the second level signal to the FPGA chip (1), wherein the FPGA chip (1) controls the gate driving stage (2) to output a third gate driving voltage, the third gate driving voltage is the same as the first gate driving voltage, and at the moment, the SiC MOSFET is completely switched on; the first gate drive voltage is positive, the value of the first gate drive voltage is equal to the value of the power supply voltage of the first gate driver, the second gate drive voltage is positive, and the second gate drive voltage is equal to the voltage difference between the power supply voltage of the first gate driver and the power supply voltage of the second gate driver;
    when the accessed PWM signal is a PWM turn-off signal, the FPGA chip (1) controls the gate drive stage (2) to output a fourth gate drive voltage, the fourth gate drive voltage is negative, the gate voltage of the SiC MOSFET is reduced and reaches the Miller platform voltage VMillerWhen the voltage detection circuit (4) detects that the drain-source voltage of the SiC MOSFET rises to a bus voltage of more than 10%, the comparator CP3Generating a third level signal and sending the third level signal to the FPGA chip (1), wherein the FPGA chip (1) delays the third level signal for a delay time t2Then, the FPGA chip (1) controls the gate drive stage (2) to output a fifth gate drive voltage, the fifth gate drive voltage is 0V, the drain-source voltage of the SiC MOSFET continues to rise, when the drain-source voltage of the SiC MOSFET is equal to the bus voltage, the drain-source current of the SiC MOSFET falls, and when the current detection circuit (3) detects that the drain-source current of the SiC MOSFET is 0, the comparator CP1Generating a fourth level signal and sending the fourth level signal to the FPGA chip (1), wherein the FPGA chip (1) controls the gate drive stage (2) to output a sixth gate drive voltage, the sixth gate drive voltage is the same as the fourth gate drive voltage,at this time, the SiC MOSFET is completely turned off.
  4. 4. The method of claim 3 wherein the delay time t is a time period t1And a delay time t2Respectively satisfy the following formulas:
    Figure FDA0002537690380000031
    Figure FDA0002537690380000032
    in formulae (5) and (6), ton,1Is the rise time, t, of the current of the gate driving stage outputting the first gate driving voltageoff,2Is the fall time of the current of the gate drive stage outputting the fourth gate drive voltage circuit, EonRepresents the energy loss during the conduction of the SiC MOSFET, EoffRepresents the energy loss during the turn-off of the SiC MOSFET, IrrRepresents the current overshoot value, V, of the SiC MOSFET in the complete conduction processosIndicating the voltage overshoot value during the complete turn-off of the SiC MOSFET,
    Figure FDA0002537690380000041
    Figure FDA0002537690380000042
    in the formulae (7) and (8), LloopIs the stray inductance, V, in the power loopDSRepresenting the drain-source voltage of the SiC MOSFET, t represents time,
    Figure FDA0002537690380000043
    represents the slope, L, of the drain-source voltage waveform of a SiC MOSFETsIs parasitic inductance between the auxiliary source and the power source, ILRepresents the circuit load current when the SiC MOSFET is fully onSince the energy loss due to the change in the slope of the drain-source voltage of the SiC MOSFET is not significant, it is considered to be a constant value, V, equal to the circuit currentDCRepresenting bus voltage, σsRepresenting the ratio of overvoltage to bus voltage, QrrRepresents the reverse recovery charge of the SiC MOSFET, K represents the slope of the current waveform of the circuit, and
    Figure FDA0002537690380000044
    Figure FDA0002537690380000045
  5. 5. the method of claim 4, wherein the slope K of the current waveform of the circuit is not a constant value, and for the sake of simplicity, only the change of the current waveform slope is considered, and the changed K is equivalent to K and K 'of constant slope according to the current equivalence principle, wherein K and K' are respectively expressed as follows:
    Figure FDA0002537690380000046
    Figure FDA0002537690380000047
    in the formula (11), K1、K2In order to output the first gate driving voltage and the second gate driving voltage, the slope of the current waveform of the circuit is expressed by K in equation (12)3、K4The slope of the waveform of the circuit current is obtained when the fourth gate driving voltage and the fifth gate driving voltage are output.
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