CN112821730B - Novel driving topology, driving method thereof and crosstalk suppression method - Google Patents
Novel driving topology, driving method thereof and crosstalk suppression method Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 27
- 230000001629 suppression Effects 0.000 title claims abstract description 15
- 229910010271 silicon carbide Inorganic materials 0.000 claims abstract description 80
- 238000001514 detection method Methods 0.000 claims abstract description 42
- 239000004065 semiconductor Substances 0.000 claims abstract description 8
- 230000005669 field effect Effects 0.000 claims abstract description 7
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 7
- -1 silicon carbide metal-oxide Chemical class 0.000 claims abstract description 6
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 73
- 238000002955 isolation Methods 0.000 claims description 18
- 230000009471 action Effects 0.000 claims description 12
- 230000000630 rising effect Effects 0.000 claims description 12
- 230000008859 change Effects 0.000 claims description 5
- 230000003071 parasitic effect Effects 0.000 abstract description 11
- 230000001052 transient effect Effects 0.000 abstract description 6
- 230000010355 oscillation Effects 0.000 abstract description 4
- 230000002401 inhibitory effect Effects 0.000 abstract description 3
- 239000008186 active pharmaceutical agent Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000003750 conditioning effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000010248 power generation Methods 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The invention discloses a novel driving topology, a driving method thereof and a crosstalk suppression method, which are applicable to a silicon carbide metal-oxide semiconductor field effect transistor of a half-bridge circuit. The invention determines the next multi-level pulse signal according to the feedback information of the detection circuit, can detect the feedback self-adaption to optimize the turn-off characteristic, and effectively eliminates the influence of the hardware delay of the inherent detection circuit of the detection circuit by performing subtraction operation through the secondary side logic control unit, thereby inhibiting the turn-off transient oscillation and voltage overshoot of the switching tube of the half-bridge circuit. When the driving tube acts, the influence of crosstalk is restrained by adjusting the grid-source electrode level of the driven tube, so that parasitic turn-on and grid-source electrode negative voltage overshoot are prevented, and the use reliability and service life of the device are improved.
Description
Technical Field
The invention relates to the technical field of power electronics, in particular to a novel driving topology of a SiC MOSFET (metal oxide semiconductor field effect transistor) suitable for a half-bridge circuit, a driving method thereof and a crosstalk suppression method.
Background
Nowadays, for high-power applications, widely-used switching devices include an IGBT module and a SiC MOSFET power module, which are composed of a silicon IGBT and a fast recovery diode, and SiC MOSFETs made of silicon carbide semiconductor materials can achieve the following advantages: under the condition of high breakdown field intensity, higher-level doping is realized, so that the on-resistance is smaller, the on-loss can be reduced under the same power level, and the system efficiency is improved. Switching loss can be reduced, and the efficiency of the converter is improved; the carrier drift velocity of the SiC MOSFET is high, and the drift velocity of 4H-SiC is twice that of Si. Furthermore, it can realize higher switching frequency, high frequency of working frequency, and miniaturization of peripheral devices; siC MOSFETs are more thermally conductive, which will also further reduce the bulk of the heat dissipation system. Simplifying the heat dissipation facility. The current mass-produced SiC MOSFET power module is widely applied to power supplies and photovoltaic power generation occasions in the industrial field, the inside of the SiC MOSFET power module is mostly of a two-in-one structure of a half-bridge circuit, and the module structure can optimize internal parasitic inductance.
However, the SiC MOSFET may cause deterioration of the switching characteristics, and the high frequency switching causes a high current change rate di/dt, which may cause the lumped stray inductance L lump to generate an induced voltage during the off-phase, and to be superimposed on the bus voltage, so that the tube is subjected to a larger drain-source voltage, i.e., an off-voltage overshoot, in the transient state. An active driving strategy can be adopted to realize multi-stage turn-off and reduce di/dt of the turn-off process. An open-loop active drive control method, such as variable drive voltage type multi-level active drive, is adopted, a sampling circuit and a feedback circuit are not required to be arranged, and the influence of hardware inherent delay is avoided, but the open-loop active drive has poor adaptability to the influence of device parameter changes, such as temperature changes, on the switching characteristics. The closed-loop active drive increases the detection of the state quantity of the power switch device, but because the on and off time of the SiC MOSFET is very short, compared with the closed-loop control of the IGBT, an active control method for high-speed control response is temporarily lacking.
The high frequency switch causes high voltage change rates dv/dt, which act on parasitic capacitance of the SiC MOSFET to cause bridge arm crosstalk, and specifically, the embodiment is that, for example, the upper-bridge arm SiC MOSFET is turned on or off in a transient state, charges stored in the SiC MOSFET transfer capacitor C GD of the upper-bridge arm SiC MOSFET are transferred through the gate source, and positive or negative crosstalk voltage is induced at the gate of the lower-bridge arm SiC MOSFET.
The absolute value of a specific crosstalk voltage spike can be estimated by the following formula, where I CGD represents the displacement current, C GD is the gate-drain capacitance, C GS is the gate-source capacitance, and V DS is the active pipe drain-source voltage:
When the forward crosstalk voltage exceeds the SiC MOSFET turn-on threshold voltage, there is a risk of arm through. When the negative crosstalk voltage exceeds the negative maximum gate-source voltage value specified by the data sheet of the SiC MOSFET, the device is at risk of damage, and higher negative pressures can shorten the lifetime of the device. When a gate dc negative bias is applied for a long period of time, the threshold voltage is lowered, which further increases the occurrence probability of parasitic turn-on.
The existing mode of crosstalk suppression of the bridge structure of the SiC MOSFET mainly comprises the following three modes:
(1) C GS capacitors are additionally connected in parallel between the grid and the source, and grid source capacitance reactance is increased.
(2) When the active tube is turned on, the source electrode potential of the passive tube is raised by using a proper negative pressure as the turn-off voltage, so that the selected negative pressure is ensured to be smaller than the threshold voltage V GS of the SiC MOSFET after the raised voltage is superposed. However, at the moment of turning off the active tube, the negative voltage is selected to be superimposed with the negative lifting voltage, so that the SiC MOSFET is subjected to a larger negative gate-source voltage, and needs to be suppressed.
(3) Using the miller clamp function, the SiC MOSFET gate-source voltage is ensured to be clamped at 0V.
The above methods all realize crosstalk suppression by adding an electronic device to a gate source, and the device is not easy to replace once being manufactured by welding, in other words, the crosstalk suppression can be performed according to special situations, but the crosstalk suppression under various working conditions cannot be realized by the design.
In order to solve the problem of the SiC MOSFET applied in the half-bridge circuit, a novel driving topology, a driving method and a crosstalk suppression method suitable for a half-bridge silicon carbide metal-oxide semiconductor field effect transistor (SiC MOSFET) module are provided.
Disclosure of Invention
The invention aims to provide a novel driving topology, a driving method and a crosstalk suppression method which are suitable for a half-bridge silicon carbide metal-oxide semiconductor field effect transistor (SiC MOSFET) module, wherein the effect of effectively suppressing off transient voltage overshoot and oscillation is achieved by setting a desired output gate source signal waveform, and the effect of effectively suppressing crosstalk is also achieved by setting a passive pipe output gate source signal waveform during the action of a driving pipe.
In order to achieve the above purpose, the technical scheme of the invention is as follows:
The novel driving topology is applicable to a silicon carbide metal-oxide semiconductor field effect transistor of a half-bridge circuit and comprises a primary side logic processing unit, an upper bridge arm isolation unit, a lower bridge arm isolation unit, an upper bridge arm secondary side logic processing unit, a lower bridge arm secondary side logic processing unit, an upper bridge arm multi-level driving circuit, a lower bridge arm multi-level driving circuit, an upper bridge arm driving resistor network, a lower bridge arm driving resistor network, an upper bridge arm turn-off drain current detection feedback circuit and a lower bridge arm turn-off drain current detection feedback circuit;
The primary side logic processing unit comprises a first output end and a second output end;
the output end of the upper bridge arm secondary side logic processing unit is connected to the input end of an upper bridge arm multi-level driving circuit, the output end of the upper bridge arm multi-level driving circuit is connected to the grid electrode of a first SiC MOSFET through an upper bridge arm driving resistor network, the power source electrode of the first SiC MOSFET is connected to the input end of an upper bridge arm turn-off drain current detection feedback circuit, and the output end of the upper bridge arm turn-off drain current detection feedback circuit is connected to the upper bridge arm secondary side logic processing unit;
The second output end is connected to the input end of the lower bridge arm isolation unit, the output end of the lower bridge arm isolation unit is connected to the input end of the lower bridge arm secondary side logic processing unit, the output end of the lower bridge arm secondary side logic processing unit is connected to the input end of the lower bridge arm multi-level driving circuit, the output end of the lower bridge arm multi-level driving circuit is connected to the grid electrode of the second SiC MOSFET through a lower bridge arm driving resistor network, the power source electrode of the second SiC MOSFET is connected to the input end of the lower bridge arm turn-off drain current detection feedback circuit, and the output end of the lower bridge arm turn-off drain current detection feedback circuit is connected to the lower bridge arm secondary side logic processing unit;
the information stream 1 is input from the input end of the primary side logic processing unit, and the information streams 2_H and 2_L with the same signals are output in a shunting way through the primary side logic processing unit;
The upper bridge arm isolation unit receives the information flow 2_H and outputs an information flow 3_H, the upper bridge arm secondary side logic processing unit receives the information flow 3_H and outputs a voltage selection enabling information flow 4_H, the upper bridge arm multi-level driving circuit receives the information flow 4_H and outputs a multi-level driving signal V GG_H with enough driving power, the signal V GG_H is input into a grid electrode of a first SiC MOSFET through an upper bridge arm driving resistor network, the upper bridge arm turn-off drain current detection feedback circuit collects an induced voltage V sense_H generated by the fact that drain current changes when the first SiC MOSFET is turned off and acts on an inductor or a coil, the induced voltage V sense_H is calculated in proportion, the calculated induced voltage k is compared with a start threshold voltage V ref1 and a stop threshold voltage V ref2 respectively, the upper bridge arm multi-level driving circuit inputs a feedback signal FB_H to the secondary side logic processing unit through a rising edge and a falling edge mode, and the upper bridge arm secondary side logic processing unit generates an output information flow 4_H according to the feedback signal FB_H and the information flow 3_H;
The lower bridge arm isolation unit receives the information flow 2_l and outputs an information flow 3_L, the lower bridge arm secondary side logic processing unit receives the information flow 3_L and outputs a voltage selection enabling information flow 4_L, the lower bridge arm multi-level driving circuit receives the information flow 4_L and outputs a multi-level driving signal V GG_L with enough driving power, the signal V GG_L is input into a grid electrode of the second SiC MOSFET through a lower bridge arm driving resistor network, the lower bridge arm turn-off drain current detection feedback circuit collects an induced voltage V sense_L generated by the fact that drain current changes when the second SiC MOSFET is turned off and acts on an inductor or a coil, the induced voltage V sense_L is calculated in proportion, the calculated induced voltage k is compared with a start threshold voltage V ref1 and a stop threshold voltage V ref2 respectively, a feedback signal FB_L is input to the lower bridge arm secondary side logic processing unit through a mode of rising edge and a falling edge, and the lower secondary side logic processing unit generates an output information flow 4_L according to the feedback signal FB_L and the information flow 3_L.
Preferably, the primary side logical processing unit performs an interlock protection on the information stream 2_h and the information stream 2_l.
Preferably, the information flows 3_H and 4_H are information flows with the source of the first SiC MOSFET as the reference ground; the information flow 4_L is an information flow with the source of the second SiC MOSFET as a reference ground.
Preferably, the output determination condition of the feedback signal is:
1) If and only if the calculated induced voltage is greater than the starting threshold voltage, the feedback signal jumps from low level to high level to generate a rising edge;
2) If and only if the scaled induced voltage is less than the termination threshold voltage, the feedback signal goes from high to low, producing a falling edge.
The invention provides a driving method of a novel driving topology, which comprises the following steps:
step one, initializing an active gate driver;
Step two, the initial pulse signal is connected into a driving resistor network to operate, when the information flow 3 generates turn-off pulse signal jump, the counter 1 of the secondary side logic control unit starts to count;
Step three, when the drain current starts to drop rapidly, if the induced voltage k is greater than V ref1, the feedback signal outputs high level from low level, and after the secondary logic control unit detects the rising edge output by the window comparator, the counter 2 of the secondary logic control unit starts to count;
step four, when the drain current drops rapidly to 0, if the induced voltage k×v sense is smaller than V ref2, the feedback signal jumps from high level to low level, after the secondary side logic control unit detects the output falling edge of the window comparator, the secondary side logic unit counter 1 and counter 2 stop counting, the count value m of the counter 1, the count value n of the counter 2 and the count value p corresponding to the inherent delay of the detection feedback loop are recorded;
Step six, refreshing pulse configuration: the working step length of the secondary side logic unit is d, the optimal intermediate level starting action time t B1 is d (m-n-p) after the turn-off pulse, the optimal level action ending time t S1 is d (n-p) after the optimal intermediate level starting action time, the upper limit of turn-off loss and the lower limit of turn-off voltage peak are set, and the turn-off optimal intermediate level V BMV is selected according to the upper limit.
The invention provides a novel driving topology crosstalk suppression method, which comprises a first SiC MOSFET on stage and a first SiC MOSFET off stage;
first SiC MOSFET on phase:
The logic control unit of the secondary side of the lower bridge arm receives the first SiC MOSFET starting information of the information flow 3, immediately reduces the output end level V GG_L of the multi-level driving circuit of the lower bridge arm, wherein the reduced level value ranges from 0 to the highest bearable negative pressure value of the grid source of the second SiC MOSFET, the drain-source voltage is reduced to a certain moment after the on-state voltage drop, and the level V GG_L is reset to the driving negative voltage V EE;
The first SiC MOSFET off phase:
the lower bridge arm secondary side logic control unit receives the first SiC MOSFET turn-off information of the information flow 3, then increases the output end level V GG_L of the lower bridge arm multi-level driving circuit, the increased level value range is from 0 to the sum of the absolute value of the threshold voltage V TH and the driving negative voltage V EE, the drain-source voltage rises to a certain moment after the bus voltage, and the level V GG_L is reset to the driving negative voltage V EE.
The beneficial effects of the invention are as follows:
1. The invention determines the next multi-level pulse signal according to the feedback information of the detection circuit, can detect the feedback self-adaption to optimize the turn-off characteristic, and can effectively eliminate the influence of the hardware delay of the inherent detection circuit of the detection circuit by performing subtraction operation through the secondary side logic control unit, thereby inhibiting the turn-off transient oscillation and voltage overshoot of the switching tube of the half-bridge circuit.
2. The invention can restrain the influence of crosstalk by adjusting the grid-source electrode level of the driven tube when the driving tube acts on the premise of not influencing the switching speed, thereby preventing parasitic turn-on and grid-source electrode negative pressure overshoot, and further improving the use reliability and service life of the device.
Drawings
Fig. 1 is a schematic diagram of a novel driving topology of a half-bridge SiC MOSFET according to an embodiment of the present invention;
FIG. 2 is a flow chart of a driving method of a novel driving topology according to an embodiment of the present invention;
fig. 3 is a schematic diagram of an analysis model of a SiC MOSFET in a novel driving topology driving method of a half-bridge SiC MOSFET according to an embodiment of the present invention;
Fig. 4 is a schematic diagram illustrating pulse generation of a novel driving topology driving method of a half-bridge SiC MOSFET according to an embodiment of the present invention;
fig. 5 is a schematic diagram of a half-bridge SiC MOSFET driving pulse for suppressing crosstalk according to an embodiment of the present invention.
Detailed Description
The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings.
As shown in fig. 1, the embodiment of the invention provides a novel driving topology of a half-bridge SiC MOSFET, which is applicable to a silicon carbide metal-oxide semiconductor field effect transistor of a half-bridge circuit, and includes a primary side logic processing unit lu_p, an upper bridge arm isolation unit H, a lower bridge arm isolation unit L, an upper bridge arm secondary side logic processing unit lu_h, a lower bridge arm secondary side logic processing unit lu_l, an upper bridge arm multi-level driving circuit a_h, a lower bridge arm multi-level driving circuit a_l, an upper bridge arm driving resistor network b_h, a lower bridge arm driving resistor network b_l, an upper bridge arm turn-off drain current detection feedback circuit c_h, and a lower bridge arm turn-off drain current detection feedback circuit c_l;
The primary side logic processing unit comprises a first output end and a second output end;
the output end of the upper bridge arm secondary side logic processing unit is connected to the input end of an upper bridge arm multi-level driving circuit, the output end of the upper bridge arm multi-level driving circuit is connected to the grid electrode of a first SiC MOSFET through an upper bridge arm driving resistor network, the power source electrode of the first SiC MOSFET is connected to the input end of an upper bridge arm turn-off drain current detection feedback circuit, and the output end of the upper bridge arm turn-off drain current detection feedback circuit is connected to the upper bridge arm secondary side logic processing unit;
The second output end is connected to the input end of the lower bridge arm isolation unit, the output end of the lower bridge arm isolation unit is connected to the input end of the lower bridge arm secondary side logic processing unit, the output end of the lower bridge arm secondary side logic processing unit is connected to the input end of the lower bridge arm multi-level driving circuit, the output end of the lower bridge arm multi-level driving circuit is connected to the grid electrode of the second SiC MOSFET through a lower bridge arm driving resistor network, the power source electrode of the second SiC MOSFET is connected to the input end of the lower bridge arm turn-off drain current detection feedback circuit, and the output end of the lower bridge arm turn-off drain current detection feedback circuit is connected to the lower bridge arm secondary side logic processing unit;
the information stream 1 is input from the input end of the primary side logic processing unit, and the information streams 2_H and 2_L with the same signals are output in a shunting way through the primary side logic processing unit;
The upper bridge arm isolation unit receives the information flow 2_H and outputs an information flow 3_H, the upper bridge arm secondary side logic processing unit receives the information flow 3_H and outputs a voltage selection enabling information flow 4_H, the upper bridge arm multi-level driving circuit receives the information flow 4_H and outputs a multi-level driving signal V GG_H with enough driving power, the signal V GG_H is input into a grid electrode of a first SiC MOSFET through an upper bridge arm driving resistor network, the upper bridge arm turn-off drain current detection feedback circuit collects an induced voltage V sense_H generated by the fact that drain current changes when the first SiC MOSFET is turned off and acts on an inductor or a coil, the induced voltage V sense_H is calculated in proportion, the calculated induced voltage k is compared with a start threshold voltage V ref1 and a stop threshold voltage V ref2 respectively, the upper bridge arm multi-level driving circuit inputs a feedback signal FB_H to the secondary side logic processing unit through a rising edge and a falling edge mode, and the upper bridge arm secondary side logic processing unit generates an output information flow 4_H according to the feedback signal FB_H and the information flow 3_H;
The lower bridge arm isolation unit receives the information flow 2_l and outputs an information flow 3_L, the lower bridge arm secondary side logic processing unit receives the information flow 3_L and outputs a voltage selection enabling information flow 4_L, the lower bridge arm multi-level driving circuit receives the information flow 4_L and outputs a multi-level driving signal V GG_L with enough driving power, the signal V GG_L is input into a grid electrode of the second SiC MOSFET through a lower bridge arm driving resistor network, the lower bridge arm turn-off drain current detection feedback circuit collects an induced voltage V sense_L generated by the fact that drain current changes when the second SiC MOSFET is turned off and acts on an inductor or a coil, the induced voltage V sense_L is calculated in proportion, the calculated induced voltage k is compared with a start threshold voltage V ref1 and a stop threshold voltage V ref2 respectively, a feedback signal FB_L is input to the lower bridge arm secondary side logic processing unit through a mode of rising edge and a falling edge, and the lower secondary side logic processing unit generates an output information flow 4_L according to the feedback signal FB_L and the information flow 3_L.
Preferably, the primary side logical processing unit performs an interlock protection on the information stream 2_h and the information stream 2_l.
Preferably, the information flows 3_H and 4_H are information flows with the source of the first SiC MOSFET as the reference ground; the information flow 4_L is an information flow with the source of the second SiC MOSFET as a reference ground.
Preferably, the output determination condition of the feedback signal is:
1) If and only if the calculated induced voltage is greater than the starting threshold voltage, the feedback signal jumps from low level to high level to generate a rising edge;
2) If and only if the scaled induced voltage is less than the termination threshold voltage, the feedback signal goes from high to low, producing a falling edge.
As shown in fig. 2, an embodiment of the present invention provides a driving method of a novel driving topology, including the following steps:
step one, initializing an active gate driver, which specifically comprises:
step 1, an analysis model of the turn-off characteristics of the SiC MOSFET is established according to the parameter information related to the turn-on characteristics of the used SiC MOSFET, as shown in fig. 3.
The switching characteristics of the SiC MOSFET include SiC MOSFET electrical characteristics and temperature characteristics including a threshold voltage V TH, a transfer capacitance C RSS, an output capacitance C OSS, an input capacitance C ISS, an on-state resistance R DSON, a drain current I DS when the internal gate resistance R G(INT)、VGS is 2 times the threshold voltage, a miller plateau transconductance g fs, and a junction temperature T J.
The parameter information comprises a driving loop parameter, a power loop parasitic parameter and a working condition voltage and current grade.
The drive loop parameters include drive positive voltage V CC, drive negative voltage V EE, turn-off intermediate level V BMV, external drive resistor R G(ext).
The power loop parasitic parameters include drain stray inductance L D, source stray inductance L S, loop parasitic inductance L LOOP, loop parasitic resistance R LOOP.
The voltage and current classes of the working conditions comprise bus voltage V DC and load current I L.
Step 2, solving an optimal intermediate level V BMV at the time of shutdown and a start action time t B1 of V BMV and an action end time t S1 of V BMV by using a shutdown characteristic analysis model, wherein the process is as follows:
In the off-delay stage, a start time t 0 and an end time t 1; at this stage, the Miller stage voltage V m1 is determined by the load current, and the gate voltage is calculated from V CC to V m1,t1
VDS(t)＝RDSon·IL
iD(t)＝IL
In the miller stage, a start time t 1 and an end time t 2; in this stage, since the gate-source voltage is kept at V m1, the driving power supply starts to charge with constant current C rss, and V DS reaches the bus voltage at time t 2, the drain-source voltage change charges the bridge arm to the output capacitor C oss, the actual drain current is reduced, and the calculation formula t 2 is
CRSS(t)＝intep1[VDS(t)]
t2＝solve[(VDS(t)＝VDC)]
In the above equation, int is the interpolation operator.
In the drain current falling phase, a start time t 2 and an end time t 3; at time t 3, V GS is reduced to V th,t3, and the formula is
Configuring an initial pulse signal:
Setting t 0 to t 2 to adopt V EE negative pressure to turn off; t 2 to t 3 are switched off with the optimal intermediate level V BMV voltage; after t 3, adopting V EE negative pressure to turn off;
Setting a detection start threshold voltage V ref1 and a detection end threshold voltage V ref2 of a detection feedback unit, wherein the setting of the threshold voltages is determined according to parasitic inductance or coil inductance between a power source and a signal source of the SiC MOSFET and dI D/dt of the expected turn-off of the SiC MOSFET device;
And setting the hardware delay compensation of the detection circuit of the secondary side logic control unit, wherein the compensation metering quantity p is related to the hardware delay time t delay of the detection circuit and the working frequency of the secondary side logic control unit.
And step two, the initial pulse signal is connected into a driving resistor network to operate, and when the information flow 3 generates turn-off pulse signal jump, the counter 1 of the secondary side logic control unit starts counting.
Step three, when the drain current starts to drop rapidly, if the induced voltage k×v sense is greater than V ref1, the feedback signal outputs a high level from a low level, and after the secondary logic control unit detects that the window comparator outputs a rising edge, the secondary logic control unit counter 2 starts to count.
And step four, when the drain current rapidly drops to 0, if the induced voltage k x V sense is smaller than V ref2, the feedback signal jumps from high level to low level, after the secondary side logic control unit detects that the window comparator outputs the falling edge, the secondary side logic unit counter 1 and the counter 2 stop counting, the count value m of the counter 1 is recorded, the count value n of the counter 2 is recorded, and the count value p corresponding to the inherent delay of the detection feedback loop is detected.
Step six, refreshing pulse configuration:
Setting the working step length of the secondary side logic unit as d, setting the optimal intermediate level starting action time t B1 as d (m-n-p) after the turn-off pulse, setting the optimal level action ending time t S1 as d (n-p) after the optimal intermediate level starting action time, setting the upper limit of turn-off loss and the lower limit of turn-off voltage peak, and selecting the turn-off optimal intermediate level V BMV according to the upper limit.
The conditioning effect of the SiC MOSFET for the pulse V GG is shown in fig. 4, and the next pulse configuration is obtained by executing the flowchart shown in fig. 2 according to the off current waveform of a certain SiC MOSFET, as shown in V GG_H* in fig. 4, by taking the upper arm SiC MOSFET as an example.
The invention determines the next multi-level pulse signal according to the feedback information of the detection circuit, can detect the feedback self-adaption to optimize the turn-off characteristic, and can effectively eliminate the influence of the hardware delay of the inherent detection circuit of the detection circuit by performing subtraction operation through the secondary side logic control unit, thereby inhibiting the turn-off transient oscillation and voltage overshoot of the switching tube of the half-bridge circuit.
The invention provides a novel driving topology crosstalk suppression method, the crosstalk suppression principle of which is shown in figure 5, and the novel driving topology crosstalk suppression method comprises a first SiC MOSFET on stage and a first SiC MOSFET off stage;
first SiC MOSFET on phase:
The lower bridge arm secondary side logic control unit receives the first SiC MOSFET starting information of the information flow 3, immediately reduces the output end level V GG_L of the lower bridge arm multi-level driving circuit, wherein the reduced level value ranges from 0 to the highest bearable negative pressure value of the second SiC MOSFET gate source, the drain-source voltage is reduced to a certain moment after the on-state voltage drop, and the V GG_L level is reset to the driving negative voltage V EE. In fig. 5, the decrease level value employed is 0.
The first SiC MOSFET off phase:
The lower bridge arm secondary side logic control unit receives the first SiC MOSFET turn-off information of the information flow 3, then increases the output end level V GG_L of the lower bridge arm multi-level driving circuit, the increased level value range is from 0 to the sum of the absolute value of the threshold voltage V TH and the driving negative voltage V EE, the drain-source voltage rises to a certain moment after the bus voltage, and the level V GG_L is reset to the driving negative voltage V EE. In fig. 5, the added level value is |v EE |.
The invention can restrain the influence of crosstalk by adjusting the grid-source electrode level of the driven tube when the driving tube acts on the premise of not influencing the switching speed, thereby preventing parasitic turn-on and grid-source electrode negative pressure overshoot, and further improving the use reliability and service life of the device.
The described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Claims (3)
1. The novel driving topology is suitable for a silicon carbide metal-oxide semiconductor field effect transistor of a half-bridge circuit and is characterized by comprising a primary side logic processing unit, an upper bridge arm isolation unit, a lower bridge arm isolation unit, an upper bridge arm secondary side logic processing unit, a lower bridge arm secondary side logic processing unit, an upper bridge arm multi-level driving circuit, a lower bridge arm multi-level driving circuit, an upper bridge arm driving resistor network, a lower bridge arm driving resistor network, an upper bridge arm turn-off drain current detection feedback circuit and a lower bridge arm turn-off drain current detection feedback circuit;
The primary side logic processing unit comprises a first output end and a second output end;
The output end of the upper bridge arm secondary side logic processing unit is connected to the input end of an upper bridge arm multi-level driving circuit, the output end of the upper bridge arm multi-level driving circuit is connected to the grid electrode of a first SiCMOSFET through an upper bridge arm driving resistor network, the power source electrode of the first SiCMOSFET is connected to the input end of an upper bridge arm turn-off drain current detection feedback circuit, and the output end of the upper bridge arm turn-off drain current detection feedback circuit is connected to the upper bridge arm secondary side logic processing unit;
the second output end is connected to the input end of the lower bridge arm isolation unit, the output end of the lower bridge arm isolation unit is connected to the input end of the lower bridge arm secondary side logic processing unit, the output end of the lower bridge arm secondary side logic processing unit is connected to the input end of the lower bridge arm multi-level driving circuit, the output end of the lower bridge arm multi-level driving circuit is connected to the grid electrode of the second SiCNOSFET through a lower bridge arm driving resistor network, the power source electrode of the second SiC MOSFET is connected to the input end of the lower bridge arm turn-off drain current detection feedback circuit, and the output end of the lower bridge arm turn-off drain current detection feedback circuit is connected to the lower bridge arm secondary side logic processing unit;
the information stream 1 is input from the input end of the primary side logic processing unit, and the information streams 2_H and 2_L with the same signals are output in a shunting way through the primary side logic processing unit;
The upper bridge arm isolation unit receives the information flow 2_H and outputs an information flow 3_H, the upper bridge arm secondary side logic processing unit receives the information flow 3_H and outputs a voltage selection enabling information flow 4_H, the upper bridge arm multi-level driving circuit receives the information flow 4_H and outputs a multi-level driving signal V GG_H with enough driving power, the signal V GG_H is input into a grid electrode of a first SiCNOSFET through an upper bridge arm driving resistor network, the upper bridge arm turn-off drain current detection feedback circuit collects an induced voltage V sense_H generated by the change of drain current acting on an inductor or a coil when the first SiCNOSFET is turned off, the induced voltage V sense_H is calculated in proportion, the calculated induced voltage k is compared with a start threshold voltage V ref1 and a stop threshold voltage V ref2 respectively, a feedback signal FB_H is input to the secondary side logic processing unit through a rising edge and a falling edge mode, and the upper bridge arm secondary side logic processing unit generates an output information flow 4_H according to the feedback signal FB_H and the information flow 3_H;
The lower bridge arm isolation unit receives the information flow 2_L and outputs an information flow 3_L, the lower bridge arm secondary side logic processing unit receives the information flow 3_L and outputs a voltage selection enabling information flow 4_L, the lower bridge arm multi-level driving circuit receives the information flow 4_L and outputs a multi-level driving signal V GG_L with enough driving power, the signal V GG_L is input into a grid electrode of a second SiCNOSFET through a lower bridge arm driving resistor network, the lower bridge arm turn-off drain current detection feedback circuit collects an induced voltage V sense_L generated by the change of drain current acting on an inductor or a coil when the second SiCNOSFET is turned off, the induced voltage V sense_L is calculated in proportion, the calculated induced voltage k is compared with a start threshold voltage V ref1 and a stop threshold voltage V ref2 respectively, a feedback signal FB_L is input to the lower bridge arm secondary side logic processing unit through a mode of rising edge and a falling edge, and the lower secondary side logic processing unit generates an output information flow 4_L according to the feedback signal FB_L and the information flow 3_L;
the primary side logic processing unit performs interlocking protection on the information stream 2_H and the information stream 2_L;
the information flows 3_H and 4_H are information flows with the source electrode of the first SiCMOSFET as the reference ground; the information flow 4_L is an information flow taking the source electrode of the second SiCMOSFET as the reference ground;
the output judging conditions of the feedback signals are as follows:
1) If and only if the calculated induced voltage is greater than the starting threshold voltage, the feedback signal jumps from low level to high level to generate a rising edge;
2) If and only if the scaled induced voltage is less than the termination threshold voltage, the feedback signal goes from high to low, producing a falling edge.
2. A method of driving a novel drive topology as recited in claim 1, comprising the steps of:
step one, initializing an active gate driver;
Step two, the initial pulse signal is connected into a driving resistor network to operate, when the information flow 3 generates turn-off pulse signal jump, the counter 1 of the secondary side logic control unit starts to count;
step three, when the drain current starts to drop rapidly, if the induced voltage k is greater than Vref1, the feedback signal outputs high level from low level, and after the secondary logic control unit detects the rising edge output by the window comparator, the counter 2 of the secondary logic control unit starts to count;
Step four, when the drain current drops rapidly to 0, if the induced voltage k×vsense is smaller than Vref2, the feedback signal jumps from high level to low level, after the secondary logic control unit detects the output falling edge of the window comparator, the secondary logic unit counter 1 and counter 2 stop counting, the count value m of counter 1, the count value n of counter 2, and the count value p corresponding to the inherent delay of the detection feedback loop are recorded;
Step six, refreshing pulse configuration: the working step length of the secondary side logic unit is d, the optimal intermediate level starting action time t B1 is d (m-n-p) after the turn-off pulse, the optimal level action ending time t S1 is d (n-p) after the optimal intermediate level starting action time, the upper limit of turn-off loss and the lower limit of turn-off voltage peak are set, and the turn-off optimal intermediate level V BMV is selected according to the upper limit.
3. The method of crosstalk suppression for a novel drive topology of claim 1, comprising a first SiCMOSFET on phase and a first SiCMOSFET off phase;
a first SiCNMOSFET on-phase:
The logic control unit of the secondary side of the lower bridge arm receives the first SiCNOSFET opening information of the information flow 3, then reduces the output end level V GG_L of the multi-level drive circuit of the lower bridge arm, the reduced level value ranges from 0 to the highest bearable negative voltage value of the grid source of the second SiCNOSFET, the drain-source voltage is reduced to a certain moment after the on-state voltage drop, and the level V GG_L is reset to the drive negative voltage V EE;
a first SiCMOSFET off phase:
The lower bridge arm secondary side logic control unit receives the first SiCNOSFET turn-off information of the information flow 3, then increases the output end level V GG_L of the lower bridge arm multi-level driving circuit, the increased level value range is from 0 to the sum of the absolute value of the threshold voltage V TH and the driving negative voltage V EE, the drain-source voltage rises to a certain moment after the bus voltage, and the level V GG_L is reset to the driving negative voltage V EE.
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| CN114094865A (en) * | 2021-11-12 | 2022-02-25 | 金琥新能源汽车(成都)有限公司 | Bridge arm crosstalk processing method and device, electronic equipment and storage medium |
| CN115622546B (en) * | 2022-12-14 | 2023-04-11 | 深圳平创半导体有限公司 | Method and device for reducing overshoot of grid voltage of power semiconductor device |
| CN116633331B (en) * | 2023-07-21 | 2023-10-20 | 成都铭科思微电子技术有限责任公司 | Switching circuit capable of switching positive and negative voltage complementary output |
| CN117650721B (en) * | 2024-01-30 | 2024-04-05 | 西安晶格慧力微电子有限公司 | Wide voltage multimode BLDC driving integrated circuit, application circuit and power consumption control method |
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