CN108270424B - Open-loop driving circuit for optimizing silicon carbide MOSFET (Metal-oxide-semiconductor field Effect transistor) on waveform - Google Patents
Open-loop driving circuit for optimizing silicon carbide MOSFET (Metal-oxide-semiconductor field Effect transistor) on waveform Download PDFInfo
- Publication number
- CN108270424B CN108270424B CN201810175507.9A CN201810175507A CN108270424B CN 108270424 B CN108270424 B CN 108270424B CN 201810175507 A CN201810175507 A CN 201810175507A CN 108270424 B CN108270424 B CN 108270424B
- Authority
- CN
- China
- Prior art keywords
- gate
- voltage
- turn
- resistor
- silicon carbide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 57
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 57
- 239000004065 semiconductor Substances 0.000 title abstract description 5
- 230000005669 field effect Effects 0.000 title abstract description 4
- 230000008859 change Effects 0.000 claims abstract description 46
- 230000000630 rising effect Effects 0.000 claims abstract description 33
- 238000013016 damping Methods 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims abstract description 23
- 230000008569 process Effects 0.000 claims abstract description 22
- 230000001052 transient effect Effects 0.000 claims abstract description 15
- 239000003990 capacitor Substances 0.000 claims description 59
- 101100393235 Caenorhabditis elegans gon-1 gene Proteins 0.000 claims description 35
- 101100482711 Caenorhabditis elegans gon-2 gene Proteins 0.000 claims description 21
- 230000007423 decrease Effects 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 10
- 238000001514 detection method Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000012053 enzymatic serum creatinine assay Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6877—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the control circuit comprising active elements different from those used in the output circuit
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
- H03K17/0814—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the output circuit
- H03K17/08142—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the output circuit in field-effect transistor switches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
- H03K2217/0036—Means reducing energy consumption
Landscapes
- Power Conversion In General (AREA)
- Electronic Switches (AREA)
Abstract
The invention discloses an open-loop driving circuit for optimizing a silicon carbide MOSFET (Metal-oxide-semiconductor field Effect transistor) on waveform, which comprises the following components: a driving voltage waveform generator for generating a driving voltage waveform of a preset rising edge; the variable gate drive resistor control circuit is used for controlling the magnitude of the gate drive resistor in different stages of the turn-on transient process, wherein the gate source voltage change rate of the silicon carbide MOSFET is consistent with the drive voltage rise change rate in the current rise stage so as to control the current rise change rate and the reverse current by controlling the drive voltage rise change rate; in the voltage dropping stage, the gate current is increased to accelerate the voltage dropping process and reduce the turn-on loss; in the stable conduction stage, the gate damping resistance is increased so as to inhibit the gate voltage overshoot without affecting the switching speed. The driving circuit has simple structure, easy realization and low cost, and can inhibit reverse current peak and gate voltage overshoot at the same time under the condition of reducing the turn-on loss.
Description
Technical Field
The invention relates to the technical field of power electronic circuits, in particular to an open-loop driving circuit for optimizing a silicon carbide MOSFET (metal oxide semiconductor field effect transistor) turn-on waveform.
Background
Silicon carbide MOSFETs are novel power semiconductors and currently have a certain distance from large-scale industrialization. Because the silicon carbide device has high switching speed, the gate voltage has serious gate oscillation and overshoot, the gate oxide layer can be broken down to cause permanent failure of the device, and serious electromagnetic interference and large open reverse current can be caused by large current change rate. Although CREE et al manufacturers provide a drive, the drive can only change the switching transient process of the silicon carbide MOSFET by changing the gate resistance, and can only balance the gate voltage overshoot and the switching loss, the switching speed and the switching loss, so that the optimized drive of the silicon carbide MOSFET is difficult to realize. The closed-loop driving circuit is commonly used for the optimized driving of a silicon IGBT (Insulated Gate Bipolar Transistor ), and requires an additional detection circuit and a feedback circuit, but because the silicon carbide MOSFET has high switching speed, the requirements on the bandwidth and the anti-interference capability of the detection circuit and the feedback circuit are very high, the implementation is complex, and the silicon carbide MOSFET is difficult to be used for engineering application.
The open loop driving circuit can optimize the turn-on waveform of the silicon carbide MOSFET without a detection circuit and a feedback circuit. Fig. 1 is an open loop driving circuit for a silicon carbide MOSFET, in which a larger resistor R gon is used during the current rising phase to control the current rising rate of change and the reverse current spike, and a delay circuit is used to control the switching transistor Qbst to turn on during the voltage falling phase, and an additional gate current is injected through a resistor Rbst to accelerate the voltage falling rate of change and reduce the turn-on loss. The working principle is as follows:
t0-t2: qbst is in an off-state, the drive voltage VCC charges the sum of the input capacitances C iss(Cgs and C gd of the silicon carbide MOSFET through the gate resistor R gon, and the control resistor R gon can control the current rising change rate and the reverse current;
t2-t3: the delay time is controlled to turn on Qbst at this stage, and the drive voltage VCC charges the gate through the gate resistors R gon and Rbst. The resistor Rbst branch produces additional gate current Igbst, which accelerates the voltage drop process and reduces turn-on loss.
The related art driving circuit can control the reverse current while optimizing the turn-on loss, but has the following drawbacks:
1) The delay time is fixed, and the method has a good optimizing effect only under specific load conditions;
2) The gate voltage overshoot is severe, and the gate voltage overshoot usually exists in the t3-t4 stage, where the gate damping resistance is the equivalent resistance of R gon and Rbst in parallel, the damping is smaller, and the gate voltage spike will be larger.
In summary, when the related art optimizes the turn-on waveform of the silicon carbide MOSFET, the related art is divided into two main types, i.e., closed-loop driving and open-loop driving. The closed-loop driving has the defects of complex circuit, high cost, easy interference of a detection circuit and the like. The open-loop driving circuit has the advantages of simple circuit, easy realization and the like, but the current open-loop driving is difficult to realize, and simultaneously, the reverse current peak and the gate voltage overshoot are restrained under the condition of optimizing the turn-on loss.
Disclosure of Invention
The present invention aims to solve at least one of the technical problems in the related art to some extent.
Therefore, the invention aims to provide an open-loop driving circuit for optimizing the turn-on waveform of a silicon carbide MOSFET, which has simple structure, easy realization and low cost, and can simultaneously inhibit reverse current spike and gate voltage overshoot under the condition of reducing turn-on loss.
To achieve the above objective, an embodiment of the present invention provides an open-loop driving circuit for optimizing a turn-on waveform of a silicon carbide MOSFET, including: a driving voltage waveform generator for generating a driving voltage waveform of a preset rising edge; the variable gate drive resistor control circuit is used for controlling the magnitude of the gate drive resistor in different stages of the turn-on transient process, wherein the gate source voltage change rate of the silicon carbide MOSFET is consistent with the drive voltage rise change rate in the current rise stage so as to control the current rise change rate and the reverse current by controlling the drive voltage rise change rate; in the voltage dropping stage, the gate current is increased to accelerate the voltage dropping process and reduce the turn-on loss; in the stable conduction stage, the gate damping resistance is increased so as to inhibit the gate voltage overshoot without affecting the switching speed.
The open-loop driving circuit for optimizing the turn-on waveform of the silicon carbide MOSFET can independently control transient processes of a current rising stage and a voltage falling stage, can increase the rising time of the capacitor voltage VC1 to control a reverse current peak, has small gate resistance, can accelerate the voltage falling transient process, reduces turn-on loss, breaks the contradiction between the reverse current peak and the turn-on loss under the traditional driving circuit, can inhibit gate voltage overshoot under the condition of not affecting the turn-on speed, and can inhibit the gate voltage overshoot by adding a larger gate resistance without affecting the transient process and without affecting the turn-on speed of the silicon carbide MOSFET.
In addition, the open-loop driving circuit for optimizing the turn-on waveform of the silicon carbide MOSFET according to the above embodiment of the present invention may further have the following additional technical features:
Further, in one embodiment of the present invention, the driving voltage waveform generator includes: a first capacitor C 1; an inductor L 1 and a first resistor R 1, where the inductor L 1 and the first resistor R 1 are connected in parallel to each other and are both connected to the first capacitor C 1 to charge the first capacitor C 1.
Further, in one embodiment of the present invention, the variable gate driving resistance control circuit includes: a first gate driving resistor R gon1 and a second gate driving resistor R gon2, wherein the resistance value of the second gate driving resistor R gon2 is greater than the resistance value of the first gate driving resistor R gon1; and a MOS transistor MOSon, wherein the MOS transistor MOSon is in an on state during the current rising stage and the voltage falling stage, the gate resistance is the first gate driving resistance R gon1, and the MOS transistor MOSon is in an off state during the stable on stage, and the gate resistance is the sum of the first gate driving resistance R gon1 and the second gate driving resistance R gon2.
Further, in one embodiment of the present invention, the driving voltage VCC charges the first capacitor C 1 through the inductor L 1 and the first resistor R 1 connected in parallel, the voltage across the first capacitor C 1 has a rise time, and the totem pole output voltage closely follows the voltage of the first capacitor C 1.
Further, in one embodiment of the present invention, the values of the inductance L 1, the first resistance R 1, and the first capacitance C 1 are adjusted to achieve the rate of change of the driving voltage VCC rise.
Further, in one embodiment of the present invention, during the current rising phase, the gate-source voltage Vgs immediately follows the first capacitor voltage VC1, and the rising time of the first capacitor voltage VC1 is controlled according to the relationship that the drain current change rate is proportional to the gate-source voltage Vgs change rate, so as to control the gate-source voltage change rate, thereby controlling the current rising change rate and the reverse current spike.
Further, in one embodiment of the present invention, during the voltage drop phase, the first capacitor voltage VC1 continues to increase from the miller voltage to the driving voltage VCC, and a larger gate current is generated on the first gate driving resistor R gon1 to charge the miller capacitor, so as to accelerate the voltage drop process and reduce the turn-on loss.
Further, in an embodiment of the present invention, in the stable on phase, as the first capacitor voltage VC1 increases, the gate-source voltage of the MOS transistor MOSon decreases, when the gate-source voltage is less than the threshold voltage, MOSon is turned off, and the gate resistor R gon is the sum of the first gate driving resistor R gon1 and the second gate driving resistor R gon2.
Further, in one embodiment of the present invention, during the stable conduction phase, the gate damping resistor R gon is larger, the damping factor is larger, and the gate voltage overshoot is smaller.
Further, in one embodiment of the present invention, when the gate damping resistor R gon is sufficiently large, the damping factor is greater than 1, and gate voltage overshoot is completely suppressed.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The foregoing and/or additional aspects and advantages of the invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a schematic diagram of a related art open loop drive circuit for a silicon carbide MOSFET;
FIG. 2 is a schematic diagram of a conventional drive circuit for a silicon carbide MOSFET;
FIG. 3 is a schematic diagram showing a comparison of a turn-on transient driven by a conventional driving circuit and a related art open loop driving circuit;
FIG. 4 is a schematic diagram of an open loop drive circuit for optimizing the turn-on waveform of a silicon carbide MOSFET in accordance with one embodiment of the present invention;
Fig. 5 is a schematic diagram of typical waveforms of gate voltage and current under a driving circuit according to an embodiment of the present invention.
FIG. 6 is a schematic diagram of a gate current flow path of a driving circuit at times t0-t3 according to one embodiment of the present invention;
FIG. 7 is a schematic diagram of an equivalent circuit of a driving circuit at times t0-t3 according to one embodiment of the present invention;
FIG. 8 is a schematic diagram of a gate current flow path of a driving circuit at times t3-t4 according to one embodiment of the present invention;
Fig. 9 is a schematic diagram of an equivalent circuit of the driving circuit at time t3-t4 according to an embodiment of the present invention.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative and intended to explain the present invention and should not be construed as limiting the invention.
Before introducing an open-loop drive circuit that optimizes the turn-on waveform of a silicon carbide MOSFET, a conventional silicon carbide MOSFET drive circuit will be described.
The silicon carbide MOSFET has the characteristics of high blocking voltage, high junction temperature, high switching speed and the like, and is expected to replace Si IGBT. As shown in fig. 2, the conventional drive circuit for silicon carbide MOSFETs can control the on waveform only by controlling the gate resistor R gon. Under the bridge arm structure, the following two pairs of contradictions exist in the opening process by using a traditional driving circuit:
1) On loss and reverse current spike. When R gon is smaller, the turn-on loss is small, but the reverse current peak is large, the reliability of the power device is affected, and particularly, the single-tube silicon carbide MOSFET with lower current level is formed; when R gon is larger, the reverse current peak becomes smaller, but the turn-on loss is obviously increased, and the system efficiency and the power density are reduced;
2) The turn-on speed and gate voltage overshoot. When R gon is smaller, the gate loop damping is smaller, the gate voltage overshoot is serious, usually more than 25V and even more than 30V, and a gate oxide layer can be broken down, so that the power device is permanently disabled; when R gon is larger, the gate loop damping becomes larger, the gate voltage overshoot is reduced, but the turn-on speed is slowed down.
And as shown in fig. 3, the comparison of the turn-on transient driven by the conventional drive circuit and the open loop drive circuit. With conventional drive circuits, the turn-on waveform of a silicon carbide MOSFET is typically sub-optimal. The closed-loop driving circuit can control the turn-on transient state of the silicon carbide MOSFET by detecting the gate voltage, the drain current change rate, the Miller platform and the like, and optimize the turn-on waveform. But its disadvantages are mainly manifested in the following aspects:
1) Additional detection circuitry and feedback circuitry are required, increasing the complexity and cost of the drive circuitry;
2) The on time of the silicon carbide MOSFET is usually tens of nanoseconds, the bandwidth requirements on the detection circuit and the feedback circuit are high, the detection circuit is easy to be interfered, and the actual control effect of the drive can be affected.
Based on the above reasons, the embodiment of the invention provides an open-loop driving circuit for optimizing the turn-on waveform of a silicon carbide MOSFET.
An open-loop driving circuit for optimizing a turn-on waveform of a silicon carbide MOSFET according to an embodiment of the present invention is described below with reference to the accompanying drawings.
Fig. 4 is a schematic diagram of an open loop drive circuit for optimizing the turn-on waveform of a silicon carbide MOSFET in accordance with one embodiment of the invention.
As shown in fig. 4, the open-loop driving circuit 10 for optimizing the turn-on waveform of the silicon carbide MOSFET includes: a drive voltage waveform generator 100 and a variable gate drive resistance control circuit.
The driving voltage waveform generator 100 is used for generating a driving voltage waveform with a preset rising edge. The gate-variable driving resistor control circuit 200 is used for controlling the magnitude of the gate-variable driving resistor in different stages of the turn-on transient process, wherein the gate-source voltage change rate and the driving voltage change rate of the silicon carbide MOSFET are consistent in the current rising stage so as to control the current rising change rate and the reverse current by controlling the driving voltage rising change rate; in the voltage dropping stage, the gate current is increased to accelerate the voltage dropping process and reduce the turn-on loss; in the stable conduction stage, the gate damping resistance is increased so as to inhibit the gate voltage overshoot without affecting the switching speed. The driving circuit 10 of the embodiment of the invention can be used for the open driving circuit design of the silicon carbide MOSFET, has simple structure, is easy to realize and has lower cost, and can simultaneously inhibit reverse current peak and gate voltage overshoot under the condition of reducing the open loss.
It will be appreciated that the drive voltage waveform generator 100 in combination with the variable gate drive resistance control circuit 200 can simultaneously suppress reverse current spikes and gate voltage overshoots with reduced turn-on losses.
Further, in one embodiment of the present invention, the driving voltage waveform generator includes: first capacitor C 1, inductance L 1, and first resistance R 1.
Wherein, the first capacitor C 1; the inductor L 1 and the first resistor R 1, the inductor L 1 and the first resistor R 1 are connected in parallel with each other and are connected to the first capacitor C 1 to charge the first capacitor C 1.
Specifically, the driving voltage waveform generator 100 is formed of an RLC circuit in which an inductor L 1 is connected in parallel with a first resistor R 1 while charging a first capacitor C 1, which functions to generate a driving voltage waveform of a specific rising edge.
Parameter calculation of the drive voltage waveform generator 100:
1) Calculation of C 1
To decouple the capacitor C 1 voltage and the silicon carbide MOSFET gate-source voltage, the capacitor C 1 needs to be large enough, and C 1 needs to satisfy the following conditions:
where β buffer is the current gain of the totem pole.
2) Calculation of R 1
The capacitance C 1 is determined under the condition that equation 1 is satisfied. In order to meet the requirement that the rate of change of the current rise and the reverse current can be effectively controlled at all load currents, the rate of change of the voltage of the capacitor C 1 should be kept as uniform as possible over the range of the capacitor voltage from VEE to VCC, and the current of the capacitor C 1 should be kept uniform over this voltage range. Capacitor C 1 currentThe conditions to be satisfied are:
The current charges C 1, and the rate of change of the voltage of C 1 should satisfy the condition:
if the target change rate of the voltage of C 1 It is known that the conditions that R 1 needs to satisfy can be calculated from equation 2:
Since the chip current output capability of the front end of R 1 is limited, the resistor R 1 is limited by this condition, and the R 1 needs to satisfy the following limitation conditions besides the formula 3:
3) Calculation of L 1
To keep the capacitance C 1 current consistent, the increase in L 1 branch current should be approximately equal to the decrease in R 1 branch current, so L 1、R1 and C 1 satisfy the following conditions:
Wherein T is the resonance period of L 1C1, and the condition satisfied by T is:
The conditions that L 1 needs to satisfy can be obtained according to formulas 4 and 5:
Further, in one embodiment of the present invention, the driving voltage VCC charges the first capacitor C 1 through the parallel inductor L 1 and the first resistor R 1, the voltage across the first capacitor C 1 has a rising time, and the totem pole output voltage closely follows the voltage of the first capacitor C 1.
Further, in one embodiment of the present invention, the values of the inductance L 1, the first resistance R 1, and the first capacitance C 1 are adjusted to achieve the rate of change of the rise of the driving voltage VCC.
Further, in one embodiment of the present invention, the variable gate driving resistance control circuit 200 includes: the first gate driving resistor R gon1, the second gate driving resistor R gon2 and the MOS transistor MOSon.
The resistance value of the second gate driving resistor R gon2 is larger than that of the first gate driving resistor R gon1. MOS transistor MOSon is in an ON state during the current rising phase and the voltage falling phase, MOS transistor MOSon is in a first gate driving resistor R gon1, and MOS transistor MOSon is in an OFF state during the stable conduction phase, and the gate resistance is the sum of first gate driving resistor R gon1 and second gate driving resistor R gon2.
It can be appreciated that the variable gate driving resistor control circuit 200 is composed of one NMOS MOSon and two gate resistors R gon1、Rgon2, and is used for controlling the magnitude of the gate resistors during different turn-on transients.
As shown in fig. 4, the parameter calculation of the variable gate driving resistance control circuit 200 is as follows:
1) Calculation of R gon1
The driving requirement R gon1 in the embodiment of the present invention is a small value, and the value of R gon1 can be finely adjusted according to practical application situations, and generally 0 Ω to 3 Ω can be taken.
2) Calculation of R gon2
The driving requirement R gon2 in the embodiment of the present invention is a larger value, and the value of R gon2 can be adjusted according to the actual application situation, and may be generally greater than 10Ω.
3) Calculation of Vref
In order for the drive of the embodiments of the present invention to be applied at full load current, consider the case of maximum load current I loadmax. From the on characteristics of the silicon carbide MOSFET, it can be seen that the miller voltage V millermax satisfies the following conditions at maximum load current:
Where g fs is the transconductance of the silicon carbide MOSFET and V th is the threshold voltage of the silicon carbide MOSFET;
At this time, in the voltage drop stage, the gate current Ig (t) and the miller capacitance charge Qgd of the silicon carbide MOSFET satisfy the conditions of equation 6 and equation 7, respectively, as follows:
as can be calculated from the formulas 6 and 7, the time T fall of the voltage drop phase should satisfy the following conditions:
in order to ensure MOSon to turn off in the t3-t4 phase, the conditions that Vref needs to meet are:
Where V MOSonth is the threshold voltage of MOSon.
Specifically, as shown in fig. 4 and 5, the change rate of the capacitor voltage VC1 is kept consistent in the range from VEE to VCC, so that it can be ensured that in the full current load range, the capacitor voltage VC1 is controlled to effectively control the current rising change rate and the reverse current peak, the on transient under the driving of the present invention is controlled in two stages according to the flow path of the gate current, at the time t0-t3, MOSon is in the on state, the first gate driving resistor is R gon1, at the time t3-t4, MOSon is in the off state, and the gate resistance is the sum of R gon1 and R gon2. R gon1 is a smaller value, is the gate resistance at time t0-t 3; r gon2 is a relatively large value; the sum of R gon1 and R gon2 is the gate resistance at stage t3-t 4.
As shown in fig. 6, the gate current flow path of the driving circuit according to the embodiment of the present invention is shown at time t0-t3, and fig. 7 is an equivalent circuit of the driving circuit according to the present invention at time t0-t 3. The capacitor voltage VC1 charges the gate through the first resistor R gon1, the first resistor R gon1 is a small value, and the time constant τ iss of the circuit formed by the input capacitor C iss of the silicon carbide MOSFET is very small, and the rise time of the capacitor voltage VC1 is much longer than τ iss.
T0-t3: the driving signal is switched from off to on, the driving voltage is switched from VEE to VCC, the driving voltage VCC charges the capacitor C 1 through the L 1 and the R 1 which are connected in parallel, and the totem pole output voltage compresses the voltage VC1 along with the capacitor C 1. The MOSon source voltage is the difference between the conduction voltage drops of the totem pole output voltages VC1 and MOSon, which is approximately equal to the totem pole output voltage VC1, and the MOSon gate source voltage is the difference between Vref and VC1. At this stage, VC1 rises from VEE to VCC, to a small value, MOSon gate-source voltage is greater than its threshold voltage, and is in on state, ensuring that the gate resistance at this stage is R gon1. The capacitor voltage VC1 charges the gate electrode of the silicon carbide MOSFET through the resistor R gon1, R gon1 is a smaller value, and the time constant tau iss of the circuit formed by the input capacitor C iss of the silicon carbide MOSFET is very small, so that the rising time of the capacitor voltage VC1 is far longer than tau iss.
Further, in one embodiment of the present invention, during the current rising phase, the gate-source voltage Vgs immediately follows the first capacitor voltage VC1, and the rising time of the first capacitor voltage VC1 is controlled according to the relationship that the drain current change rate is proportional to the gate-source voltage Vgs change rate, so as to control the current rising change rate and the reverse current spike.
It will be appreciated that during the current ramp-up phase (t 1-t 2), the gate-source voltage V gs closely follows the capacitor voltage VC1, and the gate-source voltage rate of change can be controlled by controlling the time of the ramp-up of the capacitor voltage VC1 according to the relationship that the drain current rate of change is proportional to the gate-source voltage V gs rate of change, thereby controlling the current ramp-up rate and the reverse current spike.
Specifically, in the current rising stage (t 1-t 2), the gate-source voltage V gs closely follows the capacitor voltage VC1, and the values of L 1、R1 and C 1 are controlled to control the change rate of the capacitor voltage VC1 according to the positive correlation between the change rate of the drain current and the change rate of the gate-source voltage V gs, so that the change rate of the gate-source voltage of the silicon carbide MOSFET can be controlled to control the change rate of the drain current rising and the reverse current peak
Further, in one embodiment of the present invention, during the voltage drop phase, the first capacitor voltage VC1 continues to increase from the miller voltage to the driving voltage VCC, and a larger gate current is generated on the first gate driving resistor R gon1 to charge the miller capacitor, so as to accelerate the voltage drop process and reduce the turn-on loss.
It will be appreciated that during the voltage drop phase (t 2-t 3), the first capacitor voltage VC1 continues to increase from the miller voltage to VCC, producing a larger gate current at the smaller resistor R gon1 to charge the miller capacitor, accelerating the voltage drop process and reducing turn-on losses. And in the voltage drop stage (t 2-t 3), the gate current is quickly increased from the smaller value Ic to the larger value Iv, the voltage drop process is accelerated, and the turn-on loss is reduced. The moment MOSon turns off can be adjusted by adjusting the value of Vref.
Further, in one embodiment of the present invention, in the stable on phase, as the first capacitor voltage VC1 increases, the gate-source voltage of the MOS transistor MOSon decreases, and when the gate-source voltage is smaller than the threshold voltage, MOSon is turned off, and the gate resistor R gon is the sum of the first gate driving resistor R gon1 and the second gate driving resistor R gon2.
In one embodiment of the present invention, the gate damping resistor R gon is larger, the damping factor is larger, and the gate voltage overshoot is smaller during the steady conduction phase.
In one embodiment of the present invention, when the gate damping resistor R gon is large enough, the damping factor is greater than 1 and the gate voltage overshoot is completely suppressed.
As shown in fig. 8 and 9, in the stable conduction phase (t 3-t 4), the gate-source voltage MOSon decreases with the increase of VC1, and when the gate-source voltage is smaller than the threshold voltage, MOSon is turned off, and the gate resistance R gon is equal to the sum of R gon1 and R gon2. The gate voltage overshoot generally occurs in the t3-t4 stage, and the gate damping resistor R gon is larger, the damping factor is larger, and the gate voltage overshoot is smaller. When R gon is large enough, the damping factor can be greater than 1 and gate voltage overshoot can be completely suppressed.
Specifically, t3-t4, the capacitor voltage VC1 continues to increase at this stage, the MOSon gate-source voltage is the difference between Vref and VC1, and as VC1 increases, the MOSon gate-source voltage decreases, MOSon turns off when the MOSon gate-source voltage is below its threshold voltage, and the gate resistance changes from R gon1 to R gon, where R gon is the sum of R gon1 and R gon2, R gon2 is a larger value, and then the gate resistance R gon is a larger value. The gate voltage overshoot generally occurs in the t3-t4 phase, where the gate damping resistor R gon is larger, the damping factor is larger, and the gate voltage overshoot is smaller. When R gon is large enough, the damping factor can be greater than 1 and gate voltage overshoot can be completely suppressed.
According to the open-loop driving circuit for optimizing the turn-on waveform of the silicon carbide MOSFET, transient processes of a current rising stage and a voltage falling stage can be independently controlled, the rising time of the capacitor voltage VC1 can be increased to control a reverse current peak, the gate resistance is small, the voltage falling transient process can be accelerated, the turn-on loss is reduced, the contradiction between the reverse current peak and the turn-on loss under the traditional driving circuit is broken, the gate voltage overshoot can be restrained under the condition that the turn-on speed is not influenced, the gate voltage overshoot is restrained by adding a larger gate resistance, the transient process is not influenced, and the turn-on speed of the silicon carbide MOSFET is not influenced.
In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or element being referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present invention, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly, through intermediaries, or both, may be in communication with each other or in interaction with each other, unless expressly defined otherwise. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
In the present invention, unless expressly stated or limited otherwise, a first feature "up" or "down" a second feature may be the first and second features in direct contact, or the first and second features in indirect contact via an intervening medium. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
While embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the invention.
Claims (9)
1. An open loop drive circuit for optimizing the turn-on waveform of a silicon carbide MOSFET, comprising:
a driving voltage waveform generator for generating a driving voltage waveform of a preset rising edge;
the control circuit of the variable gate drive resistor is used for controlling the magnitude of the gate drive resistor at different stages of the turn-on transient process, wherein,
In the current rising stage, the gate-source voltage change rate of the silicon carbide MOSFET is consistent with the driving voltage rising change rate, so that the current rising change rate and the reverse current are controlled by controlling the driving voltage rising change rate; in the voltage dropping stage, the gate current is increased to accelerate the voltage dropping process and reduce the turn-on loss; in the stable conduction stage, the gate damping resistance is increased so as to inhibit the overshoot of the gate voltage without affecting the switching speed;
Wherein, the gate-variable drive resistance control circuit includes:
A first gate driving resistor R gon1 and a second gate driving resistor R gon2, wherein the resistance value of the second gate driving resistor R gon2 is greater than the resistance value of the first gate driving resistor R gon1;
And a MOS transistor MOSon, wherein the MOS transistor MOSon is in an on state during the current rising stage and the voltage falling stage, the gate resistance is the first gate driving resistance R gon1, and the MOS transistor MOSon is in an off state during the stable on stage, and the gate resistance is the sum of the first gate driving resistance R gon1 and the second gate driving resistance R gon2.
2. The open loop drive circuit for optimizing a turn-on waveform of a silicon carbide MOSFET of claim 1, wherein the drive voltage waveform generator comprises:
a first capacitor C 1;
An inductor L 1 and a first resistor R 1, where the inductor L 1 and the first resistor R 1 are connected in parallel to each other and are both connected to the first capacitor C 1 to charge the first capacitor C 1.
3. The open loop drive circuit for optimizing the turn-on waveform of a silicon carbide MOSFET according to claim 2 wherein the drive voltage VCC charges the first capacitor C 1 through the inductor L 1 and the first resistor R 1 in parallel, the voltage across the first capacitor C 1 having a rise time, the totem pole output voltage closely following the voltage of the first capacitor C 1.
4. The open loop drive circuit for optimizing a turn-on waveform of a silicon carbide MOSFET of claim 3 wherein values of said inductance L 1, said first resistance R 1, and said first capacitance C 1 are adjusted to achieve a rate of change of said drive voltage VCC rise.
5. The open loop drive circuit for optimizing the turn-on waveform of a silicon carbide MOSFET according to claim 1 wherein during the current ramp-up phase, the gate-to-source voltage Vgs closely follows the first capacitor voltage VC1, and wherein the first capacitor voltage VC1 ramp-up time, and hence the gate-to-source voltage ramp-up rate, is controlled in accordance with the relationship in which the drain current ramp-up rate is proportional to the gate-to-source voltage Vgs ramp-up rate, to control the current ramp-up rate and the reverse current spike.
6. The open loop drive circuit of claim 5 wherein during the voltage drop phase, the first capacitor voltage VC1 continues to increase from miller voltage to drive voltage VCC, generating a greater gate current on the first gate drive resistor R gon1 to charge the miller capacitor, accelerating the voltage drop process, and reducing turn-on losses.
7. The open loop drive circuit of claim 1, wherein during a steady turn-on phase, as the first capacitance voltage VC1 increases, the gate-source voltage of the MOS transistor MOSon decreases, MOSon turns off when the gate-source voltage is less than a threshold voltage, and the gate damping resistor R gon is the sum of the first gate drive resistor R gon1 and the second gate drive resistor R gon2.
8. The open loop drive circuit for optimizing the turn-on waveform of a silicon carbide MOSFET of claim 7 wherein said gate damping resistor R gon is greater, the damping factor is greater, and the gate voltage overshoot is less during the steady turn-on phase.
9. The open loop drive circuit for optimizing the turn-on waveform of a silicon carbide MOSFET of claim 8 wherein said damping factor is greater than 1 and gate voltage overshoot is completely suppressed when said gate damping resistor R gon is sufficiently large.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810175507.9A CN108270424B (en) | 2018-03-02 | 2018-03-02 | Open-loop driving circuit for optimizing silicon carbide MOSFET (Metal-oxide-semiconductor field Effect transistor) on waveform |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810175507.9A CN108270424B (en) | 2018-03-02 | 2018-03-02 | Open-loop driving circuit for optimizing silicon carbide MOSFET (Metal-oxide-semiconductor field Effect transistor) on waveform |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108270424A CN108270424A (en) | 2018-07-10 |
| CN108270424B true CN108270424B (en) | 2024-05-07 |
Family
ID=62774489
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810175507.9A Active CN108270424B (en) | 2018-03-02 | 2018-03-02 | Open-loop driving circuit for optimizing silicon carbide MOSFET (Metal-oxide-semiconductor field Effect transistor) on waveform |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108270424B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112436725A (en) * | 2020-10-15 | 2021-03-02 | 北京交通大学 | Gate-source voltage disturbance suppression circuit based on transconductance gain negative feedback mechanism |
| CN113054972B (en) * | 2021-03-15 | 2024-06-25 | 北京航空航天大学 | Silicon carbide MOSFET driving circuit for improving turn-on performance and control method |
| CN113238113B (en) * | 2021-05-13 | 2024-09-10 | 日照旭日电子有限公司 | Electromagnetic interference detection device |
| CN113489288A (en) * | 2021-07-19 | 2021-10-08 | 光华临港工程应用技术研发(上海)有限公司 | Low electromagnetic interference silicon carbide power semiconductor device driving circuit method |
| CN113810035B (en) * | 2021-09-07 | 2024-06-11 | 深圳市福瑞电气有限公司 | Control method and circuit for parallel connection of silicon carbide MOSFET (Metal-oxide-semiconductor field Effect transistor) multiple tubes |
| CN116316503B (en) * | 2023-01-18 | 2023-09-22 | 广东工业大学 | Bridge arm switch tube gate-source voltage spike adjusting device and implementation method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6127746A (en) * | 1996-10-21 | 2000-10-03 | International Rectifier Corp. | Method of controlling the switching DI/DT and DV/DT of a MOS-gated power transistor |
| JP2003324338A (en) * | 2002-04-30 | 2003-11-14 | Denso Corp | Current clamp circuit |
| CN201518451U (en) * | 2010-03-10 | 2010-06-30 | 天津大学 | IPM special driving power supply |
| CN103944549A (en) * | 2014-04-03 | 2014-07-23 | 南京航空航天大学 | High-reliability MOSFET drive circuit |
| CN208272946U (en) * | 2018-03-02 | 2018-12-21 | 清华大学 | Optimization silicon carbide MOSFET opens the open loop driving circuit of waveform |
-
2018
- 2018-03-02 CN CN201810175507.9A patent/CN108270424B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6127746A (en) * | 1996-10-21 | 2000-10-03 | International Rectifier Corp. | Method of controlling the switching DI/DT and DV/DT of a MOS-gated power transistor |
| JP2003324338A (en) * | 2002-04-30 | 2003-11-14 | Denso Corp | Current clamp circuit |
| CN201518451U (en) * | 2010-03-10 | 2010-06-30 | 天津大学 | IPM special driving power supply |
| CN103944549A (en) * | 2014-04-03 | 2014-07-23 | 南京航空航天大学 | High-reliability MOSFET drive circuit |
| CN208272946U (en) * | 2018-03-02 | 2018-12-21 | 清华大学 | Optimization silicon carbide MOSFET opens the open loop driving circuit of waveform |
Non-Patent Citations (1)
| Title |
|---|
| A Novel Active Gate Driver for Improving SiC MOSFET Switching Trajectory;Alejandro Paredes Camacho;Vicent Sala;Hamidreza Ghorbani;Jose Luis Romeral Martinez;IEEE transactions on industrial electronics;64(11);全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108270424A (en) | 2018-07-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108270424B (en) | Open-loop driving circuit for optimizing silicon carbide MOSFET (Metal-oxide-semiconductor field Effect transistor) on waveform | |
| US8138818B2 (en) | Gate drive apparatus | |
| US7514967B2 (en) | Driver for voltage driven type switching element | |
| US7408398B2 (en) | Circuit arrangement having a power transistor and a drive circuit for the power transistor | |
| US7113412B2 (en) | Drive circuit and power supply apparatus | |
| EP1831998B1 (en) | Self-timed switching regulator pre-driver | |
| CN108377141B (en) | Switching rate monitoring and control | |
| CN112821730B (en) | Novel driving topology, driving method thereof and crosstalk suppression method | |
| JP2001217697A (en) | Drive device for semiconductor element and its control method | |
| CN111342642B (en) | Flyback power control method for driving silicon carbide MOSFET | |
| CN115173676B (en) | SiC MOSFET driving circuit for inhibiting overshoot peak | |
| CN114124060A (en) | Active driving system and method | |
| JP6887393B2 (en) | Power converter | |
| CN208272946U (en) | Optimization silicon carbide MOSFET opens the open loop driving circuit of waveform | |
| CN216699815U (en) | Novel driving topology | |
| CN113054828B (en) | Drive circuit and electrical power generating system of power switch tube | |
| CN114696595A (en) | Drive device | |
| CN113949260A (en) | High-speed high-voltage large-current modulation circuit | |
| CN114640328B (en) | Temperature-resistant SiC MOSFET driving circuit capable of inhibiting on-current oscillation and control method thereof | |
| US20230053929A1 (en) | Driving apparatus | |
| CN215934712U (en) | Gate drive circuit with controllable switching speed | |
| US11108388B1 (en) | Silicon carbide power device, driving circuit and control method | |
| CN113472184B (en) | Driving method and driving circuit | |
| CN118783743A (en) | Controllable grid current source driving circuit | |
| CN113676023A (en) | Gate drive circuit with controllable switching speed and method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |