CN108270424B - Optimizing the open-loop drive circuit for silicon carbide MOSFET turn-on waveform - Google Patents

Abstract

The invention discloses an open-loop driving circuit for optimizing a silicon carbide MOSFET (Metal-oxide-semiconductor field Effect transistor) on waveform, which comprises the following components: a driving voltage waveform generator for generating a driving voltage waveform of a preset rising edge; the variable gate drive resistor control circuit is used for controlling the magnitude of the gate drive resistor in different stages of the turn-on transient process, wherein the gate source voltage change rate of the silicon carbide MOSFET is consistent with the drive voltage rise change rate in the current rise stage so as to control the current rise change rate and the reverse current by controlling the drive voltage rise change rate; in the voltage dropping stage, the gate current is increased to accelerate the voltage dropping process and reduce the turn-on loss; in the stable conduction stage, the gate damping resistance is increased so as to inhibit the gate voltage overshoot without affecting the switching speed. The driving circuit has simple structure, easy realization and low cost, and can inhibit reverse current peak and gate voltage overshoot at the same time under the condition of reducing the turn-on loss.

Description

Optimizing the open-loop drive circuit for silicon carbide MOSFET turn-on waveform

Technical Field

The present invention relates to the technical field of power electronic circuits, and in particular to an open-loop drive circuit for optimizing a silicon carbide MOSFET turn-on waveform.

Background technique

Silicon carbide MOSFET is a new type of power semiconductor, which is still a long way from large-scale industrialization. Due to the fast switching speed of silicon carbide devices, the gate voltage will have more serious gate oscillation and overshoot, which may break through the gate oxide layer and cause permanent failure of the device. The larger current change rate will bring more serious electromagnetic interference and larger turn-on reverse current. Although manufacturers such as CREE provide drivers, the driver can only change the switching transient process of silicon carbide MOSFET by changing the gate resistance, and can only balance the compromise between gate voltage overshoot and switching loss, switching speed and switching loss, and it is difficult to achieve the optimized drive of silicon carbide MOSFET. Closed-loop drive circuits are often used for the optimized drive of silicon IGBT (Insulated Gate Bipolar Transistor), which requires additional detection circuits and feedback circuits. However, due to the fast switching speed of silicon carbide MOSFET, the bandwidth requirements and anti-interference ability of the detection circuit and feedback circuit are very high, and the implementation is complex and difficult to use in engineering applications.

The open-loop drive circuit can optimize the turn-on waveform of the SiC MOSFET without the need for a detection circuit or a feedback circuit. Figure 1 is an open-loop drive circuit for SiC MOSFET. A larger resistor _Rgon is used in the current rising phase to control the current rising rate and the reverse current spike. The switch Qbst is controlled by a delay circuit to turn it on in the voltage falling phase, and additional gate current is injected through the resistor Rbst to accelerate the voltage falling rate and reduce the turn-on loss. The working principle is as follows:

t0-t2: Qbst is in the off state, the driving voltage VCC charges the SiC MOSFET input capacitance _Ciss (the sum of _Cgs and _Cgd ) through the gate resistor _Rgon , and the control resistor _Rgon can control the current rise rate and reverse current;

t2-t3: Control the delay time to turn on Qbst in this stage, and the driving voltage VCC charges the gate through the gate resistor _Rgon and Rbst. The resistor Rbst branch will generate additional gate current Igbst, accelerate the voltage drop process, and reduce the turn-on loss.

The driving circuit of the related art can control the reverse current and optimize the turn-on loss, but it has the following disadvantages:

1) The delay time is fixed, and it can only achieve better optimization effect under specific load conditions;

2) The gate voltage overshoot is serious. The gate voltage overshoot usually exists in the t3-t4 stage. In this stage, the gate damping resistor is the equivalent resistance of _Rgon and Rbst in parallel. The damping is small and the gate voltage spike will be larger.

In summary, when optimizing the turn-on waveform of SiC MOSFET, the related technologies are divided into two categories: closed-loop drive and open-loop drive. Closed-loop drive has the disadvantages of complex circuit, high cost, and susceptibility to interference of detection circuit. Although the open-loop drive circuit has the advantages of simple circuit and easy implementation, it is difficult for the current open-loop drive to suppress the reverse current spike and gate voltage overshoot while optimizing the turn-on loss.

Summary of the invention

The present invention aims to solve one of the technical problems in the related art at least to a certain extent.

To this end, the purpose of the present invention is to propose an open-loop drive circuit for optimizing the turn-on waveform of a silicon carbide MOSFET. The drive circuit has a simple structure, is easier to implement, and has a low cost. It can reduce turn-on losses while suppressing reverse current spikes and gate voltage overshoot.

To achieve the above-mentioned purpose, an embodiment of the present invention proposes an open-loop drive circuit for optimizing the turn-on waveform of a silicon carbide MOSFET, comprising: a drive voltage waveform generator, used to generate a drive voltage waveform with a preset rising edge; a variable gate drive resistance control circuit, used to control the size of the gate drive resistance at different stages of the turn-on transient process, wherein, in the current rising stage, the gate-source voltage change rate of the silicon carbide MOSFET is consistent with the drive voltage rising change rate, so as to control the current rising change rate and the reverse current by controlling the drive voltage rising change rate; in the voltage falling stage, the gate current is increased to accelerate the voltage falling process and reduce the turn-on loss; in the stable conduction stage, the gate damping resistance is increased to suppress the gate voltage overshoot without affecting the switching speed.

The open-loop drive circuit for optimizing the turn-on waveform of the silicon carbide MOSFET in the embodiment of the present invention can independently control the transient processes of the current rising stage and the voltage falling stage, and can increase the rise time of the capacitor voltage VC1 to control the reverse current spike, but the gate resistance is very small, which can accelerate the voltage drop transient process and reduce the turn-on loss, breaking the contradiction between the reverse current spike and the turn-on loss in the traditional drive circuit, and can suppress the gate voltage overshoot without affecting the turn-on speed. By adding a larger gate resistance, the gate voltage overshoot is suppressed, but it does not affect the transient process and will not affect the turn-on speed of the silicon carbide MOSFET.

In addition, the open-loop drive circuit for optimizing the turn-on waveform of the silicon carbide MOSFET according to the above embodiment of the present invention may also have the following additional technical features:

Furthermore, in one embodiment of the present invention, the driving voltage waveform generator includes: a first capacitor C ₁ ; an inductor L ₁ and a first resistor R ₁ , wherein the inductor L ₁ and the first resistor R ₁ are connected in parallel to each other and are both connected to the first capacitor C ₁ to charge the first capacitor C ₁ .

Further, in one embodiment of the present invention, the variable gate drive resistance control circuit includes: a first gate drive resistor R _gon1 and a second gate drive resistor R _gon2 , wherein the resistance of the second gate drive resistor R _gon2 is greater than the resistance of the first gate drive resistor R _gon1 ; a MOS tube MOSON, wherein in the current rising stage and the voltage falling stage, the MOS tube MOSON is in an on state, and the gate resistance is the first gate drive resistor R _gon1 , and in the stable conduction stage, the MOS tube MOSON is in an off state, and the gate resistance is the sum of the first gate drive resistor R _gon1 and the second gate drive resistor R _gon2 .

Furthermore, in one embodiment of the present invention, the driving voltage VCC charges the first capacitor _C1 through the inductor _L1 and the first resistor _R1 connected in parallel, the voltage across the first capacitor _C1 has a rising time, and the totem pole output voltage closely follows the voltage of the first capacitor _C1 .

Furthermore, in one embodiment of the present invention, the values of the inductor L ₁ , the first resistor R ₁ and the first capacitor C ₁ are adjusted to achieve the rising rate of the driving voltage VCC.

Furthermore, in one embodiment of the present invention, in the current rising stage, the gate-source voltage Vgs closely follows the first capacitor voltage VC1, and according to the relationship that the drain current change rate is proportional to the gate-source voltage Vgs change rate, the rise time of the first capacitor voltage VC1 is controlled, and then the gate-source voltage change rate is controlled to control the current rising rate and the reverse current peak.

Furthermore, in one embodiment of the present invention, in the voltage drop stage, the first capacitor voltage VC1 continues to increase from the Miller voltage to the driving voltage VCC, generating a large gate current on the first gate driving resistor R _gon1 to charge the Miller capacitor, thereby accelerating the voltage drop process and reducing turn-on loss.

Furthermore, in one embodiment of the present invention, in the stable conduction stage, as the first capacitor voltage VC1 increases, the gate-source voltage of the MOS tube MOSON decreases, and when the gate-source voltage is less than the threshold voltage, MOSON is turned off, and the gate resistor R _gon is the sum of the first gate drive resistor R _gon1 and the second gate drive resistor R _gon2 .

Furthermore, in one embodiment of the present invention, in the stable conduction stage, the gate damping resistance R _gon is relatively large, the damping factor is relatively large, and the gate voltage overshoot is relatively small.

Furthermore, in one embodiment of the present invention, when the gate damping resistance R _gon is large enough, the damping factor is greater than 1, and the gate voltage overshoot is completely suppressed.

Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and/or additional aspects and advantages of the present invention will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

FIG1 is a schematic diagram of an open-loop driving circuit for a silicon carbide MOSFET in the related art;

FIG2 is a schematic diagram of a conventional driving circuit of a silicon carbide MOSFET;

FIG3 is a comparative schematic diagram of a turn-on transient process under the driving of a conventional drive circuit and an open-loop drive circuit of the related art;

4 is a schematic structural diagram of an open-loop driving circuit for optimizing a turn-on waveform of a silicon carbide MOSFET according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of typical waveforms of gate voltage and current in a driving circuit according to an embodiment of the present invention.

6 is a schematic diagram of a gate current flow path of a driving circuit at time t0-t3 according to an embodiment of the present invention;

FIG7 is a schematic diagram of an equivalent circuit of a driving circuit at time t0-t3 according to an embodiment of the present invention;

FIG8 is a schematic diagram of a gate current flow path of a driving circuit at time t3-t4 according to an embodiment of the present invention;

FIG. 9 is a schematic diagram of an equivalent circuit of a driving circuit at time t3 - t4 according to an embodiment of the present invention.

Detailed ways

Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

Before introducing the open-loop drive circuit that optimizes the turn-on waveform of the SiC MOSFET, the traditional SiC MOSFET drive circuit is first introduced.

Silicon carbide MOSFET has the characteristics of high blocking voltage, high junction temperature, and high switching speed, and is expected to replace Si IGBT. As shown in Figure 2, the traditional drive circuit of silicon carbide MOSFET can only control the turn-on waveform by controlling the gate resistance R _gon . Under the bridge arm structure, using the traditional drive circuit, the turn-on process has the following two contradictions:

1) Turn-on loss and reverse current spike. When R _gon is small, the turn-on loss is small, but the reverse current spike is large, which affects the reliability of power devices, especially single-tube SiC MOSFETs with low current levels; when R _gon is large, the reverse current spike becomes smaller, but the turn-on loss will be significantly increased, reducing system efficiency and power density;

2) Turn-on speed and gate voltage overshoot. When R _gon is small, the gate loop damping is small, and the gate voltage overshoot is serious, usually exceeding 25V, or even exceeding 30V, which may break through the gate oxide layer and cause permanent failure of the power device; when R _gon is large, the gate loop damping becomes larger, the gate voltage overshoot decreases, but the turn-on speed is slowed down.

As shown in Figure 3, the turn-on transient process under the traditional drive circuit and the open-loop drive circuit is compared. Under the traditional drive circuit, the turn-on waveform of the SiC MOSFET is usually suboptimal. The closed-loop drive circuit can control the turn-on transient of the SiC MOSFET by detecting the gate voltage, the drain current change rate, the Miller platform, etc., and optimize the turn-on waveform. However, its shortcomings are mainly reflected in the following aspects:

1) Additional detection circuits and feedback circuits are required, increasing the complexity and cost of the drive circuit;

2) The turn-on time of silicon carbide MOSFET is usually tens of nanoseconds, which requires a very high bandwidth for the detection circuit and feedback circuit. In addition, the detection circuit is susceptible to interference, which may affect the actual control effect of the drive.

Based on the above reasons, an embodiment of the present invention proposes an open-loop drive circuit that optimizes the turn-on waveform of a silicon carbide MOSFET.

The following describes an open-loop drive circuit for optimizing a turn-on waveform of a silicon carbide MOSFET according to an embodiment of the present invention with reference to the accompanying drawings.

FIG. 4 is a schematic diagram of the structure of an open-loop drive circuit for optimizing a turn-on waveform of a silicon carbide MOSFET according to an embodiment of the present invention.

As shown in FIG. 4 , the open-loop drive circuit 10 for optimizing the turn-on waveform of the silicon carbide MOSFET includes: a drive voltage waveform generator 100 and a variable gate drive resistance control circuit.

The driving voltage waveform generator 100 is used to generate a driving voltage waveform with a preset rising edge. The variable gate drive resistance control circuit 200 is used to control the size of the gate drive resistance at different stages of the turn-on transient process, wherein, in the current rising stage, the gate-source voltage change rate of the silicon carbide MOSFET is consistent with the driving voltage rising change rate, so as to control the current rising change rate and the reverse current by controlling the driving voltage rising change rate; in the voltage falling stage, the gate current is increased to accelerate the voltage falling process and reduce the turn-on loss; in the stable conduction stage, the gate damping resistance is increased to suppress the gate voltage overshoot without affecting the switching speed. The driving circuit 10 of the present embodiment can be used for the turn-on drive circuit design of the silicon carbide MOSFET, with a simple structure, easy to implement, and low cost. It can suppress the reverse current spike and gate voltage overshoot while reducing the turn-on loss.

It can be understood that the combination of the driving voltage waveform generator 100 and the variable gate driving resistance control circuit 200 can suppress the reverse current spike and gate voltage overshoot while reducing the turn-on loss.

Furthermore, in one embodiment of the present invention, the driving voltage waveform generator includes: a first capacitor C ₁ , an inductor L ₁ and a first resistor R ₁ .

Among them, the first capacitor C ₁ , the inductor L ₁ and the first resistor R ₁ , the inductor L ₁ and the first resistor R ₁ are connected in parallel to each other and are both connected to the first capacitor C ₁ to charge the first capacitor C ₁ .

Specifically, the driving voltage waveform generator 100 is composed of an RLC circuit, in which the inductor _L1 and the first resistor _R1 are connected in parallel and charge the first capacitor _C1 at the same time, so as to generate a driving voltage waveform with a specific rising edge.

Parameter calculation of the driving voltage waveform generator 100:

1) Calculation of _C1

In order to decouple the capacitor _C1 voltage and the SiC MOSFET gate-source voltage, the capacitor _C1 needs to be large enough and _C1 needs to meet the following conditions:

where β _buffer is the current gain of the totem pole.

2) Calculation of _R1

Capacitor _C1 is determined under the condition of satisfying Formula 1. In order to ensure that the current rise rate and reverse current can be effectively controlled under all load currents, the change rate of capacitor _C1 voltage should be kept consistent as much as possible within the range of capacitor voltage from VEE to VCC, and the current of capacitor _C1 should be kept consistent within this voltage range. Capacitor _C1 current Conditions to be met:

This current charges _C1 , and the voltage change rate _{of C1} should satisfy the following condition:

If the _C1 voltage target change rate It is known that the conditions that R ₁ needs to satisfy can be calculated from formula 2:

Since the current output capability of the chip at the front end of R ₁ is limited, the resistor R ₁ is subject to this condition. In addition to satisfying formula 3, R ₁ also needs to satisfy the following restriction:

3) Calculation of _L1

To keep the capacitor _C1 current consistent, the increase in the _L1 branch current should be approximately equal to the decrease in the _R1 branch current. Therefore, the conditions satisfied by _L1 , _R1, and _C1 are:

Where T is the resonant period of L ₁ C ₁ , and the condition satisfied by T is:

According to formulas 4 and 5, the conditions that _L1 must satisfy are:

Furthermore, in one embodiment of the present invention, the driving voltage VCC charges the first capacitor _C1 through the parallel inductor _L1 and the first resistor _R1 , the voltage across the first capacitor _C1 has a rising time, and the totem pole output voltage closely follows the voltage of the first capacitor _C1 .

Furthermore, in one embodiment of the present invention, the values of the inductor L ₁ , the first resistor R ₁ and the first capacitor C ₁ are adjusted to achieve a rising rate of change of the driving voltage VCC.

Furthermore, in one embodiment of the present invention, the variable gate drive resistance control circuit 200 includes: a first gate drive resistor R _gon1 , a second gate drive resistor R _gon2 and a MOS transistor MOSON.

Among them, the first gate drive resistor R _gon1 and the second gate drive resistor R _gon2 , the resistance of the second gate drive resistor R _gon2 is greater than the resistance of the first gate drive resistor R _gon1 . MOS tube MOMon, in the current rising stage and the voltage falling stage, the MOS tube MOMon is in the on state, the gate resistance is the first gate drive resistor R _gon1 , and in the stable conduction stage, the MOS tube MOMon is in the off state, the gate resistance is the sum of the first gate drive resistor R _gon1 and the second gate drive resistor R _gon2 .

It can be understood that the variable gate drive resistance control circuit 200 is composed of an NMOS MOSon and two gate resistors R _gon1 and R _gon2 , and its function is to control the size of the gate resistance in different turn-on transient processes.

In addition, as shown in FIG. 4 , the parameters of the variable gate drive resistance control circuit 200 are calculated as follows:

1) Calculation of _Rgon1

The driving requirement R _gon1 of the embodiment of the present invention is a relatively small value, and the value of R _gon1 can be fine-tuned according to actual application conditions, and can generally be 0Ω to 3Ω.

2) Calculation of _Rgon2

The driving requirement R _gon2 of the embodiment of the present invention is a relatively large value, and the value of R _gon2 can be adjusted according to actual application conditions, and can generally be greater than 10Ω.

3) Calculation of Vref

In order to apply the drive of the embodiment of the present invention under full load current conditions, the maximum load current I _loadmax is considered. According to the turn-on characteristics of the silicon carbide MOSFET, it can be known that under the maximum load current conditions, the Miller voltage V _millermax satisfies the following conditions:

Where, _gfs is the transconductance of SiC MOSFET, _Vth is the threshold voltage of SiC MOSFET;

At this time, in the voltage drop stage, the gate current Ig _(t) and the Miller capacitance charge Qgd of the SiC MOSFET satisfy the conditions of Formula 6 and Formula 7 respectively:

According to Formula 6 and Formula 7, it can be calculated that the condition that the time T _fall of the voltage drop stage should meet is:

In order to ensure that MOSon is turned off during the t3-t4 phase, the conditions that Vref needs to meet are:

Wherein, V _MOSonth is the threshold voltage of MOSon.

Specifically, as shown in Figs. 4 and 5, the capacitor voltage VC1 maintains a consistent rate of change within the range of VEE to VCC, which ensures that within the full current load range, the control of the capacitor voltage VC1 can effectively control the current rise rate of change and the reverse current spike. The turn-on transient state driven by the present invention is divided into two stages of control according to the flow path of the gate current. At t0-t3, MOson is in the turn-on state, and the first gate drive resistance is R _gon1 . At t3-t4, MOson is in the turn-off state, and the gate resistance is the sum of R _gon1 and R _gon2 . R _gon1 is a smaller value and is the gate resistance at t0-t3; R _gon2 is a relatively larger value; the sum of R _gon1 and R _gon2 is the gate resistance at t3-t4.

As shown in FIG6 , the gate current flow path of the driving circuit of the embodiment of the present invention at the time t0-t3 is shown, and FIG7 is the equivalent circuit of the driving circuit of the present invention at the time t0-t3. The capacitor voltage VC1 charges the gate through the first resistor R _gon1 . The first resistor R _gon1 is a relatively small value, and the time constant τ iss of the circuit formed by the input capacitor C _iss of the silicon carbide MOSFET _is very small. The rise time of the capacitor voltage VC1 is much greater than τ _iss .

t0-t3: The driving signal is converted from off to on, and the driving voltage is converted from VEE to VCC. The driving voltage VCC charges the capacitor _C1 through the parallel _L1 and _R1 , and the totem pole output voltage closely follows the capacitor _C1 voltage VC1. The MOson source voltage is the difference between the totem pole output voltage VC1 and the MOson conduction voltage drop, which is approximately equal to the totem pole output voltage VC1. The MOson gate-source voltage is the difference between Vref and VC1. In this stage, VC1 rises from VEE to VCC, which is a smaller value. The MOson gate-source voltage is greater than its threshold voltage and is in the on state, ensuring that the gate resistance in this stage is _Rgon1 . The capacitor voltage VC1 charges the gate of the silicon carbide MOSFET through the resistor _Rgon1 , and _Rgon1 is a small value. The time constant τiss of the circuit formed by the input capacitor _Ciss of the silicon carbide MOSFET _is very small, which can meet the requirement that the rise time of the capacitor voltage VC1 is much greater than _τiss .

Furthermore, in one embodiment of the present invention, in the current rising stage, the gate-source voltage Vgs closely follows the first capacitor voltage VC1, and according to the relationship that the drain current change rate is proportional to the gate-source voltage Vgs change rate, the rise time of the first capacitor voltage VC1 is controlled, and then the gate-source voltage change rate is controlled to control the current rising rate and the reverse current peak.

It can be understood that in the current rising stage (t1-t2), the gate-source voltage _Vgs closely follows the capacitor voltage VC1. According to the relationship that the drain current change rate is proportional to the gate-source voltage _Vgs change rate, by controlling the rise time of the capacitor voltage VC1, the gate-source voltage change rate can be controlled, thereby controlling the current rise rate and the reverse current peak.

Specifically, in the current rising stage (t1-t2), the gate-source voltage _Vgs closely follows the capacitor voltage VC1. According to the positive correlation between the drain current change rate and the gate-source voltage _Vgs change rate, the change rate of the capacitor voltage VC1 can be controlled by controlling the values of _L1 , _R1 and _C1 . This can control the gate-source voltage change rate of the silicon carbide MOSFET, thereby controlling its drain current rise rate and reverse current spike.

Furthermore, in one embodiment of the present invention, in the voltage drop stage, the first capacitor voltage VC1 continues to increase from the Miller voltage to the driving voltage VCC, generating a large gate current on the first gate driving resistor R _gon1 to charge the Miller capacitor, thereby accelerating the voltage drop process and reducing turn-on loss.

It can be understood that in the voltage drop phase (t2-t3), the first capacitor voltage VC1 continues to increase from the Miller voltage to VCC, generating a larger gate current on the smaller resistor _Rgon1 to charge the Miller capacitor, accelerating the voltage drop process and reducing the turn-on loss. In the voltage drop phase (t2-t3), the gate current quickly rises from a smaller value Ic to a larger value Iv, accelerating the voltage drop process and reducing the turn-on loss. By adjusting the value of Vref, the moment when MOson is turned off can be adjusted.

Furthermore, in one embodiment of the present invention, in the stable conduction stage, as the first capacitor voltage VC1 increases, the gate-source voltage of the MOS tube MOSON decreases. When the gate-source voltage is less than the threshold voltage, MOSON is turned off, and the gate resistance R _gon is the sum of the first gate drive resistance R _gon1 and the second gate drive resistance R _gon2 .

In one embodiment of the present invention, in the stable conduction stage, the gate damping resistance R _gon is large, the damping factor is large, and the gate voltage overshoot is small.

In one embodiment of the present invention, when the gate damping resistance R _gon is large enough, the damping factor is greater than 1, and the gate voltage overshoot is completely suppressed.

The gate current flow path and equivalent circuit in the t3-t4 stage are shown in Figure 8 and Figure 9 respectively. In the stable conduction stage (t3-t4), as VC1 increases, the MOson gate-source voltage decreases. When its gate-source voltage is less than the threshold voltage, MOson is turned off, and the gate resistance R _gon is equal to the sum of R _gon1 and R _gon2 . Gate voltage overshoot usually occurs in the t3-t4 stage. At this time, the gate damping resistance R _gon is large, the damping factor is large, and the gate voltage overshoot is small. When R _gon is large enough, the damping factor can be greater than 1, and the gate voltage overshoot can be completely suppressed.

Specifically, t3-t4: In this stage, the capacitor voltage VC1 continues to increase, and the MOMon gate-source voltage is the difference between Vref and VC1. As VC1 increases, the MOMon gate-source voltage will decrease. When the MOMon gate-source voltage is lower than its threshold voltage, MOMon is turned off, and the gate resistance changes from R _gon1 to R _gon , where R _gon is the sum of R _gon1 and R _gon2 , and R _gon2 is a larger value, then the gate resistance R _gon is a larger value. Gate voltage overshoot usually occurs in the t3-t4 stage. In this stage, the gate damping resistance R _gon is large, the damping factor is large, and the gate voltage overshoot is small. When R _gon is large enough, the damping factor can be greater than 1, and the gate voltage overshoot can be completely suppressed.

According to the open-loop drive circuit for optimizing the turn-on waveform of the silicon carbide MOSFET according to the embodiment of the present invention, the transient processes of the current rising stage and the voltage falling stage can be independently controlled, and the rise time of the capacitor voltage VC1 can be increased to control the reverse current spike, but the gate resistance is very small, which can accelerate the voltage drop transient process and reduce the turn-on loss, breaking the contradiction between the reverse current spike and the turn-on loss under the traditional drive circuit, and can suppress the gate voltage overshoot without affecting the turn-on speed. By adding a larger gate resistance, the gate voltage overshoot is suppressed, but it does not affect the transient process and will not affect the turn-on speed of the silicon carbide MOSFET.

In the description of the present invention, it is to be understood that the terms “center”, “longitudinal”, “lateral”, “length”, “width”, “thickness”, “up”, “down”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, “clockwise”, “counterclockwise”, “axial”, “radial”, “circumferential”, etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims (9)

1. An open-loop drive circuit for optimizing the turn-on waveform of a silicon carbide MOSFET, comprising: A driving voltage waveform generator, used for generating a driving voltage waveform with a preset rising edge; The variable gate drive resistance control circuit is used to control the gate drive resistance at different stages of the turn-on transient process, wherein: In the current rising stage, the gate-source voltage change rate of the silicon carbide MOSFET is consistent with the driving voltage rising change rate, so as to control the current rising change rate and the reverse current by controlling the driving voltage rising change rate; in the voltage falling stage, the gate current is increased to accelerate the voltage falling process and reduce the turn-on loss; in the stable conduction stage, the gate damping resistance is increased to suppress the gate voltage overshoot without affecting the switching speed; Wherein, the variable gate drive resistance control circuit comprises: a first gate drive resistor R _gon1 and a second gate drive resistor R _gon2 , wherein the resistance of the second gate drive resistor R _gon2 is greater than the resistance of the first gate drive resistor R _gon1 ; MOS tube MOMon, in the current rising stage and the voltage falling stage, the MOS tube MOMon is in the on state, and the gate resistance is the first gate driving resistance R _gon1 ; and in the stable conduction stage, the MOS tube MOMon is in the off state, and the gate resistance is the sum of the first gate driving resistance R _gon1 and the second gate driving resistance R _gon2 . 2. The open-loop drive circuit for optimizing the turn-on waveform of a silicon carbide MOSFET according to claim 1, wherein the drive voltage waveform generator comprises: A first capacitor C ₁ ; An inductor L ₁ and a first resistor R ₁ , wherein the inductor L ₁ and the first resistor R ₁ are connected in parallel to each other and are both connected to the first capacitor C ₁ to charge the first capacitor C ₁ . 3. The open-loop drive circuit for optimizing the turn-on waveform of the silicon carbide MOSFET according to claim 2 is characterized in that the drive voltage VCC charges the first capacitor _C1 through the inductor _L1 and the first resistor _R1 connected in parallel, the voltage across the first capacitor _C1 has a rise time, and the totem pole output voltage closely follows the voltage of the first capacitor _C1 . 4 . The open-loop driving circuit for optimizing the turn-on waveform of a silicon carbide MOSFET according to claim 3 , wherein the values of the inductor L ₁ , the first resistor R ₁ and the first capacitor C ₁ are adjusted to achieve a rising rate of change of the driving voltage VCC. 5 . 5. The open-loop drive circuit for optimizing the turn-on waveform of a silicon carbide MOSFET according to claim 1 is characterized in that, in the current rising stage, the gate-source voltage Vgs closely follows the first capacitor voltage VC1, and according to the relationship that the drain current change rate is proportional to the gate-source voltage Vgs change rate, the rise time of the first capacitor voltage VC1 is controlled, and then the gate-source voltage change rate is controlled to control the current rise rate and the reverse current peak. 6. The open-loop drive circuit for optimizing the turn-on waveform of a silicon carbide MOSFET according to claim 5 is characterized in that, in the voltage drop stage, the first capacitor voltage VC1 continues to increase from the Miller voltage to the drive voltage VCC, and a large gate current is generated on the first gate drive resistor R _gon1 to charge the Miller capacitor, thereby accelerating the voltage drop process and reducing the turn-on loss. 7. The open-loop drive circuit for optimizing the turn-on waveform of the silicon carbide MOSFET according to claim 1 is characterized in that, in the stable conduction stage, as the first capacitor voltage VC1 increases, the gate-source voltage of the MOS tube MOSON decreases, and when the gate-source voltage is less than the threshold voltage, MOSON is turned off, and the gate damping resistor R _gon is the sum of the first gate drive resistor R _gon1 and the second gate drive resistor R _gon2 . 8. The open-loop drive circuit for optimizing the turn-on waveform of a silicon carbide MOSFET according to claim 7, characterized in that, in the stable conduction stage, the gate damping resistance R _gon is large, the damping factor is large, and the gate voltage overshoot is small. 9. The open-loop drive circuit for optimizing the turn-on waveform of a silicon carbide MOSFET according to claim 8, characterized in that when the gate damping resistance R _gon is large enough, the damping factor is greater than 1, and the gate voltage overshoot is completely suppressed.