CN117650721B - Wide voltage multimode BLDC driving integrated circuit, application circuit and power consumption control method - Google Patents

Wide voltage multimode BLDC driving integrated circuit, application circuit and power consumption control method Download PDF

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Publication number
CN117650721B
CN117650721B CN202410124614.4A CN202410124614A CN117650721B CN 117650721 B CN117650721 B CN 117650721B CN 202410124614 A CN202410124614 A CN 202410124614A CN 117650721 B CN117650721 B CN 117650721B
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circuit
driving
mos tube
switch
comparator
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CN117650721A (en
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杨波
杨军
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Xi'an Lattice Huili Microelectronics Co ltd
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Xi'an Lattice Huili Microelectronics Co ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P6/00—Arrangements for controlling synchronous motors or other dynamo-electric motors using electronic commutation dependent on the rotor position; Electronic commutators therefor
    • H02P6/08—Arrangements for controlling the speed or torque of a single motor
    • H02P6/085—Arrangements for controlling the speed or torque of a single motor in a bridge configuration
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0009—Devices or circuits for detecting current in a converter
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0032—Control circuits allowing low power mode operation, e.g. in standby mode
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The invention discloses a wide-voltage multimode BLDC driving integrated circuit, wherein a driving integrated circuit U3 is integrated with a first logic control module U2, an LDO power supply module, a pre-driving module and a step-up/down circuit U1; the step-up/step-down circuit U1 includes a first switch K11, a second switch K12, a third switch K21, a fourth switch K22, a first comparator CMP1, and a second comparator CMP2. The invention also discloses an application circuit of the wide-voltage multimode BLDC drive integrated circuit. The invention also discloses a power consumption control method of the wide-voltage multimode BLDC drive integrated circuit. The invention has simple structure and reasonable design, integrates the power supply circuit and the driving circuit into a whole, and adds the step-up and step-down circuit, thereby greatly widening the lower limit of the working voltage range of the driving circuit and prolonging the service life of the battery; the multi-mode working mode is adopted, so that the circuit power consumption is reduced, and the standby time is prolonged.

Description

Wide voltage multimode BLDC driving integrated circuit, application circuit and power consumption control method
Technical Field
The invention belongs to the technical field of motor drive control, and particularly relates to a wide-voltage multimode BLDC drive integrated circuit, an application circuit and a power consumption control method.
Background
With the increasing use of battery powered applications in portable fields such as industry, agriculture, household appliances, consumer electronics, etc., how to extend the standby time of a device has become an important challenge.
The traditional brushless direct current motor (Brushless Direct Current Motor, BLDC) driving circuit is composed of a micro control unit (Microcontroller Unit; MCU) +low dropout linear voltage stabilizer (Low dropout regulator; LDO) +predriver (Predrv), and the MCU controls the Predrv driving motor; the 5V output of the LDO supplies power for the MCU and the low-voltage part of the Predrv; the 12V output of the LDO is used for driving and supplying power for Predrv; predrv detects motor current through Rsense resistor to realize protection function.
Major drawbacks of existing battery powered, BLDC drive technology include: 1 has a narrow operating voltage range. For example, using 5 batteries, the initial voltage is 21V, when the voltage drops to 12V,the normal operation of 12V of the LDO cannot be ensured, and the driving capability of the BLDC is indirectly influenced; 2 the current detection power consumption is large. Power p=i 2 Rsense, I denotes the current flowing through resistor Rsense, with greater drive current, greater power loss resulting in greater Rsense resistor volume; 3, the structure is complex, and the application cost is high. The driving circuit needs independent LDO power supply, bootstrapping diode and PCB layout and wiring are inconvenient. 4, the working mode is single, and the standby power consumption is high.
Thus, there remains a need for improvement in the art.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a wide-voltage multimode BLDC driving integrated circuit, an application circuit and a power consumption control method, which have simple structure and reasonable design, integrate a power supply circuit and a driving circuit into a whole, and add a step-up and step-down circuit, thereby greatly widening the lower limit of the working voltage range of the driving circuit and prolonging the service life of a battery; the standby time is increased by adopting the multimode working mode.
In order to solve the technical problems, the invention adopts the following technical scheme: the wide-voltage multimode BLDC driving integrated circuit is characterized in that a driving integrated circuit U3 is integrated with a first logic control module U2, an LDO power supply module, a pre-driving module, a step-up and step-down circuit U1 and a nondestructive current detection module; the first logic control module U2 provides control instructions for the pre-driving module and the buck-boost circuit U1; the LDO power supply module supplies power to the first logic control module U2 and the pre-drive module and provides reference voltage for the buck-boost circuit U1; the pre-driving module is used for outputting driving signals to the three-phase full-bridge driving circuit; the step-up/step-down circuit U1 is configured to: outputting a high-side driving voltage and a low-side driving voltage for supplying power to the pre-driving module, wherein when the step-up/step-down circuit U1 works in a step-up mode, the high-side driving voltage is increased; the nondestructive current detection module is used for detecting three-phase current of the three-phase full-bridge driving circuit; the buck-boost circuit U1 includes a first switch K11, a second switch K12, a third switch K21, a fourth switch K22, a first comparator CMP1, and a second comparator CMP2; one end of the first capacitor C1 is connected with one end of the second switch K12 and one end of the third switch K21The other end of the third switch K21 is connected with the power supplyThe other end of the second switch K12 is grounded; the other end of the first capacitor C1 is connected with the connecting end of one end of the first switch K11 and one end of the fourth switch K22, and the other end of the first switch K11 is divided into five paths, one path is connected with a power supply->The second path is connected with one end of a second capacitor C2, the third path is connected with the anode of a diode D1, the fourth path is connected with a first branch of a normally closed contact of a fifth switch K1, and the fifth path is connected with one end of a resistor R5 and a connecting end of one end of a grid electrode of a MOS tube P6; the other end of the fourth switch K22 is divided into four paths, one path is connected with the other end of the second capacitor C2, the second path is connected with the cathode of the diode D1, the third path is connected with a normally open contact of the fifth switch K1, the fourth path is connected with one end of a resistor R0, and the other end of the resistor R0 is connected with the source electrode of the MOS tube P6; the second branch of the normally closed contact of the fifth switch K1 is connected with the output end of a second comparator CMP2, the non-inverting input end of the second comparator CMP2 is connected with the other end of a resistor R5 and the connecting end of one end of a resistor R6, and the other end of the resistor R6 is grounded; the inverting input of the second comparator CMP2 is connected to the reference voltage +.>Connecting; the stationary contact of the fifth switch K1 is connected with the source electrode of the MOS tube P5, the grid electrode of the MOS tube P5 is connected with the output end of the amplifier AMP1, and the inverting input end of the amplifier AMP1 is connected with the reference voltage +.>The positive input end of the amplifier AMP1 is connected with the connecting end of one end of a resistor R3 and one end of a resistor R4, the other end of the resistor R3 is divided into three paths, the first path is connected with the drain electrode of a MOS tube P5, the second path is connected with one end of a capacitor C3, the other end of the capacitor C3 is grounded, and the third path is connected with a power supply>Connecting; another resistor R4One end of the device is grounded; the non-inverting input end of the first comparator CMP1 is connected with the connecting end of one end of a resistor R1 and one end of a resistor R2, the other end of the resistor R1 is connected with the drain electrode of a MOS tube P6, the other end of the resistor R2 is grounded, and the inverting input end of the first comparator CMP1 is connected with a reference voltage->The output end of the first comparator CMP1 is connected with the second logic control circuit U4; the second logic control circuit U4 is configured to output clock signals for controlling the first switch K11, the second switch K12, the third switch K21, and the fourth switch K22.
The wide-voltage multimode BLDC driving integrated circuit comprises a nondestructive current detection module, a voltage detection module and a voltage detection module, wherein the nondestructive current detection module comprises a three-stage PMOS current mirror, a comparator CMPA, a comparator CMPB and a comparator CMPC, the input end of the three-stage PMOS current mirror comprises an NMOS tube N7 and an MOS tube P1, the output branch of the three-stage PMOS current mirror comprises an MOS tube P2, an MOS tube P3 and an MOS tube P4 which are connected in parallel, and the in-phase input end of the amplifier AMP2 is connected with a reference voltageConnected with the source of NMOS transistor N7 and resistor R and the inverting input of amplifier AMP2 sense The connecting end of one end of (a) is connected with the resistor R sense The other end of the NMOS tube N7 is grounded, the drain electrode of the NMOS tube N7 is divided into two paths, one path is connected with the drain electrode of the MOS tube P1, and the other path is connected with the grid electrode of the MOS tube P1, the grid electrode of the MOS tube P2, the grid electrode of the MOS tube P3 and the connecting end of the grid electrode of the MOS tube P4; the drain electrode of the MOS tube P2 is divided into two paths, one path is connected with the inverting input end of the comparator CMPA, the second path is grounded through a resistor RSA, and the drain electrode of the MOS tube N2 is connected with the non-inverting input end of the comparator CMPA; the drain electrode of the MOS tube P3 is divided into two paths, one path is connected with the inverting input end of the comparator CMPB, the second path is grounded through a resistor RSB, and the drain electrode of the MOS tube N4 is connected with the non-inverting input end of the comparator CMPB; the drain electrode of the MOS tube P4 is divided into two paths, one path is connected with the inverting input end of the comparator CMPC, the second path is grounded through a resistor RSC, and the drain electrode of the MOS tube N6 is connected with the non-inverting input end of the comparator CMPC; the source electrode of the MOS tube P1, the source electrode of the MOS tube P2, the source electrode of the MOS tube P3 and the source electrode of the MOS tube P4 are connected with a power supply VCC; the output of the comparator CMPA and the output of the comparator CMPBAnd the output end of the comparator CMPC is used as the input of an OR gate logic circuit, and the output of the OR gate logic circuit is connected with the first logic control module U2.
In the wide-voltage multimode BLDC driving integrated circuit, a high-voltage isolation circuit is connected between the source of the MOS transistor N2 and the non-inverting input terminal of the comparator CMPA, between the source of the MOS transistor N4 and the non-inverting input terminal of the comparator CMPB, and between the source of the MOS transistor N6 and the non-inverting input terminal of the comparator CMPC.
The wide-voltage multimode BLDC driving integrated circuit comprises an A-phase driving circuit, a B-phase driving circuit and a C-phase driving circuit which are identical in structure, wherein the A-phase driving circuit comprises a high-side driving unit and a low-side driving unit.
The application circuit of the wide-voltage multimode BLDC drive integrated circuit comprises a drive integrated circuit U3 and a peripheral circuit, wherein the peripheral circuit comprises a battery power supply module, an MCU control chip and a three-phase full-bridge drive circuit, a three-phase output end of the three-phase full-bridge drive circuit is connected with a brushless direct current motor, the drive integrated circuit U3 is integrated with a first logic control module U2, an LDO power supply module, a pre-drive module and a buck-boost circuit U1, the first logic control module U2 is connected with the MCU control chip, and the battery power supply module is connected with the LDO power supply module through a switch K.
The peripheral circuit comprises a charge pump circuit, wherein the charge pump circuit comprises a capacitor C5, and one end of the capacitor C5 is connected with a power supplyThe other end of the capacitor C5 is connected with the output of the step-up/step-down circuit U1 in two ways>The other path is connected with a high-voltage driving circuit of the pre-driving module.
The application circuit of the wide-voltage multimode BLDC drive integrated circuit comprises an upper bridge arm and a lower bridge arm, wherein the upper bridge arm comprises a MOS tube N1, a MOS tube N3 and a MOS tube N5, the lower bridge arm comprises a MOS tube N2, a MOS tube N4 and a MOS tube N6, the pre-drive module comprises an A-phase drive circuit, a B-phase drive circuit and a C-phase drive circuit which are identical in structure, the A-phase drive circuit comprises a high-side drive unit and a low-side drive unit, the high-side drive unit drives one power MOS tube in the upper bridge arm, and the low-side drive unit drives one power MOS tube in the lower bridge arm.
The power consumption control method of the wide-voltage multimode BLDC driving integrated circuit is realized based on the driving integrated circuit U3 and the peripheral circuit, and comprises the following steps of:
step one, powering up a battery power supply module,
judging whether an enabling pin of the LDO power supply module is at a high level, if so, starting the LDO power supply module, enabling other module circuits to be inoperative, and driving the integrated circuit U3 to enter an ultralow-power-consumption standby mode; if the voltage is low, driving the integrated circuit U3 to enter a zero power consumption standby mode;
step three, judging whether the first logic control module U2 receives the instruction of the MCU control chip, if so, starting the step-up and step-down circuit U1, and whenAnd +.>After the voltage is normal, driving the integrated circuit U3 to enter a normal working mode, and entering a step four; if the MCU instruction is not received, driving the integrated circuit U3 to enter an ultralow power consumption standby mode;
step four, starting timing, and driving the integrated circuit U3 to enter an ultralow-power-consumption standby mode when the timing duration exceeds a timing threshold value and the first logic control module U2 does not receive an instruction; and returning to the third step.
The power consumption control method of the wide-voltage multimode BLDC drive integrated circuit has a timing threshold of 16ms.
Compared with the prior art, the invention has the following advantages:
1. the invention has simple structure, reasonable design and convenient realization, use and operation.
2. The invention integrates the power supply circuit and the driving circuit into a whole, thereby simplifying the application.
3. The invention adopts the step-up and step-down circuit U1, can widen the working voltage range of the BLDC driving circuit supplied by the 5 batteries to 5.5V-21V, greatly widens the lower limit of the working voltage range of the driving circuit, and prolongs the service life of the batteries.
4. The invention adopts nondestructive current detection, and flows through R sense The current level of the power supply is microampere level, the power consumption is basically negligible, the power consumption is reduced, and the efficiency is improved.
5. The invention adopts a multimode working mode, reduces the power consumption of a circuit, realizes ultralow power consumption standby, prolongs the standby time, and maximally prolongs the service life of a battery.
In conclusion, the invention has simple structure and reasonable design, integrates the power supply circuit and the driving circuit, and adds the step-up and step-down circuit, thereby greatly widening the lower limit of the working voltage range of the driving circuit and prolonging the service life of the battery; the multi-mode working mode is adopted, so that the circuit power consumption is reduced, and the standby time is prolonged.
The technical scheme of the invention is further described in detail through the drawings and the embodiments.
Drawings
Fig. 1 is a schematic circuit diagram of the present invention.
Fig. 2 is a schematic circuit diagram of the buck-boost circuit U1 of the present invention.
Fig. 3 is a timing chart of the operation of the buck-boost circuit U1 of the present invention.
Fig. 4 is a schematic circuit diagram of a non-destructive current sensing circuit according to the present invention.
Fig. 5 is a schematic circuit diagram of an application circuit of the driving integrated circuit of the present invention.
Fig. 6 is a schematic circuit diagram of another application circuit of the driving integrated circuit of the present invention.
FIG. 7 is a flow chart of a control method of the present invention.
Detailed Description
The method of the present invention will be described in further detail with reference to the accompanying drawings.
It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be combined with each other. The invention will be described in detail below with reference to the drawings in connection with embodiments.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments in accordance with the present application. As used herein, the singular is also intended to include the plural unless the context clearly indicates otherwise, and furthermore, it is to be understood that the terms "comprises" and/or "comprising" when used in this specification are taken to specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof.
It should be noted that the terms "first," "second," and the like in the description and claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that embodiments of the present application described herein may be capable of being practiced otherwise than as specifically illustrated and described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Spatially relative terms, such as "above … …," "above … …," "upper surface at … …," "above," and the like, may be used herein for ease of description to describe one device or feature's spatial location relative to another device or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "above" or "over" other devices or structures would then be oriented "below" or "beneath" the other devices or structures. Thus, the exemplary term "above … …" may include both orientations of "above … …" and "below … …". The device may also be positioned in other different ways (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
Example 1
As shown in fig. 1, the wide voltage multimode BLDC driving integrated circuit of the present invention, the driving integrated circuit U3 is integrated with a first logic control module U2, an LDO power supply module, a pre-driving module, a buck-boost circuit U1 and a lossless current detection module; the first logic control module U2 provides control instructions for the pre-driving module and the buck-boost circuit U1; the LDO power supply module supplies power to the first logic control module U2 and the pre-drive module and provides reference voltage for the buck-boost circuit U1; the pre-driving module is used for outputting driving signals to the three-phase full-bridge driving circuit; the step-up/step-down circuit U1 is configured to: outputting a high-side driving voltage and a low-side driving voltage for supplying power to the pre-driving module, wherein when the step-up/step-down circuit U1 works in a step-up mode, the high-side driving voltage is increased; the nondestructive current detection module is used for detecting three-phase current of the three-phase full-bridge driving circuit.
As shown in fig. 1, the control signal generated by the first logic control module U2 is not limited to providing a control command to the pre-driving module and the buck-boost circuit U1, but may also include other internal control signals. The output voltage of the LDO power supply module is not limited to power for the first logic control module U2 and the pre-driving module, and provides a reference voltage for the buck-boost circuit U1, and may also provide voltages for other power consumption modules.
The integrated circuit integrates the power supply circuit and the driving circuit into a whole, simplifies application, and adds the step-up and step-down circuit U1 for widening the working voltage range. By adopting a nondestructive current detection technology, the power consumption is reduced, and meanwhile, the requirement on a sampling resistor is reduced; by adopting the multimode working mode, the standby mode with zero power consumption and the standby mode with ultra-low power consumption can be realized, and the service life of the battery is greatly prolonged.
It should be noted that the input voltage of the LDO power supply module comes from the battery power supply module. The operating voltage range of the BLDC driving circuit powered by the battery determines the service life of the battery, for example, the conventional 5-battery power supply, the initial voltage is 21V, the operating voltage range of the conventional BLDC driving circuit can be only between 12.5-21V, and the service life of the battery is reduced. In order to widen the working voltage range of the BLDC driving circuit, the LDO power supply module in FIG. 1 adopts an LDO with an enabling end INH, the output voltage of the LDO power supply module is fixed to be 5V, and calculated by a given minimum voltage difference of 0.5V, the minimum output voltage of the LDO power supply module is 5.5V, so that the working voltage range of the BLDC driving circuit powered by a 5-battery can be widened to 5.5V-21V, the lower limit of the working voltage range of the driving circuit is greatly widened, and the service life of the battery is prolonged.
As shown in fig. 2, in the present embodiment, the buck-boost circuit U1 includes a first switch K11, a second switch K12, a third switch K21, a fourth switch K22, a first comparator CMP1, and a second comparator CMP2; one end of the first capacitor C1 is connected with one end of the second switch K12 and one end of the third switch K21, and the other end of the third switch K21 is connected with a power supplyThe other end of the second switch K12 is grounded; the other end of the first capacitor C1 is connected with the connecting end of one end of the first switch K11 and one end of the fourth switch K22, and the other end of the first switch K11 is divided into five paths, one path is connected with a power supply->The second path is connected with one end of a second capacitor C2, the third path is connected with the anode of a diode D1, the fourth path is connected with a first branch of a normally closed contact of a fifth switch K1, and the fifth path is connected with one end of a resistor R5 and a connecting end of one end of a grid electrode of a MOS tube P6; the other end of the fourth switch K22 is divided into four paths, one path is connected with the other end of the second capacitor C2, the second path is connected with the cathode of the diode D1, the third path is connected with a normally open contact of the fifth switch K1, the fourth path is connected with one end of a resistor R0, and the other end of the resistor R0 is connected with the source electrode of the MOS tube P6; the second branch of the normally-closed contact of the fifth switch K1 is connected with the output end of the second comparator CMP2, the non-inverting input end of the second comparator CMP2 is connected with the other end of the resistor R5The connecting end of one end of the resistor R6 is connected with the ground, and the other end of the resistor R6 is grounded; the inverting input of the second comparator CMP2 is connected to the reference voltage +.>Connecting; the stationary contact of the fifth switch K1 is connected with the source electrode of the MOS tube P5, the grid electrode of the MOS tube P5 is connected with the output end of the amplifier AMP1, and the inverting input end of the amplifier AMP1 is connected with the reference voltage +.>The positive input end of the amplifier AMP1 is connected with the connecting end of one end of a resistor R3 and one end of a resistor R4, the other end of the resistor R3 is divided into three paths, the first path is connected with the drain electrode of a MOS tube P5, the second path is connected with one end of a capacitor C3, the other end of the capacitor C3 is grounded, and the third path is connected with a power supply>Connecting; the other end of the resistor R4 is grounded; the non-inverting input end of the first comparator CMP1 is connected with the connecting end of one end of a resistor R1 and one end of a resistor R2, the other end of the resistor R1 is connected with the drain electrode of a MOS tube P6, the other end of the resistor R2 is grounded, and the inverting input end of the first comparator CMP1 is connected with a reference voltage->The output end of the first comparator CMP1 is connected with the second logic control circuit U4; the second logic control circuit U4 is configured to output clock signals for controlling the first switch K11, the second switch K12, the third switch K21, and the fourth switch K22.
As shown in fig. 2, the buck-boost circuit U1 is configured such that the first switch K11/second switch K12 and the third switch K21/fourth switch K22 are two-phase non-overlapping clocks, and charge the first capacitor C1 in the clock cycle of K11/K12; in the period of K21/K22, the first capacitor C1 is discharged to charge the second capacitor C2, so that the other end of the second capacitor C2 is the VCP enabling end. The voltage at the VCP enable terminal is=/>+/>。/>Representing the voltage of the second capacitor.
The voltage of the VCP enabling end is controlled by a resistor R0, a MOS tube P6, a resistor R1 and a resistor R2Dividing the voltage to obtain an input voltage of the non-inverting input terminal of the first comparator CMP1, wherein the input voltage of the inverting input terminal of the first comparator CMP1 is the reference voltage +.>When the voltage of the non-inverting input terminal is greater than the voltage of the inverting input terminal, the output terminal of the first comparator CMP1 is at a high level, the second logic control circuit U4 does not work, the clock signals of K11/K12 and K21/K22 are closed, and the circuit stops working. Once the voltage at the non-inverting input terminal of the first comparator CMP1 is smaller than the voltage at the inverting input terminal, the output terminal of the first comparator CMP1 is at a low level, the second logic control circuit U4 operates, the clocks of K11/K12, K21/K22 are recovered, and the circuit operates.
In actual use, as shown in fig. 2, the analytical circuit is available,，/>represents the voltage between the gate and the source of MOS transistor P6, ">Represents the current through MOS transistor P6, +.>Representing the device-related parameters of MOS transistor P6, wherein +.>Representation ofMobility of MOS transistor P6 +.>The specific capacitance of the gate oxide of the MOS transistor P6 is shown,represents the width of MOS transistor P6, +.>Represents the length of MOS tube P6, +.>Represents the channel threshold voltage of MOS transistor P6, < ->The resistance value of the resistor R0 is shown.
Specifically, the voltage at the non-inverting input terminal of the first comparator CMP1 isThe voltage at the inverting input of the first comparator CMP1 is +.>When->The output end of the first comparator CMP1 is at a high level, the second logic control circuit U4 does not work, clock signals of K11/K12 and K21/K22 are closed, the circuit work is stopped, the step-up circuit stops working, and the circuit works in a step-down mode. When->The output end of the first comparator CMP1 is at a low level, the second logic control circuit U4 works, the clocks of K11/K12 and K21/K22 are recovered, and the circuit works.
Capacitor C1 and capacitor C2 are alternately charged, and the circuit operates in a boost mode, as shown in FIG. 3, with voltageRise in voltageThe power supply circuit is used for supplying power to the high-side driving unit, so that the voltage working range of the circuit is greatly widened.
In one possible embodiment, the resistance value of the resistor R2 is,. Thus->The output of the first comparator CMP1 is high. When->The output of the first comparator CMP1 is low.
The amplifier AMP1, the MOS tube P5, the resistor R3, the resistor R4 and the capacitor C3 form a PNP voltage stabilizer, and the output of the PNP voltage stabilizer isPower is supplied to the low side drive unit. The source voltage of the MOS tube P5 is divided by a resistor R3 and a resistor R4, and the divided voltage and a reference voltageThe output is regulated by the amplifier AMP1, in comparison.
By means of resistance R5, resistance R6 detectionVoltage (V)>The voltage is divided by the resistor R5 and the resistor R6, < >>Is used as the non-inverting input terminal of the second comparator CMP2 and the reference voltage of the inverting input terminal of the second comparator CMP2>Comparing when the non-inverting input terminal of the second comparator CMP2 is higher than the non-inverting input terminal of the second comparator CMP2When the inverting input terminal is in the inverting input terminal, the output of the second comparator CMP2 is high, and the fifth switch K1 is switched to the normally-closed contact communication +.>Voltage (V)>The voltage is connected to the source electrode of the MOS tube P5; when the noninverting input terminal of the second comparator CMP2 is lower than the inverting input terminal of the second comparator CMP2, the output of the second comparator CMP2 is low, switching the fifth switch K1 to the normally open contact communication +.>Voltage (V)>The voltage is connected to the source of MOS transistor P5. Fig. 3 is an operation timing chart of the buck-boost circuit U1.
In this embodiment, the device includes a battery power supply module that provides VBAT voltage, where the battery power supply module is connected to the LDO power supply module through a switch K, and the VBAT voltage supplies power to the three-phase full bridge driving circuit.
In this embodiment, as shown in fig. 4, the lossless current detection module includes a three-stage PMOS current mirror, a comparator CMPA, a comparator CMPB and a comparator CMPC, the input end of the three-stage PMOS current mirror includes an NMOS transistor N7 and an MOS transistor P1, the output branch of the three-stage PMOS current mirror includes an MOS transistor P2, an MOS transistor P3 and an MOS transistor P4 connected in parallel, and the non-inverting input end of the amplifier AMP2 is connected with a reference voltageConnected with the source of NMOS transistor N7 and resistor R and the inverting input of amplifier AMP2 sense The connecting end of one end of (a) is connected with the resistor R sense The other end of the NMOS tube N7 is grounded, the drain electrode of the NMOS tube N7 is divided into two paths, one path is connected with the drain electrode of the MOS tube P1, and the other path is connected with the grid electrode of the MOS tube P1, the grid electrode of the MOS tube P2, the grid electrode of the MOS tube P3 and the connecting end of the grid electrode of the MOS tube P4; the drain electrode of the MOS tube P2 is divided into two paths, one path is connected with the inverting input end of the comparator CMPA, the second path is grounded through a resistor RSA, and the drain electrode of the MOS tube N2 is identical with the comparator CMPAThe phase input ends are connected; the drain electrode of the MOS tube P3 is divided into two paths, one path is connected with the inverting input end of the comparator CMPB, the second path is grounded through a resistor RSB, and the drain electrode of the MOS tube N4 is connected with the non-inverting input end of the comparator CMPB; the drain electrode of the MOS tube P4 is divided into two paths, one path is connected with the inverting input end of the comparator CMPC, the second path is grounded through a resistor RSC, and the drain electrode of the MOS tube N6 is connected with the non-inverting input end of the comparator CMPC; the source electrode of the MOS tube P1, the source electrode of the MOS tube P2, the source electrode of the MOS tube P3 and the source electrode of the MOS tube P4 are connected with a power supply VCC; the output end of the comparator CMPA, the output end of the comparator CMPB and the output end of the comparator CMPC are used as inputs of an or gate logic circuit, and the output of the or gate logic circuit is connected with the first logic control module U2.
In order to detect the working current of a motor, the current sampling is carried out through a series resistor, so that larger power consumption can be caused; b-phase current detection is carried out by detecting the voltage difference between SB voltage and LSS voltage, namely the drain-source voltage of the power switch N4 tube; c-phase current detection is performed by detecting the voltage difference between the SC voltage and the LSS voltage, namely the drain-source voltage of the power switch N6 tube.
The output end of the comparator CMPA, the output end of the comparator CMPB and the output end of the comparator CMPC are used as the input of an OR gate logic circuit, when all the inputs are low, the output is low, namely three-phase current detection is qualified, the output end of the comparator CMPA, the output end of the comparator CMPB and the output end of the comparator CMPC are all in low level, and the OR gate logic circuit outputs in low level; when any one of the phase currents is not qualified, namely one of the outputs of the comparator CMPA, the comparator CMPB or the comparator CMPC is at a high level, the OR gate logic circuit outputs at a high level.
The current detection topology is shown in the in-frame structure of fig. 4. The on-resistance of the N2 tube is R dson2 ，For reference voltage, +.>A BLDC working current I is the resistance value of the resistor RSA LCP The method comprises the following steps: />As can be seen from the above formula, by providing R sense The resistance value of the resistor can regulate the working current of the BLDC and flow through R sense The current level of (2) is microampere level, the power consumption is basically negligible, and thus, the current detection is lossless.
In this embodiment, a high-voltage isolation circuit is connected between the drain of the MOS transistor N2 and the non-inverting input terminal of the comparator CMPA, between the drain of the MOS transistor N4 and the non-inverting input terminal of the comparator CMPB, and between the drain of the MOS transistor N6 and the non-inverting input terminal of the comparator CMPC, respectively.
In this embodiment, the pre-driving module includes an a-phase driving circuit, a B-phase driving circuit, and a C-phase driving circuit with the same structure, where the a-phase driving circuit includes a high-side driving unit and a low-side driving unit.
When in actual use, the high-side driving unit drives one power MOS tube in the upper bridge arm, and the low-side driving unit drives one power MOS tube in the lower bridge arm. In one possible embodiment, the high-side driving unit of the a-phase driving circuit drives the MOS transistor N1, the low-side driving unit of the a-phase driving circuit drives the MOS transistor N2, the high-side driving unit of the B-phase driving circuit drives the MOS transistor N3, the low-side driving unit of the B-phase driving circuit drives the MOS transistor N4, the high-side driving unit of the C-phase driving circuit drives the MOS transistor N5, and the low-side driving unit of the C-phase driving circuit drives the MOS transistor N6.
Example two
As shown in fig. 5 and 6, an application circuit of a wide-voltage multimode BLDC driving integrated circuit in this embodiment includes a driving integrated circuit U3 and a peripheral circuit, the peripheral circuit includes a battery power supply module, an MCU control chip and a three-phase full-bridge driving circuit, a three-phase output end of the three-phase full-bridge driving circuit is connected to a brushless dc motor, the driving integrated circuit U3 is integrated with a first logic control module U2, an LDO power supply module, a pre-driving module and a buck-boost circuit U1, the first logic control module U2 is connected to the MCU control chip, and the battery power supply module is connected to the LDO power supply module through a switch K.
In fig. 5, VBAT represents the voltage of the battery powered module.
The working principle is as follows: the power supply module of the battery is electrified, whether the switch K is closed or not is judged, whether an enabling pin of the LDO power supply module is at a high level or not is judged, if the enabling pin is at a low level, the integrated circuit U3 is driven to enter a zero power consumption standby mode, if the enabling pin is at the high level, the LDO power supply module is started, other module circuits do not work, and the integrated circuit U3 is driven to enter an ultralow power consumption standby mode; judging whether the first logic control module U2 receives the instruction of the MCU control chip, if so, starting the voltage boosting and reducing circuit U1, and whenAnd +.>After the voltage is normal, driving the integrated circuit U3 to enter a normal working mode, and entering a step four; if the instruction of the MCU control chip is not received, driving the integrated circuit U3 to enter an ultralow-power-consumption standby mode; starting timing, and driving the integrated circuit U3 to enter an ultralow-power-consumption standby mode when the timing duration exceeds a timing threshold value and the first logic control module U2 does not receive an instruction; and returning to the third step. By the multimode working mode, low power consumption is realized.
The circuit is suitable for a BLDC driving circuit with relatively small driving power and can realize 100% PWM speed regulation.
In this embodiment, the peripheral circuit includes a charge pump circuit including a capacitor C5, one end of the capacitor C5 and a power supplyThe other end of the capacitor C5 is connected with the output of the step-up/step-down circuit U1 in two ways>The other path is connected with a high-voltage driving circuit of the pre-driving module.
In this embodiment, the three-phase full-bridge driving circuit includes an upper bridge arm and a lower bridge arm, the upper bridge arm includes MOS transistors N1, N3, N5, the lower bridge arm includes MOS transistors N2, N4, N6, the pre-driving module includes an a-phase driving circuit, a B-phase driving circuit, and a C-phase driving circuit with the same structure, the a-phase driving circuit includes a high-side driving unit and a low-side driving unit, the high-side driving unit drives one power MOS transistor in the upper bridge arm, and the low-side driving unit drives one power MOS transistor in the lower bridge arm.
FIG. 5 shows a three-phase full-bridge driving circuit in which the input power of the high-side driving A corresponding to the MOS transistor N1 of the upper bridge arm isThe input power of the low-side drive A corresponding to the MOS tube N2 of the lower bridge arm is +.>。
In this embodiment, as shown in fig. 5, the driving integrated circuit U3 includes a charge pump circuit, the charge pump circuit includes a capacitor C5, one end of the capacitor C5 and a power supply voltageThe other end of the capacitor C5 is connected with the output of the step-up/step-down circuit U1>The voltages are connected.
By incorporating a charge pump circuit into a power supply circuit, a power supply voltage is supplied by the charge pump circuitAfter boosting, the high-voltage driving circuit is output and supplied to the pre-driving module, so that the driving voltages of three high-voltage driving output ends of the high-voltage driving circuit are all raised, and the overall switching speed of the MOS tube is improved.
In one possible embodiment, the driving integrated circuit U3 is shown as a whole chip, and then, as shown in fig. 6, the mcu is configured to send an instruction to the driving integrated circuit U3, where the driving integrated circuit U3 is externally connected to a three-phase full-bridge driving circuit, and three-phase output terminals of the three-phase full-bridge driving circuit are connected to the brushless dc motor M.
Example III
As shown in fig. 7, the power consumption control method of the wide voltage multimode BLDC driving integrated circuit of the present invention is implemented based on a driving integrated circuit U3 and a peripheral circuit, and includes the steps of:
step one, powering up a battery power supply module.
Judging whether an enabling pin of the LDO power supply module is at a high level, if so, starting the LDO power supply module, enabling other module circuits to be inoperative, and driving the integrated circuit U3 to enter an ultralow-power-consumption standby mode; if the voltage is low, the driving integrated circuit U3 enters a zero power consumption standby mode.
In one possible embodiment, the LDO power module uses an LDO with an enable pin to input a high and low level through an enable pin INH. When the enable pin INH is low, the LDO power supply module is turned off, and consumes only very low standby current. When the enable pin INH is high, the LDO power supply module is turned on.
In one possible embodiment, the low level is 0V and the high level is 5V.
In one possible embodiment, the circuit diagram of the LDO power module is the same as the circuit schematic of the voltage regulator model NCP 730.
Step three, judging whether the first logic control module U2 receives the instruction of the MCU control chip, if so, starting the step-up and step-down circuit U1, and whenAnd +.>After the voltage is normal, driving the integrated circuit U3 to enter a normal working mode, and entering a step four; if the MCU instruction is not received, the integrated circuit U3 is driven to enter an ultralow power consumption standby mode.
Step four, starting timing, and driving the integrated circuit U3 to enter an ultralow-power-consumption standby mode when the timing duration exceeds a timing threshold value and the first logic control module U2 does not receive an instruction; and returning to the third step.
To maximize the extension of battery life, the driver integrated circuit U3 adopts a multimode operating mode: zero power consumption standby mode, ultra-low power consumption standby mode, normal operating mode.
When the enabling pin INH of the LDO power supply module is at a low level or floats, the whole driving integrated circuit U3 stops working and is in a zero-power consumption standby mode; when the enable pin INH of the LDO power supply module is high, i.e. connected toWhen the voltage is applied, the driving integrated circuit U3 is started to be an LDO power supply module, and other circuits do not work, so that the power consumption is lower than 10uA, namely an ultra-low power consumption standby mode; after the first logic control circuit U2 receives the control instruction, the step-up and step-down circuit U1 is started immediately, and when +.>And +.>And after the voltage is normal, entering a normal working mode. The first logic control module U2 exceeds the timing threshold value and does not receive the instruction of the MCU control chip, and automatically enters an ultralow power consumption standby mode.
In one possible embodiment, the timing threshold is 16ms. It should be noted that the timing threshold is only an example, and not a limitation of the present invention, and any suitable time period for achieving the best performance is within the scope of the present invention.
Certain terminology is used throughout this application to refer to particular elements. Those of ordinary skill in the art will appreciate that a hardware manufacturer may refer to the same element by different names. The description and claims do not take the form of an element differentiated by name, but rather by functional differences. In this application, the device is described as a MOS transistor P or a MOS transistor N, some N-channel or P-channel device, or some N-type or P-type doped region, however, it will be appreciated by those of ordinary skill in the art that complementary devices may be implemented in accordance with the present invention. It will be appreciated by those of ordinary skill in the art that conductivity type refers to a mechanism by which electrical conduction occurs, such as by hole or electron conduction, so conductivity type does not relate to doping concentration but rather to doping type, such as P-type or N-type.
It will be appreciated by those of ordinary skill in the art that the terms "during", "when" and "when … …" as used herein in relation to circuit operation are not strict terms indicating an action that occurs immediately upon the start of a start-up action, but rather there may be some small but reasonable delay or delays between it and the reaction action (reaction) initiated by the start-up action, such as various transmission delays and the like. The word "about" or "substantially" is used herein to mean that an element value (element) has a parameter that is expected to be close to the stated value or position. However, as is well known in the art, there is always a slight deviation such that the value or position is difficult to strictly assume the stated value. It has been well established in the art that deviations of at least ten percent (10%) (at least twenty percent (20%)) for semiconductor doping concentrations are reasonable deviations from the exact ideal targets described.
The foregoing is merely an embodiment of the present invention, and the present invention is not limited thereto, and any simple modification, variation and equivalent structural changes made to the foregoing embodiment according to the technical matter of the present invention still fall within the scope of the technical solution of the present invention.

Claims (7)

1. The wide voltage multimode BLDC drive integrated circuit is characterized in that: the driving integrated circuit U3 is integrated with a first logic control module U2, an LDO power supply module, a pre-driving module, a step-up/step-down circuit U1 and a nondestructive current detection module;
the first logic control module U2 provides control instructions for the pre-driving module and the buck-boost circuit U1;
the LDO power supply module supplies power to the first logic control module U2 and the pre-drive module and provides reference voltage for the buck-boost circuit U1;
the pre-driving module is used for outputting driving signals to the three-phase full-bridge driving circuit;
the step-up/step-down circuit U1 is configured to: outputting a high-side driving voltage and a low-side driving voltage for supplying power to the pre-driving module, wherein when the step-up/step-down circuit U1 works in a step-up mode, the high-side driving voltage is increased;
the nondestructive current detection module is used for detecting three-phase current of the three-phase full-bridge driving circuit; the buck-boost circuit U1 includes a first switch K11, a second switch K12, a third switch K21, a fourth switch K22, a first comparator CMP1, and a second comparator CMP2;
one end of the first capacitor C1 is connected with one end of the second switch K12 and one end of the third switch K21, and the other end of the third switch K21 is connected with a power supplyThe other end of the second switch K12 is grounded;
the other end of the first capacitor C1 is connected with the connecting end of one end of the first switch K11 and one end of the fourth switch K22, and the other end of the first switch K11 is divided into five paths, one path is connected with a power supplyThe second path is connected with one end of a second capacitor C2, the third path is connected with the anode of a diode D1, the fourth path is connected with a first branch of a normally closed contact of a fifth switch K1, and the fifth path is connected with one end of a resistor R5 and a connecting end of one end of a grid electrode of a MOS tube P6; the other end of the fourth switch K22 is divided into four paths, one path is connected with the other end of the second capacitor C2, the second path is connected with the cathode of the diode D1, the third path is connected with a normally open contact of the fifth switch K1, the fourth path is connected with one end of a resistor R0, and the other end of the resistor R0 is connected with the source electrode of the MOS tube P6;
the second branch of the normally closed contact of the fifth switch K1 is connected with the output end of a second comparator CMP2, the non-inverting input end of the second comparator CMP2 is connected with the other end of a resistor R5 and the connecting end of one end of a resistor R6, and the other end of the resistor R6 is grounded; the inverting input of the second comparator CMP2 is connected to the reference voltageConnecting;
the stationary contact of the fifth switch K1 is connected with the source electrode of the MOS tube P5, the grid electrode of the MOS tube P5 is connected with the output end of the amplifier AMP1,inverting input terminal of amplifier AMP1 and reference voltageThe positive input end of the amplifier AMP1 is connected with the connecting end of one end of a resistor R3 and one end of a resistor R4, the other end of the resistor R3 is divided into three paths, the first path is connected with the drain electrode of a MOS tube P5, the second path is connected with one end of a capacitor C3, the other end of the capacitor C3 is grounded, and the third path is connected with a power supply>Connecting; the other end of the resistor R4 is grounded;
the non-inverting input end of the first comparator CMP1 is connected with the connecting end of one end of the resistor R1 and one end of the resistor R2, the other end of the resistor R1 is connected with the drain electrode of the MOS tube P6, the other end of the resistor R2 is grounded, and the inverting input end of the first comparator CMP1 is connected with the reference voltageThe output end of the first comparator CMP1 is connected with the second logic control circuit U4;
the second logic control circuit U4 is configured to output clock signals for controlling the first switch K11, the second switch K12, the third switch K21, and the fourth switch K22;
the nondestructive current detection module comprises a three-stage PMOS current mirror, a comparator CMPA, a comparator CMPB and a comparator CMPC, wherein the input end of the three-stage PMOS current mirror comprises an NMOS tube N7 and an MOS tube P1, the output branch of the three-stage PMOS current mirror comprises an MOS tube P2, an MOS tube P3 and an MOS tube P4 which are connected in parallel, and the non-inverting input end of the amplifier AMP2 is connected with a reference voltageConnected with the source of NMOS transistor N7 and resistor R and the inverting input of amplifier AMP2 sense The connecting end of one end of (a) is connected with the resistor R sense The other end of the NMOS tube N7 is grounded, the drain electrode of the NMOS tube N7 is divided into two paths, one path is connected with the drain electrode of the MOS tube P1, and the other path is connected with the grid electrode of the MOS tube P1, the grid electrode of the MOS tube P2, the grid electrode of the MOS tube P3 and the connecting end of the grid electrode of the MOS tube P4;
the drain electrode of the MOS tube P2 is divided into two paths, one path is connected with the inverting input end of the comparator CMPA, the second path is grounded through a resistor RSA, and the drain electrode of the MOS tube N2 is connected with the non-inverting input end of the comparator CMPA; the drain electrode of the MOS tube P3 is divided into two paths, one path is connected with the inverting input end of the comparator CMPB, the second path is grounded through a resistor RSB, and the drain electrode of the MOS tube N4 is connected with the non-inverting input end of the comparator CMPB; the drain electrode of the MOS tube P4 is divided into two paths, one path is connected with the inverting input end of the comparator CMPC, the second path is grounded through a resistor RSC, and the drain electrode of the MOS tube N6 is connected with the non-inverting input end of the comparator CMPC; the source electrode of the MOS tube P1, the source electrode of the MOS tube P2, the source electrode of the MOS tube P3 and the source electrode of the MOS tube P4 are connected with a power supply VCC;
the output end of the comparator CMPA, the output end of the comparator CMPB and the output end of the comparator CMPC are used as inputs of an OR gate logic circuit, and the output of the OR gate logic circuit is connected with the first logic control module U2;
the drain electrode of the MOS tube N2 is connected with the non-inverting input end of the comparator CMPA, the drain electrode of the MOS tube N4 is connected with the non-inverting input end of the comparator CMPB, and the drain electrode of the MOS tube N6 is connected with the non-inverting input end of the comparator CMPC respectively.
2. The wide voltage multimode BLDC driving integrated circuit of claim 1, wherein: the pre-driving module comprises an A-phase driving circuit, a B-phase driving circuit and a C-phase driving circuit which are identical in structure, wherein the A-phase driving circuit comprises a high-side driving unit and a low-side driving unit.
3. An application circuit of a wide voltage multimode BLDC driving integrated circuit is characterized in that: the driving integrated circuit U3 and the peripheral circuit comprise a battery power supply module, an MCU control chip and a three-phase full-bridge driving circuit, wherein the three-phase output end of the three-phase full-bridge driving circuit is connected with a brushless direct current motor, the driving integrated circuit U3 is integrated with a first logic control module U2, an LDO power supply module, a pre-driving module and a buck-boost circuit U1, the first logic control module U2 is connected with the MCU control chip, and the battery power supply module is connected with the LDO power supply module through a switch K.
4. An application circuit of a wide voltage multimode BLDC driving integrated circuit as set forth in claim 3, wherein: the peripheral circuit comprises a charge pump circuit, the charge pump circuit comprises a capacitor C5, and one end of the capacitor C5 is connected with a power supplyThe other end of the capacitor C5 is connected with the output of the step-up/step-down circuit U1 in two ways>The other path is connected with a high-voltage driving circuit of the pre-driving module.
5. An application circuit of a wide voltage multimode BLDC driving integrated circuit as set forth in claim 3, wherein: the three-phase full-bridge driving circuit comprises an upper bridge arm and a lower bridge arm, wherein the upper bridge arm comprises an MOS tube N1, an MOS tube N3 and an MOS tube N5, the lower bridge arm comprises an MOS tube N2, an MOS tube N4 and an MOS tube N6, the pre-driving module comprises an A-phase driving circuit, a B-phase driving circuit and a C-phase driving circuit which are identical in structure, the A-phase driving circuit comprises a high-side driving unit and a low-side driving unit, the high-side driving unit drives one power MOS tube in the upper bridge arm, and the low-side driving unit drives one power MOS tube in the lower bridge arm.
6. The power consumption control method of the wide-voltage multimode BLDC driving integrated circuit is characterized by comprising the following steps of: the power consumption control method is realized based on the driving integrated circuit U3 and the peripheral circuit according to claim 3, and comprises the steps of:
step one, powering up a battery power supply module,
judging whether an enabling pin of the LDO power supply module is at a high level, if so, starting the LDO power supply module, enabling other module circuits to be inoperative, and driving the integrated circuit U3 to enter an ultralow-power-consumption standby mode; if the voltage is low, driving the integrated circuit U3 to enter a zero power consumption standby mode;
step three, judging whether the first logic control module U2 receives the MCU control chipIf the instruction is received, the step-up and step-down circuit U1 is started, whenAnd +.>After the voltage is normal, driving the integrated circuit U3 to enter a normal working mode, and entering a step four; if the MCU instruction is not received, driving the integrated circuit U3 to enter an ultralow power consumption standby mode;
step four, starting timing, and driving the integrated circuit U3 to enter an ultralow-power-consumption standby mode when the timing duration exceeds a timing threshold value and the first logic control module U2 does not receive an instruction; and returning to the third step.
7. The method for controlling power consumption of a wide voltage multimode BLDC driving integrated circuit of claim 6, wherein: the timing threshold is 16ms.
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GB0104312D0 (en) * 1999-01-22 2001-04-11 Wood John Electronic circuitry
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