CN115242055B - Detection circuit and power supply circuit for DC-DC converter - Google Patents

Detection circuit and power supply circuit for DC-DC converter Download PDF

Info

Publication number
CN115242055B
CN115242055B CN202210814789.9A CN202210814789A CN115242055B CN 115242055 B CN115242055 B CN 115242055B CN 202210814789 A CN202210814789 A CN 202210814789A CN 115242055 B CN115242055 B CN 115242055B
Authority
CN
China
Prior art keywords
circuit
coupled
output
capacitor
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202210814789.9A
Other languages
Chinese (zh)
Other versions
CN115242055A (en
Inventor
张宝全
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SG Micro Beijing Co Ltd
Original Assignee
SG Micro Beijing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SG Micro Beijing Co Ltd filed Critical SG Micro Beijing Co Ltd
Priority to CN202210814789.9A priority Critical patent/CN115242055B/en
Publication of CN115242055A publication Critical patent/CN115242055A/en
Application granted granted Critical
Publication of CN115242055B publication Critical patent/CN115242055B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
    • G01R19/16533—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the application
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
    • G01R19/16566—Circuits and arrangements for comparing voltage or current with one or several thresholds and for indicating the result not covered by subgroups G01R19/16504, G01R19/16528, G01R19/16533
    • G01R19/16576—Circuits and arrangements for comparing voltage or current with one or several thresholds and for indicating the result not covered by subgroups G01R19/16504, G01R19/16528, G01R19/16533 comparing DC or AC voltage with one threshold
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0012—Control circuits using digital or numerical techniques
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The invention discloses a detection circuit and a power supply circuit for a DC-DC converter, wherein the power supply circuit is arranged in the DC-DC converter and comprises a detection circuit; the detection circuit comprises a single-side delay circuit, a reference voltage circuit, a capacitor voltage circuit, a comparison circuit, a first NOR gate, a timer, a logic circuit and a control circuit, wherein the output end of the timer is coupled with the control circuit and outputs a first trigger signal; the single-side delay circuit delays the rising edge of the modulation signal sent by the modulation signal end to output a single-side delay signal; the comparison circuit compares the reference voltage value output by the reference voltage circuit with the capacitor voltage value output by the capacitor voltage circuit, and inputs a comparison result to the first NOR gate; the first NOR gate inputs an indication signal to the logic circuit according to the comparison result and the unilateral delay signal; the logic circuit outputs a second trigger signal based on the indication signal; the control circuit outputs a trigger signal according to the first trigger signal and the second trigger signal, and controls the charge pump to be turned on and off.

Description

Detection circuit and power supply circuit for DC-DC converter
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a detection circuit and a power supply circuit for a DC-DC converter.
Background
Along with the expanding market of integrated circuits, direct current-to-direct current (DC-DC) converters are rapidly developed, and as a switching power supply technology, the DC-DC converters have the advantages of fast dynamic response, simple control and the like and have wide application. In order to ensure that the power tube in the DC-DC converter can work normally, a bootstrap capacitor (BST capacitor) is required to supply power to the driving part of the power tube, and in some lithium battery application environments, maximization of the service time of the BST capacitor is also expected, and the system can provide an operation mode of the power tube close to 100% duty cycle besides conventional application.
Because the conventional BST capacitor is charged in the period of time when the power tube is turned off, when the duty ratio is close to 100%, the BST capacitor is undervoltage due to insufficient power supplementing time of the BST capacitor, and in this case, a charge pump needs to be connected to supply power to the BST capacitor. However, when the charge pump in the related art supplies power to the BST capacitor, the on-resistance of the power tube is often increased, and the working efficiency of the circuit is reduced.
Disclosure of Invention
The invention mainly aims to provide a detection circuit and a power supply circuit for a DC-DC converter, which are used for solving the problems that in the prior art, a charge pump charges and supplements electricity for a BST capacitor to increase the conduction impedance of a power tube and reduce the working efficiency of the circuit.
In order to achieve the above object, a first aspect of the present invention provides a detection circuit for a DC-DC converter, the detection circuit being provided in the DC-DC converter and the detection circuit including: the circuit comprises a single-side delay circuit, a reference voltage circuit, a capacitor voltage circuit, a comparison circuit, a first NOR gate, a timer, a logic circuit and a control circuit, wherein:
the input end of the timer is coupled with the modulation signal end, the output end of the timer is coupled with the first input end of the control circuit, and the timer is configured to output a first trigger signal;
The single-side delay circuit is configured to delay the rising edge of a modulation signal sent by the modulation signal end, and output a single-side delay signal from the output end;
the first end of the reference voltage circuit is coupled with the fixed voltage end, the second end of the reference voltage circuit is coupled with the first input end of the comparison circuit, and the reference voltage circuit is configured to input a reference voltage value to the first input end of the comparison circuit;
The second end of the capacitor voltage circuit is coupled with the second input end of the comparison circuit, and the capacitor voltage circuit is configured to input a capacitor voltage value to the second input end of the comparison circuit;
The output end of the comparison circuit is coupled with the first input end of the first NOR gate, and the comparison circuit is configured to compare the reference voltage value and the capacitor voltage value and input a comparison result to the first input end of the first NOR gate;
The output end of the first NOR gate is coupled with the first input end of the logic circuit, and the first NOR gate is configured to input an indication signal to the first input end of the logic circuit according to the comparison result and the single-side delay signal;
The second input end of the logic circuit is coupled with the modulation signal end, the output end of the logic circuit is coupled with the second input end of the control circuit, and the logic circuit is configured to output a second trigger signal; and
The output end of the control circuit is coupled with the charge pump, and the control circuit is configured to output a trigger signal according to a first trigger signal and a second trigger signal and control the charge pump to switch between a first switch state and a second switch state, wherein the first switch state is that the charge pump is on, and the second switch state is that the charge pump is off.
Optionally, the comparing circuit comprises a comparator and a first inverter, wherein:
the non-inverting input end of the comparator is coupled with the second end of the reference voltage circuit, the inverting input end of the comparator is coupled with the second end of the capacitor voltage circuit, and the output end of the comparator is coupled with the first end of the first inverter;
the second end of the first inverter is coupled to the first input end of the first NOR gate.
Further, the third end of the reference voltage circuit is a grounding end;
the reference voltage circuit includes a first resistor and a second resistor, wherein:
the first end of the first resistor is coupled with the fixed voltage end, and the second end of the first resistor is coupled with the non-inverting input end of the comparator and the first end of the second resistor;
the second end of the second resistor is coupled to the ground.
Further, the third end of the capacitor voltage circuit is a grounding end;
the capacitive voltage circuit includes: a current source, a first capacitor, and a first transistor, wherein:
the current source is coupled with the first end of the first capacitor, the first pole of the first transistor and the inverting input end of the comparator;
The control electrode of the first transistor is coupled to the output end of the single-side delay circuit, and the second electrode of the first transistor and the second end of the first capacitor are respectively coupled to the grounding end.
Optionally, the timer is configured to output the first trigger signal according to a modulation signal sent by the modulation signal terminal when the on-time length of the first transistor is greater than the time length threshold, and the modulation signal includes a pulse width modulation signal.
Optionally, the capacitor voltage circuit includes a first transistor, a second end of the single-side delay circuit is coupled to a control electrode of the first transistor and a second input end of the first nor gate, a third end of the single-side delay circuit is coupled to a power supply end, and a fourth end of the single-side delay circuit is a ground end;
the single-side delay circuit includes a second inverter, a second transistor, a third resistor, and a second capacitor, wherein:
The first end of the second inverter is coupled with the modulation signal end, the second end of the second inverter is coupled with the control electrode of the second transistor after inverting, and the second end of the second inverter is coupled with the control electrode of the third transistor;
the first electrode of the second transistor is coupled with the common power supply end, and the second electrode of the second transistor is coupled with the first end of the third resistor;
the first pole of the third transistor is coupled to the second end of the third resistor and the first end of the second capacitor, and the second pole of the third transistor is coupled to the second end of the second capacitor and the ground.
Optionally, the logic circuit comprises: a nand gate, a third inverter, a reset circuit, and a flip-flop, wherein:
the first input end of the NAND gate is coupled with the output end of the first NOR gate, the second input end of the NAND gate is coupled with the modulating signal end, and the output end of the NAND gate is coupled with the first end of the third inverter;
The second end of the third inverter is coupled with the first input end of the touch generator;
The input end of the reset circuit is coupled with the modulation signal end, the output end of the reset circuit is coupled with the second input end of the trigger, and the reset circuit is configured to reset the second trigger signal to a low level according to the falling edge of the modulation signal sent by the modulation signal end;
The output end of the trigger is coupled with the second input end of the control circuit, and the trigger is configured to output a second trigger signal according to the control signal output by the second end of the third inverter and the reset signal output by the output end of the reset circuit.
Further, the reset circuit includes: a fourth transistor, a fourth resistor, a third capacitor, and a second nor gate, wherein:
The control electrode of the fourth transistor is coupled with the modulation signal end, the first electrode of the fourth transistor is coupled with the second end of the fourth resistor, the first end of the third capacitor and the first input end of the second NOR gate, and the second electrode of the fourth transistor is coupled with the second end of the third capacitor and the grounding end;
the first end of the fourth resistor is coupled with the common power end;
The second input end of the second nor gate is coupled to the modulation signal end, the output end of the second nor gate is coupled to the second input end of the trigger, and the second nor gate is configured to input a reset signal to the second input end of the trigger.
Further, the control circuit includes a third nor gate and a fourth inverter, wherein:
the first input end of the third nor gate is coupled with the output end of the timer, the second input end of the third nor gate is coupled with the output end of the touch generator, and the output end of the third nor gate is coupled with the first end of the fourth inverter;
the second end of the fourth inverter is coupled with the charge pump, and the fourth inverter outputs a trigger signal to control the switch of the charge pump.
A second aspect of the present invention provides a power supply circuit for a DC-DC converter, the power supply circuit being provided in the DC-DC converter, and the power supply circuit including the detection circuit for a DC-DC converter of any one of the first aspects, the power supply circuit further comprising: a first charging circuit, a second charging circuit, a fourth capacitor, a driving circuit, a fifth transistor, a first diode, an inductor, and an output circuit, wherein:
the first end of the first charging circuit is coupled with the input voltage end, and the second end of the first charging circuit is coupled with the second end of the second charging circuit, the first end of the fourth capacitor and the first end of the driving circuit;
The first end of the second charging circuit is coupled with the output end of the control circuit in the detection circuit, and the second charging circuit is configured to charge the fourth capacitor according to the trigger signal output by the control circuit;
the input end of the driving circuit is coupled with the modulation signal end, the output end of the driving circuit is coupled with the control electrode of the fifth transistor, and the driving circuit is configured to drive the fifth transistor according to the input modulation signal;
The first pole of the fifth transistor is coupled with the input voltage end, and the second pole of the fifth transistor is coupled with the second end of the fourth capacitor, the second end of the driving circuit, the second end of the first diode and the first end of the inductor;
the first end of the first diode is coupled with the grounding end;
the second end of the inductor is coupled with the output voltage end; and
The output circuit is configured to generate an output voltage signal from the inductor current flowing through the inductor.
Optionally, the first charging circuit includes: LDO module and second diode, wherein:
The first end of the LDO module is coupled with the input voltage end, and the second end of the LDO module is coupled with the first end of the second diode;
the second end of the second diode is coupled to the second end of the second charging circuit, the first end of the fourth capacitor and the first end of the driving circuit.
Optionally, the second charging circuit includes: a charge pump and a third diode, wherein:
The first end of the charge pump is coupled with the output end of the control circuit in the detection circuit, the second end of the charge pump is coupled with the first end of the third diode, the charge pump is configured to switch between a first switch state and a second switch state according to a trigger signal output by the control circuit, wherein the first switch state is that the charge pump is started, the fourth capacitor is charged through the third diode, and the second switch state is that the charge pump is stopped;
the second terminal of the third diode is coupled to the second terminal of the first charging circuit, the first terminal of the fourth capacitor, and the first terminal of the driving circuit.
Optionally, the output circuit includes: a fifth resistor, a sixth resistor, and a fifth capacitor, wherein:
The first end of the fifth resistor is coupled with the second end of the inductor, the first end of the sixth resistor and the output voltage end, and the second end of the third resistor is coupled with the ground end;
the second end of the sixth resistor is coupled with the first end of the fifth capacitor;
the second terminal of the fifth capacitor is coupled to the ground terminal.
In the detection circuit for a DC-DC converter provided by the embodiment of the present invention, the detection circuit is provided in the DC-DC converter and includes: the circuit comprises a single-side delay circuit, a reference voltage circuit, a capacitor voltage circuit, a comparison circuit, a first NOR gate, a timer, a logic circuit and a control circuit, wherein the input end of the timer is coupled with a modulation signal end, the output end of the timer is coupled with the first input end of the control circuit, and the timer is configured to output a first trigger signal; the single-side delay circuit is configured to delay the rising edge of a modulation signal sent by the modulation signal end, and output a single-side delay signal from the output end; the first end of the reference voltage circuit is coupled with the fixed voltage end, the second end of the reference voltage circuit is coupled with the first input end of the comparison circuit, and the reference voltage circuit is configured to input a reference voltage value to the first input end of the comparison circuit; the second end of the capacitor voltage circuit is coupled with the second input end of the comparison circuit, and the capacitor voltage circuit is configured to input a capacitor voltage value to the second input end of the comparison circuit; the output end of the comparison circuit is coupled with the first input end of the first NOR gate, and the comparison circuit is configured to compare the reference voltage value and the capacitor voltage value and input a comparison result to the first input end of the first NOR gate; detecting the reference voltage value and the capacitance voltage value through a comparison circuit, and detecting insufficient power supply when the capacitance voltage value is smaller than the reference voltage value, wherein a charge pump is required to be started for power supply at the moment;
The output end of the first NOR gate is coupled with the first input end of the logic circuit, and the first NOR gate is configured to input an indication signal to the first input end of the logic circuit according to the comparison result and the single-side delay signal; the second input end of the logic circuit is coupled with the modulation signal end, the output end of the logic circuit is coupled with the second input end of the control circuit, and the logic circuit is configured to output a second trigger signal; the output end of the control circuit is coupled with the charge pump, and the control circuit is configured to output a trigger signal according to a first trigger signal and a second trigger signal and control the charge pump to switch between a first switch state and a second switch state, wherein the first switch state is that the charge pump is on, and the second switch state is that the charge pump is off. The control circuit controls the charge pump to be turned on and off according to the first trigger signal and the second trigger signal, and when the power supply voltage is insufficient, the charge pump is controlled to be turned on to supply power to the capacitor, and higher voltage is provided, so that the conduction impedance of the power tube can be obviously reduced, the efficiency is improved, and the problems of increasing the conduction impedance of the power tube and reducing the working efficiency of the circuit when the charge pump charges and supplements electricity for the BST capacitor in the prior art are solved.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings which are required in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are only some embodiments of the invention and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a circuit diagram of a conventional power supply circuit for a DC-DC converter;
Fig. 2 is an exemplary block diagram of a detection circuit for a DC-DC converter provided by an embodiment of the present invention;
fig. 3 is an exemplary circuit diagram of a detection circuit for a DC-DC converter provided by an embodiment of the present invention;
Fig. 4 is an exemplary waveform diagram of a first trigger signal in a detection circuit according to an embodiment of the present invention;
FIG. 5 is an exemplary waveform diagram of a second trigger signal in a detection circuit according to an embodiment of the present invention;
fig. 6 is an exemplary circuit diagram of a power supply circuit for a DC-DC converter according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. It will be apparent that the described embodiments are some, but not all, embodiments of the invention. All other embodiments, which can be obtained by a person skilled in the art without creative efforts, based on the described embodiments of the present invention also fall within the protection scope of the present invention.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together either directly or joined through one or more intermediate parts.
In all embodiments of the present invention, since the source and drain (emitter and collector) of the transistor are symmetrical and the on-current direction between the source and drain (emitter and collector) of the N-type transistor and the P-type transistor is opposite, in embodiments of the present invention the controlled middle terminal of the transistor is referred to as the control pole and the remaining two terminals of the transistor are referred to as the first pole and the second pole, respectively. The transistors employed in the embodiments of the present invention are mainly switching transistors. In addition, terms such as "first" and "second" are used merely to distinguish one component (or portion of a component) from another component (or another portion of a component).
Fig. 1 shows an exemplary circuit diagram of a supply circuit for a DC-DC converter. The DC-DC converter can convert one direct current voltage into other direct current voltages, wherein PWM is a power tube starting signal adopting a pulse width modulation mode, the frequency of switching pulse is certain, and the output voltage is stable by changing the pulse output width; BST-UVLO is a charge pump signal which is output when the voltage of BST is lower than a reference value VREF; the LDO module is a low dropout linear voltage regulator, is a linear buck power management chip and is used for stably outputting a fixed voltage; charge_pump is a Charge pump for supplying power to BST capacitor Cbst under certain conditions; SBD is a Schottky diode; BST and SW represent two nodes in the circuit and corresponding voltage values respectively; vin is input voltage, vb is fixed voltage after Vin passes through the LDO module, vout is output voltage, cout is output capacitance, and Resr is equivalent series resistance.
In BUCK type DC-DC applications, when an NMOS fet is selected as the power transistor, a BST capacitor is required to power the high side driver_ Hside of its driving portion.
In some lithium battery applications, it is desirable to maximize the time of use, and it is desirable that the system be able to provide a 100% duty cycle or a mode of operation close to 100% duty cycle in addition to conventional applications. The system works close to 100% duty cycle, the BST capacitor Cbst has no charging time basically, but at 100% duty cycle, the BST capacitor Cbst loses the charging time completely, and as the on time is prolonged, if no power supply is provided, the 100% on state cannot be maintained, so that a charge pump is required to supply power to the BST capacitor, in this case, when the charge pump is connected in to supply power to the BST capacitor, so that a research direction of such scheme is provided.
In order to cope with the problem when the charge pump is powered, a UVLO of BST is set in the related art to detect the BST voltage, as shown in fig. 1, the UVLO comparator is a hysteresis comparator, the reference point is a reference voltage value vref±, the lower hysteresis limit is VREF-, and the upper hysteresis limit is vref+. If BST-SW < VREF-, the output BST_UVLO is high, which indicates that the BST capacitor Cbst is undervoltage, and the charge pump is started to work so as to charge the BST capacitor Cbst; if BST-SW > VREF+, then the output BST_UVLO goes low, indicating that the BST capacitance voltage difference meets the application requirements, and the charge pump stops working.
However, this solution has an important drawback: when the voltage difference of the BST capacitor is not reduced to UVLO, the charge pump is not operated, and even if the charge pump is operated, the charge pump cannot be stopped after the voltage difference of the BST capacitor is equal to the fixed voltage Vb. When the voltage difference of the BST capacitor is smaller than VREF-, the charge pump is started, and Vc supplements power for the BST capacitor Cbst; when Vc charges and supplements electricity for the BST capacitor Cbst to be more than VREF+, the charge pump is turned off, and the BST capacitor Cbst stops supplementing electricity for the BST capacitor, and after the BST capacitor Cbst supplies electricity for a period of time for the high-side power tube HS driving part, the voltage difference of the BST capacitor is reduced to be less than VREF-due to voltage consumption and leakage loss. Therefore, the voltage difference of the BST capacitor is always VREF+/-so that the Vgs voltage of the power tube is at the value of BST_UVLO, the self-conduction impedance of the power tube is directly increased, and the system efficiency is further reduced.
The embodiment of the invention provides a detection circuit and a power supply circuit for a DC-DC conversion circuit, wherein the power supply circuit comprises the detection circuit, an exemplary circuit diagram of the detection circuit is shown in fig. 3, and an exemplary circuit diagram of the power supply circuit is shown in fig. 6. The BST capacitor Cbst is powered by the power supply circuit to drive the high-side power tube HS, and in order to charge and supplement power for the BST capacitor Cbst when the voltage difference of the BST capacitor is reduced, the detection circuit BST-Test circuit is used for determining when to start the charge pump to charge the BST capacitor, so that the conduction impedance of the power tube is reduced, and the working efficiency of the circuit is improved.
In a continuous conduction mode (CCM mode), in one switching period, the current of the inductor is continuous, the current does not return to 0, and the inductor is never reset; the total BST capacitance charge problem in CCM mode is first calculated from the energy conservation point of view.
In the Toff period, sw=0, the bst capacitor is complemented by Vin through the output Vb of the LDO module, the complemented current average value is denoted as Ii, and the complemented charge amount is as follows: ii Toff;
In the Ton time period, the power tube is turned on, under the condition that the on-resistance of the power tube is ignored, sw=vin, the average value Io of the BST leakage current, the leaked electric charge amount is io×ton, the consumed electric charge amount when the grid electrode of the power tube is charged is Q tot＝Vgs*Ceq, wherein Q tot is the total electric charge amount required to be consumed for charging the grid electrode potential of the power tube from 0 to a target value Vgs; c eq＝Qtot/Vgs is the equivalent capacitance of the grid electrode in the charging process.
In the power supply circuit, the precondition for maintaining sufficient BST power supply is ii×toff > io×ton+q tot; conversely, as time passes, the charge of the BST capacitor will not go out and will be lost, so the charge pump needs to be turned on as long as the equation Ii < Toff < Io > ton+q tot is satisfied.
From the above formula, it can be seen that:
(1) When the power tube is turned on with 100% duty cycle, toff=0, so the charge pump must be turned on;
(2) When the power tube is not 100% duty cycle, the Ton term can be ignored because the Io/Ii value is very small, and the above formula can be adjusted as follows: ii is Toff < Qtot, wherein Q tot =Vgs is calculated by a simulation model, vgs takes a limit value Vb, and the value Vb is a fixed voltage output by the LDO module when the high voltage is applied, so that the voltage difference of the BST capacitor is determined, and the LDO module can be removed when the low voltage is applied, and at the moment, vb=vin. Thus, a scaling can be made defining a current source iia=ii/n, and an analog capacitance c1=c eq/m, which can be obtained: iia Toff/C1< Vb m/n, the charge pump is turned on under this condition, which ensures that the demand is met.
Circuit diagrams satisfying the charge pump on scheme in the foregoing (1) and (2) are discussed below.
Case a: for the scheme of starting the charge pump in the previous step (1), a timer can be adopted to realize, when the timer detects that the starting time Ton of the power tube exceeds a duration threshold, the charge pump is started to charge the BST capacitor, for example, the duration threshold can be set to be 10us or 20us according to the condition of an actual power supply circuit;
Case B: for the charge pump scheme (2), only a detection circuit bst_test satisfying the formula iia×toff/C1< vb×m/n is needed, and when the voltage value iia×toff/C1 at the two ends of the capacitor C1 is smaller than the reference voltage value vref=vb×m/n, the charge pump is turned on to charge the BST capacitor.
By combining the circuit satisfying the above case a and the circuit satisfying the above case B into the same detection circuit, a detection circuit detecting the charge pump on condition can be obtained, such as an exemplary block diagram and an exemplary circuit diagram of the detection circuit for a DC-DC converter provided by the embodiment of the present invention shown in fig. 2 and 3, wherein the detection circuit is provided in the DC-DC converter and the detection circuit bst_test includes: the circuit comprises a single-side delay circuit, a reference voltage circuit, a capacitor voltage circuit, a comparison circuit, a first NOR gate, a timer, a logic circuit and a control circuit, wherein:
The input end of the timer is coupled with the modulation signal end PWM, the output end of the timer is coupled with the first input end of the control circuit, and the timer is configured to output a first trigger signal Start1; when the counted time Ton of the power tube HS is larger than the time threshold Ta, the timer outputs a first trigger signal Start1 to the control circuit so that the control circuit controls the charge pump to be started.
The single-side delay circuit is configured to delay the rising edge of a modulation signal sent by the modulation signal end PWM, and output a single-side delay signal Kc from the output end;
The first end of the reference voltage circuit is coupled with the fixed voltage end Vb, the second end of the reference voltage circuit is coupled with the first input end of the comparison circuit, and the reference voltage circuit is configured to input a reference voltage value Vref to the first input end of the comparison circuit;
The second end of the capacitor voltage circuit is coupled with the second input end of the comparison circuit, and the capacitor voltage circuit is configured to input a capacitor voltage value to the second input end of the comparison circuit;
The output end of the comparison circuit is coupled with the first input end of the first NOR gate, and the comparison circuit is configured to compare the reference voltage value Vref and the capacitor voltage value and input a comparison result to the first input end of the first NOR gate;
The output end of the first NOR gate is coupled with the first input end of the logic circuit, and the first NOR gate is configured to input an indication signal Ka to the first input end of the logic circuit according to the comparison result and the unilateral delay signal Kc;
The second input end of the logic circuit is coupled with the modulation signal end PWM, the output end of the logic circuit is coupled with the second input end of the control circuit, and the logic circuit is configured to output a second trigger signal Start2; the logic circuit outputs a second trigger signal Start2 to the control circuit, and the control circuit controls the charge pump to be turned on and off.
The output end of the control circuit is coupled with the charge pump, and the control circuit is configured to output a trigger signal Start according to a first trigger signal Start1 and a second trigger signal Start2 and control the charge pump to switch between a first switch state and a second switch state, wherein the first switch state is that the charge pump is on, and the second switch state is that the charge pump is off. The control circuit outputs a trigger signal Start according to the first trigger signal Start1 or the second trigger signal Start2, controls the charge pump to be started and stopped, charges and supplements electricity for the BST capacitor Cbst when the charge pump is controlled to be started, and is in a non-working state when the charge pump is controlled to be stopped, and does not charge the BST capacitor Cbst.
In an alternative embodiment of the invention, the comparison circuit comprises a comparator COMP and a first inverter, wherein:
the non-inverting input end of the comparator COMP is coupled with the second end of the reference voltage circuit, the inverting input end of the comparator COMP is coupled with the second end of the capacitor voltage circuit, and the output end of the comparator COMP is coupled with the first end of the first inverter;
the second end of the first inverter is coupled to the first input end of the first NOR gate.
Further, the third terminal of the reference voltage circuit is a ground terminal GND; the reference voltage circuit comprises a first resistor R1 and a second resistor R2, wherein:
The first end of the first resistor R1 is coupled to the fixed voltage end Vb, and the second end of the first resistor R1 is coupled to the non-inverting input end of the comparator COMP and the first end of the second resistor R2;
the second terminal of the second resistor R2 is coupled to the ground GND.
Further, the third end of the capacitor voltage circuit is a ground end GND; the capacitive voltage circuit includes: a current source Iia, a first capacitor C1, and a first transistor Q, wherein:
the current source Iia is coupled to the first terminal of the first capacitor C1, the first pole of the first transistor Q and the inverting input terminal of the comparator COMP;
the control electrode of the first transistor Q is coupled to the output end of the single-side delay circuit, the second electrode of the first transistor Q and the second end of the first capacitor C1 are respectively coupled to the ground end GND, and the first transistor may be an N-type transistor.
In a preferred embodiment of the present invention, the timer is configured to output a first trigger signal Start1 to be at a high level according to a modulation signal sent by the modulation signal terminal PWM when the on-period Ton of the first transistor Q is greater than the period threshold Ta, to control the charge pump to be turned on, and to charge the BST capacitor, where; the modulated signal comprises a pulse width modulated signal.
In an alternative embodiment of the present invention, the capacitor voltage circuit includes a first transistor Q, a second end of the single-side delay circuit is coupled to a control electrode of the first transistor Q and a second input end of the first nor gate, a third end of the single-side delay circuit is coupled to a power supply end, and a fourth end of the single-side delay circuit is a ground end GND;
The single-side delay circuit includes a second inverter, a second transistor, a third resistor Ra, and a second capacitor Ca, wherein:
The first end of the second inverter is coupled with the modulation signal end PWM, the second end of the second inverter is coupled with the control electrode of the second transistor after inverting, and the second end of the second inverter is coupled with the control electrode of the third transistor; the second transistor is a P-type transistor, and the third transistor is an N-type transistor;
The first pole of the second transistor is coupled with the common power supply end, and the second pole of the second transistor is coupled with the first end of the third resistor Ra;
the first pole of the third transistor is coupled to the second terminal of the third resistor Ra and the first terminal of the second capacitor Ca, and the second pole of the third transistor is coupled to the second terminal of the second capacitor Ca and the ground GND.
The principle of operation of the single-sided delay circuit is described below in connection with the exemplary circuit diagram of the detection circuit of fig. 3.
When the PWM signal changes from high level to low level, the third transistor N is turned on, the second capacitor Ca is discharged, and the discharge time is short and negligible, so that the delay of the unilateral delay signal Kc on the falling edge of the PWM signal is negligible;
When the PWM signal changes from low level to high level, the second transistor P is turned on, the public power supply charges the second capacitor Ca, the charging time and the current are limited by the third resistor Ra, the single-side delay signal Kc is delayed at the rising edge of the PWM signal, and the specific time of delay is controlled by the third resistor Ra and the second capacitor Ca.
In an alternative embodiment of the invention, the logic circuit comprises: a nand gate, a third inverter, a reset circuit, and a flip-flop, wherein:
the first input end of the NAND gate is coupled with the output end of the first NOR gate, the second input end of the NAND gate is coupled with the PWM signal end, and the output end of the NAND gate is coupled with the first end of the third inverter;
The second end of the third inverter is coupled with the first input end of the touch generator;
the input end of the reset circuit is coupled with the modulation signal end PWM, the output end of the reset circuit is coupled with the second input end of the trigger, and the reset circuit is configured to reset the second trigger signal to a low level according to the falling edge of the modulation signal sent by the modulation signal end;
The output end of the trigger is coupled to the second input end of the control circuit, and the trigger is configured to output a second trigger signal Start2 according to the control signal Kb output by the second end of the third inverter and the reset signal reset output by the output end of the reset circuit. The flip-flop may be an RS flip-flop.
Further, the reset circuit includes: a fourth transistor, a fourth resistor Rb, a third capacitor Cb, and a second nor gate, wherein:
The control electrode of the fourth transistor is coupled to the modulation signal terminal PWM, the first electrode of the fourth transistor is coupled to the second end of the fourth resistor Rb, the first end of the third capacitor Cb and the first input end of the second nor gate, and the second electrode of the fourth transistor is coupled to the second end of the third capacitor Cb and the ground GND;
A first end of the fourth resistor Rb is coupled to the common power source end;
the second input end of the second nor gate is coupled to the modulation signal end PWM, the output end of the second nor gate is coupled to the second input end of the flip-flop, and the second nor gate is configured to input the reset signal reset to the second input end of the flip-flop.
The operation principle of the reset circuit is described below in connection with an exemplary circuit diagram of the detection circuit in fig. 3.
When the PWM signal is kept at a high level or a low level, the reset signal reset is kept at a low level; when the PWM signal changes from high level to low level, the plate voltage on the third capacitor Cb is pulled down for a short time, the reset signal reset is set to high level, and the second trigger signal Start2 output by the RS trigger is reset to low level; the time during which the reset signal reset is maintained at the high level, that is, the time during which the upper plate of the third capacitor Cb is low, is controlled by the fourth resistor Rb and the third capacitor Cb.
Further, the control circuit includes a third nor gate and a fourth inverter, wherein:
the first input end of the third nor gate is coupled with the output end of the timer, the second input end of the third nor gate is coupled with the output end of the touch generator, and the output end of the third nor gate is coupled with the first end of the fourth inverter;
the second end of the fourth inverter is coupled with the charge pump, and the fourth inverter outputs a trigger signal Start to control the switch of the charge pump.
The working principle of the detection circuit is set forth below in connection with an exemplary circuit diagram of the detection circuit for a DC-DC converter shown in fig. 3.
For the situation A, detecting the power tube opening time Ton, namely detecting the time when the PWM signal is high, when the PWM signal exceeds the time duration threshold Ta of the timer, the output of the first trigger signal Start1 becomes high, controlling the trigger signal Start to become high, and starting the charge pump; when the power tube is closed, namely PWM=0, the first trigger signal Start1 is recovered to be low, and the charge pump is turned off; an exemplary waveform diagram of the first trigger signal Start1 when the PWM signal appears at a sustained high level exceeding the duration threshold Ta is shown in fig. 4.
For the foregoing case B, in the Toff period, that is, in the pwm=0 period, the current source Iia charges the C1 capacitor, kc is a single-side delay signal of the PWM signal, and when the PWM signal is changed from the high level to the low level, kc is not delayed and is synchronous with PWM; when PWM goes from low to high, kc has a small delay, later than the PWM signal changes.
If the C1 capacitor voltage is higher than Vref (vref=vb×m/n) in the Toff period, that is, if Ka goes low before the PWM signal goes high, the output Kb signal is constant low, and in this state, the RS flip-flop outputs the second trigger signal Start2 low, that is, does not turn on the charge pump;
If the C1 capacitor voltage is lower than Vref (vref=vb×m/n) during the Toff period, the output Kb signal turns high if Ka fails to turn low before the PWM signal goes high, in which state the trigger output Start2 is high, i.e. the charge pump is turned on; when the PWM is low again, the output of the second trigger signal Start2 is reset to be low, the charge pump is turned off, and the judgment is carried out again.
Fig. 5 shows an exemplary waveform diagram of a second trigger signal Start2 in a detection circuit provided by the embodiment of the present invention, where the waveform diagram includes a PWM signal, a Kc signal, a Ka signal, a Kb signal, and a Start2 signal, where the Kc signal is a single-side delay signal of the PWM signal, and there is a small delay in the Kc signal and the PWM signal perform an and operation on a rising edge of the PWM signal, so that the Kb signal can be obtained;
When the Toff time is longer, the Kb signal is constant low because the Ka signal and the PWM signal do not have the same high level time, the second trigger signal Start2 output by the RS trigger is low, and the charge pump is not started;
When the Toff time is short, the rising edge of the Kb signal from low to high controls the second trigger signal Start2 to be high level, the charge pump is started, the falling edge of the PWM from high to low resets the second trigger signal Start2, the rising edge of the PWM from high to low changes the second trigger signal Start2 to be low level, and the charge pump is closed; on the next rising edge of the Kb signal, the second trigger signal Start2 goes high, turning on the charge pump.
The detection circuit controls the charge pump to be started, so that the Vgs is maximized when the power tube is started, compared with the traditional solution, the detection circuit is obviously larger than the BST_UVLO in the traditional solution, the on-resistance of the power tube can be obviously reduced, and the working efficiency of the circuit is improved.
Fig. 6 shows an exemplary circuit diagram of a power supply circuit for a DC-DC converter, the power supply circuit being provided in the DC-DC converter and including the detection circuit BST-Test circuit shown in fig. 3, the power supply circuit further including: the first charging circuit, the second charging circuit, the fourth capacitor Cbst, the driving circuit driver_ Hside, the fifth transistor HS, the first diode SBD, the inductor L, and the output circuit, the fifth transistor HS may be an N-type transistor, a high-side power transistor, where:
The first end of the first charging circuit is coupled to the input voltage end Vin, and the second end of the first charging circuit is coupled to the second end of the second charging circuit, the first end of the fourth capacitor Cbst and the first end of the driving circuit driver_ Hside;
The first end of the second charging circuit is coupled with the output end of the control circuit in the detection circuit, and the second charging circuit is configured to charge the fourth capacitor Cbst according to the trigger signal Start output by the control circuit; the fourth capacitor Cbst may be a bootstrap capacitor; the charge pump is started according to the trigger signal Start output by the control circuit in the detection circuit, the charge pump charges and supplements electricity for the fourth capacitor Cbst, and then the fourth capacitor Cbst supplies electricity for the driving circuit of the power tube, so that the Vgs is maximized when the power tube is started, compared with the traditional solution, the conduction impedance of the power tube can be obviously reduced, and the working efficiency of the circuit is improved.
The input end of the driving circuit driver_ Hside is coupled to the modulation signal end PWM, the output end of the driving circuit driver_ Hside is coupled to the control electrode of the fifth transistor HS, and the driving circuit driver_ Hside is configured to drive the fifth transistor HS according to the input modulation signal; the modulation signal of the modulation signal terminal PWM comprises a pulse width modulation signal.
The first pole of the fifth transistor HS is coupled to the input voltage terminal Vin, and the second pole of the fifth transistor HS is coupled to the second terminal of the fourth capacitor Cbst, the second terminal of the driving circuit driver_ Hside, the second terminal of the first diode SBD, and the first terminal of the inductor L;
the first end of the first diode SBD is coupled with the ground end GND; the first diode SBD may be a schottky diode SBD;
The second end of the inductor L is coupled with the output voltage end Vout;
The output circuit is configured to generate an output voltage signal from the inductor current flowing through the inductor L.
In an alternative embodiment of the present invention, the first charging circuit includes: LDO module and second diode, wherein:
The first end of the LDO module is coupled with the input voltage end Vin, and the second end of the LDO module is coupled with the first end of the second diode; after the input voltage Vin passes through the LDO module, a fixed voltage Vb can be output, and the second diode can be a Schottky diode SBD;
The second end of the second diode is coupled to the second end of the second charging circuit, the first end of the fourth capacitor Cbst, and the first end of the driving circuit driver_ Hside.
In an alternative embodiment of the present invention, the second charging circuit includes: charge pump charge_pump and a third diode, wherein:
The first end of the charge pump is coupled with the output end of the control circuit in the detection circuit, the second end of the charge pump is coupled with the first end of the third diode, the charge pump is configured to switch between a first switch state and a second switch state according to a trigger signal Start output by the control circuit, wherein the first switch state is that the charge pump is started, the fourth capacitor Cbst is charged through the third diode, and the second switch state is that the charge pump is stopped; when the charge pump is started, the output voltage is Vc, the BST capacitor is charged through the third diode, the voltage difference of the BST capacitor is large, vgs is ensured to be maximized when the power tube is started, the conduction impedance of the power tube is reduced, and the working efficiency of the circuit is improved.
The second terminal of the third diode is coupled to the second terminal of the first charging circuit, the first terminal of the fourth capacitor Cbst, and the first terminal of the driving circuit driver_ Hside.
In an alternative embodiment of the present invention, the output circuit includes: a fifth resistor R L, a sixth resistor Resr, and a fifth capacitor Cout, wherein:
the first end of the fifth resistor R L is coupled to the second end of the inductor L, the first end of the sixth resistor Resr, and the output voltage terminal Vout, and the second end of the fifth resistor R L is coupled to the ground terminal GND;
A second terminal of the sixth resistor Resr is coupled to a first terminal of the fifth capacitor Cout;
the second terminal of the fifth capacitor Cout is coupled to the ground GND.
From the above description, it can be seen that the following technical effects are achieved:
the voltage of the capacitor is detected by the comparator, so that the under-voltage of the BST capacitor can be timely detected when the voltage of the capacitor is smaller than the reference voltage, and preparation is made for charging the BST capacitor by starting the charge pump subsequently;
The control circuit controls the charge pump to be started and closed according to the first trigger signal and the second trigger signal, when the power supply voltage is insufficient, the charge pump is controlled to be started to supply power to the capacitor, and higher voltage is provided, so that the on-resistance of the power tube can be obviously reduced, the efficiency is improved, and the problems that the on-resistance of the power tube is increased and the working efficiency of the circuit is reduced when the charge pump charges and supplements electricity for the BST capacitor in the prior art are solved;
The charge pump is started after the detection circuit provided by the invention is judged, so that the voltage Vgs is ensured to be maximized when the power tube is started, and compared with the traditional solution, the on-resistance of the power tube can be obviously reduced, and the efficiency is improved.
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus and methods according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
As used herein and in the appended claims, the singular forms of words include the plural and vice versa, unless the context clearly dictates otherwise. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the terms "comprising" and "including" are to be construed as being inclusive rather than exclusive. Likewise, the terms "comprising" and "or" should be interpreted as inclusive, unless such an interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it follows a set of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or broad.
Further aspects and scope will become apparent from the description provided herein. It is to be understood that various aspects of the application may be implemented alone or in combination with one or more other aspects. It should also be understood that the description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure.
Although embodiments of the present invention have been described in connection with the accompanying drawings, various modifications and variations may be made by those skilled in the art without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope of the invention as defined by the appended claims.

Claims (10)

1. A detection circuit for a DC-DC converter, characterized in that the detection circuit is provided in the DC-DC converter and the detection circuit comprises: the circuit comprises a single-side delay circuit, a reference voltage circuit, a capacitor voltage circuit, a comparison circuit, a first NOR gate, a timer, a logic circuit and a control circuit, wherein:
The input end of the timer is coupled with the modulation signal end, the output end of the timer is coupled with the first input end of the control circuit, and the timer is configured to output a first trigger signal;
the first end of the single-side delay circuit is coupled with the modulation signal end, the second end of the single-side delay circuit is coupled with the first end of the capacitor voltage circuit and the second input end of the first NOR gate, and the single-side delay circuit is configured to delay the rising edge of a modulation signal sent by the modulation signal end and output a single-side delay signal from the output end;
The first end of the reference voltage circuit is coupled with the fixed voltage end, the second end of the reference voltage circuit is coupled with the first input end of the comparison circuit, and the reference voltage circuit is configured to input a reference voltage value to the first input end of the comparison circuit;
a second terminal of the capacitor voltage circuit is coupled to a second input terminal of the comparison circuit, and the capacitor voltage circuit is configured to input a capacitor voltage value to the second input terminal of the comparison circuit;
The output end of the comparison circuit is coupled with the first input end of the first NOR gate, and the comparison circuit is configured to compare the reference voltage value and the capacitance voltage value and input a comparison result to the first input end of the first NOR gate;
the output end of the first NOR gate is coupled with the first input end of the logic circuit, and the first NOR gate is configured to input an indication signal to the first input end of the logic circuit according to the comparison result and the single-side delay signal;
The second input end of the logic circuit is coupled with the modulation signal end, the output end of the logic circuit is coupled with the second input end of the control circuit, and the logic circuit is configured to output a second trigger signal; and
The output end of the control circuit is coupled with the charge pump, and the control circuit is configured to output a trigger signal according to the first trigger signal and the second trigger signal, so as to control the charge pump to switch between a first switch state and a second switch state, wherein the first switch state is that the charge pump is on, and the second switch state is that the charge pump is off.
2. The detection circuit of claim 1, wherein the comparison circuit comprises a comparator and a first inverter, wherein:
The non-inverting input end of the comparator is coupled with the second end of the reference voltage circuit, the inverting input end of the comparator is coupled with the second end of the capacitor voltage circuit, and the output end of the comparator is coupled with the first end of the first inverter;
The second end of the first inverter is coupled to the first input end of the first NOR gate.
3. The detection circuit of claim 2, wherein the third terminal of the reference voltage circuit is a ground terminal;
the reference voltage circuit includes a first resistor and a second resistor, wherein:
the first end of the first resistor is coupled with a fixed voltage end, and the second end of the first resistor is coupled with the non-inverting input end of the comparator and the first end of the second resistor;
The second end of the second resistor is coupled to the ground.
4. The detection circuit of claim 2, wherein the third terminal of the capacitor voltage circuit is a ground terminal;
The capacitive voltage circuit includes: a current source, a first capacitor, and a first transistor, wherein:
the current source is coupled to the first end of the first capacitor, the first pole of the first transistor, and the inverting input of the comparator;
the control electrode of the first transistor is coupled to the output end of the single-side delay circuit, and the second electrode of the first transistor and the second end of the first capacitor are respectively coupled to the ground end.
5. The detection circuit of claim 1, wherein the timer is configured to output the first trigger signal based on a modulation signal from the modulation signal terminal when the on-time length of the first transistor is greater than a time length threshold, the modulation signal comprising a pulse width modulation signal.
6. The detection circuit of claim 1, wherein the capacitor voltage circuit comprises a first transistor, a second terminal of the single-side delay circuit is coupled to a control electrode of the first transistor and a second input terminal of the first nor gate, a third terminal of the single-side delay circuit is coupled to a power supply terminal, and a fourth terminal of the single-side delay circuit is a ground terminal;
the single-side delay circuit includes a second inverter, a second transistor, a third resistor, and a second capacitor, wherein:
The first end of the second inverter is coupled with the modulation signal end, the second end of the second inverter is coupled with the control electrode of the second transistor after being inverted, and the second end of the second inverter is coupled with the control electrode of the third transistor;
a first pole of the second transistor is coupled to a common power supply terminal, and a second pole of the second transistor is coupled to a first terminal of the third resistor;
The first pole of the third transistor is coupled to the second end of the third resistor and the first end of the second capacitor, and the second pole of the third transistor is coupled to the second end of the second capacitor and the ground.
7. The detection circuit of claim 1, wherein the logic circuit comprises: a nand gate, a third inverter, a reset circuit, and a flip-flop, wherein:
The first input end of the NAND gate is coupled with the output end of the first NAND gate, the second input end of the NAND gate is coupled with the modulation signal end, and the output end of the NAND gate is coupled with the first end of the third inverter;
The second end of the third inverter is coupled with the first input end of the trigger;
The input end of the reset circuit is coupled with the modulation signal end, the output end of the reset circuit is coupled with the second input end of the trigger, and the reset circuit is configured to reset the second trigger signal to a low level according to the falling edge of the modulation signal sent by the modulation signal end;
The output end of the trigger is coupled with the second input end of the control circuit, and the trigger is configured to output a second trigger signal according to the control signal output by the second end of the third inverter and the reset signal output by the output end of the reset circuit.
8. The detection circuit of claim 7, wherein the reset circuit comprises: a fourth transistor, a fourth resistor, a third capacitor, and a second nor gate, wherein:
The control electrode of the fourth transistor is coupled to the modulation signal end, the first electrode of the fourth transistor is coupled to the second end of the fourth resistor, the first end of the third capacitor and the first input end of the second NOR gate, and the second electrode of the fourth transistor is coupled to the second end of the third capacitor and the ground end;
the first end of the fourth resistor is coupled with a common power supply end;
The second input end of the second nor gate is coupled to the modulation signal end, the output end of the second nor gate is coupled to the second input end of the trigger, and the second nor gate is configured to input a reset signal to the second input end of the trigger.
9. The detection circuit of claim 7, wherein the control circuit comprises a third nor gate and a fourth inverter, wherein:
the first input end of the third nor gate is coupled to the output end of the timer, the second input end of the third nor gate is coupled to the output end of the trigger, and the output end of the third nor gate is coupled to the first end of the fourth inverter;
the second end of the fourth inverter is coupled with a charge pump, and the fourth inverter outputs a trigger signal to control the switch of the charge pump.
10. A power supply circuit for a DC-DC converter, characterized in that the power supply circuit is provided in the DC-DC converter, and the power supply circuit comprises the detection circuit for a DC-DC converter according to any one of claims 1 to 9, the power supply circuit further comprising: a first charging circuit, a second charging circuit, a fourth capacitor, a driving circuit, a fifth transistor, a first diode, an inductor, and an output circuit, wherein:
the first end of the first charging circuit is coupled with an input voltage end, and the second end of the first charging circuit is coupled with the second end of the second charging circuit, the first end of the fourth capacitor and the first end of the driving circuit;
The first end of the second charging circuit is coupled with the output end of the control circuit in the detection circuit, and the second charging circuit is configured to charge the fourth capacitor according to the trigger signal output by the control circuit;
an input end of the driving circuit is coupled with a modulation signal end, an output end of the driving circuit is coupled with a control electrode of the fifth transistor, and the driving circuit is configured to drive the fifth transistor according to an input modulation signal;
A first pole of the fifth transistor is coupled to the input voltage terminal, and a second pole of the fifth transistor is coupled to the second terminal of the fourth capacitor, the second terminal of the driving circuit, the second terminal of the first diode, and the first terminal of the inductor;
the first end of the first diode is coupled with the grounding end;
the second end of the inductor is coupled with the output voltage end; and
The output circuit is configured to generate an output voltage signal from an inductor current flowing through the inductor.
CN202210814789.9A 2022-07-11 2022-07-11 Detection circuit and power supply circuit for DC-DC converter Active CN115242055B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210814789.9A CN115242055B (en) 2022-07-11 2022-07-11 Detection circuit and power supply circuit for DC-DC converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210814789.9A CN115242055B (en) 2022-07-11 2022-07-11 Detection circuit and power supply circuit for DC-DC converter

Publications (2)

Publication Number Publication Date
CN115242055A CN115242055A (en) 2022-10-25
CN115242055B true CN115242055B (en) 2024-05-14

Family

ID=83672525

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210814789.9A Active CN115242055B (en) 2022-07-11 2022-07-11 Detection circuit and power supply circuit for DC-DC converter

Country Status (1)

Country Link
CN (1) CN115242055B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117674807B (en) * 2023-12-12 2024-05-14 上海高晶检测科技股份有限公司 Control circuit system of rejection mechanism and metal detector

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105245103A (en) * 2014-07-01 2016-01-13 德克萨斯仪器股份有限公司 DC to DC converter and pwm controller with adaptive compensation circuit
CN205105092U (en) * 2014-11-19 2016-03-23 成都芯源系统有限公司 Constant on-time controlled switching converter and controller thereof
CN109905813A (en) * 2019-04-10 2019-06-18 启攀微电子（上海）有限公司 Adaptive puppet closed loop charge pump circuit

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI261406B (en) * 2004-07-08 2006-09-01 Analog Integrations Corp Charge pump DC/DC converter with constant-frequency operation
US10720840B2 (en) * 2017-12-22 2020-07-21 Stmicroelectronics S.R.L. DC-DC converter circuit with synchronization module and corresponding conversion method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105245103A (en) * 2014-07-01 2016-01-13 德克萨斯仪器股份有限公司 DC to DC converter and pwm controller with adaptive compensation circuit
CN205105092U (en) * 2014-11-19 2016-03-23 成都芯源系统有限公司 Constant on-time controlled switching converter and controller thereof
CN109905813A (en) * 2019-04-10 2019-06-18 启攀微电子（上海）有限公司 Adaptive puppet closed loop charge pump circuit

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
DC-DC电荷泵的研究与设计;曹香凝, 汪东旭, 严利民;通信电源技术;20041025(05);全文 *

Also Published As

Publication number Publication date
CN115242055A (en) 2022-10-25

Similar Documents

Publication Publication Date Title
US11011991B1 (en) Regulation loop circuit
US9484758B2 (en) Hybrid bootstrap capacitor refresh technique for charger/converter
US10763748B2 (en) Buck-boost DC-DC converter
CN100403636C (en) Pulse frequency mode DC-DC converter circuit
US8000117B2 (en) Buck boost function based on a capacitor bootstrap input buck converter
JP5211959B2 (en) DC-DC converter
US9729061B2 (en) Boost regulator having adaptive dead time
US9698677B2 (en) Brownout recovery circuit for bootstrap capacitor and switch power supply circuit
CN102299626A (en) Method and device for converting direct current into direct current
US7932709B1 (en) Stable high efficiency step-up voltage regulator with fast transient response and ultra low output voltage ripple
US10693376B2 (en) Electronic converter and method of operating an electronic converter
CN202918193U (en) Bootstrap voltage refresh control circuit and voltage conversion circuit
JP2008022642A (en) Dc-dc converter
GB2441926A (en) DC/DC converter
CN103248221A (en) Voltage reduction converter
CN113497559B (en) Converter circuit, corresponding device and method
US11152861B2 (en) Multiphase converter design with multi-path phase management
CN115242055B (en) Detection circuit and power supply circuit for DC-DC converter
JP2006014559A (en) Dc/dc converter
CN112532021B (en) Input parallel output series multi-converter switching power supply
CN115242054B (en) Power supply circuit for DC-DC converter
CN114257066A (en) Switch converter and control circuit thereof
CN115032473A (en) Switch converter and light load mode detection circuit and method thereof
CN112436488A (en) Under-voltage protection circuit of DC-DC bootstrap power supply
CN114977785B (en) Device for controlling charge pump in DC-DC chip

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant