CN115242055A - Detection circuit and power supply circuit for DC-DC converter - Google Patents

Detection circuit and power supply circuit for DC-DC converter Download PDF

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Publication number
CN115242055A
CN115242055A CN202210814789.9A CN202210814789A CN115242055A CN 115242055 A CN115242055 A CN 115242055A CN 202210814789 A CN202210814789 A CN 202210814789A CN 115242055 A CN115242055 A CN 115242055A
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circuit
coupled
terminal
output
input
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CN115242055B (en
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张宝全
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SG Micro Beijing Co Ltd
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SG Micro Beijing Co Ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
    • G01R19/16533—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the application
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
    • G01R19/16566—Circuits and arrangements for comparing voltage or current with one or several thresholds and for indicating the result not covered by subgroups G01R19/16504, G01R19/16528, G01R19/16533
    • G01R19/16576—Circuits and arrangements for comparing voltage or current with one or several thresholds and for indicating the result not covered by subgroups G01R19/16504, G01R19/16528, G01R19/16533 comparing DC or AC voltage with one threshold
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0012—Control circuits using digital or numerical techniques
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The invention discloses a detection circuit and a power supply circuit for a DC-DC converter, wherein the power supply circuit is arranged in the DC-DC converter and comprises the detection circuit; the detection circuit comprises a single-side delay circuit, a reference voltage circuit, a capacitor voltage circuit, a comparison circuit, a first NOR gate, a timer, a logic circuit and a control circuit, wherein the output end of the timer is coupled with the control circuit and outputs a first trigger signal; the single-side delay circuit delays the rising edge of the modulation signal sent by the modulation signal end and outputs a single-side delay signal; the comparison circuit compares a reference voltage value output by the reference voltage circuit with a capacitance voltage value output by the capacitance voltage circuit, and inputs a comparison result to the first NOR gate; the first NOR gate inputs an indication signal to the logic circuit according to the comparison result and the single-side delay signal; the logic circuit outputs a second trigger signal based on the indication signal; the control circuit outputs a trigger signal according to the first trigger signal and the second trigger signal to control the charge pump to be turned on and off.

Description

Detection circuit and power supply circuit for DC-DC converter
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a detection circuit and a power supply circuit for a DC-DC converter.
Background
With the increasing expansion of the integrated circuit market, a direct current-to-direct current (DC-DC) converter is also rapidly developed, and as a switching power supply technology, the DC-DC converter has the advantages of fast dynamic response, simple control and the like, and has wide application. In order to ensure that a power tube in a DC-DC converter can work normally, a bootstrap capacitor (BST capacitor) is required to be used to supply power to a driving part of the power tube, and in some lithium battery application environments, it is also expected that the service time of the BST capacitor is maximized, and the system can provide a working mode that the duty ratio of the power tube is close to 100% besides conventional application.
Because the conventional BST capacitor is charged in the time period when the power tube is closed, when the duty ratio is close to 100%, the BST capacitor is under-voltage due to insufficient power supplementing time of the BST capacitor, and under the condition, a charge pump needs to be connected to supply power to the BST capacitor. However, when the charge pump in the related art supplies power to the BST capacitor, the on-resistance of the power transistor is often increased, which reduces the operating efficiency of the circuit.
Disclosure of Invention
The invention mainly aims to provide a detection circuit and a power supply circuit for a DC-DC converter, and aims to solve the problems that in the prior art, a charge pump charges and supplements a BST capacitor, the on-resistance of a power tube is increased, and the working efficiency of the circuit is reduced.
In order to achieve the above object, a first aspect of the present invention provides a detection circuit for a DC-DC converter, the detection circuit being provided in the DC-DC converter and the detection circuit including: unilateral time delay circuit, reference voltage circuit, electric capacity voltage circuit, comparison circuit, first NOR gate, timer, logic circuit and control circuit, wherein:
the input end of the timer is coupled with the modulation signal end, the output end of the timer is coupled with the first input end of the control circuit, and the timer is configured to output a first trigger signal;
the first end of the single-side delay circuit is coupled with the modulation signal end, the second end of the single-side delay circuit is coupled with the first end of the capacitor voltage circuit and the second input end of the first NOR gate, and the single-side delay circuit is configured to delay the rising edge of the modulation signal sent by the modulation signal end and output a single-side delay signal from the output end;
the first end of the reference voltage circuit is coupled with the fixed voltage end, the second end of the reference voltage circuit is coupled with the first input end of the comparison circuit, and the reference voltage circuit is configured to input a reference voltage value to the first input end of the comparison circuit;
a second terminal of the capacitance-voltage circuit is coupled to the second input terminal of the comparison circuit, and the capacitance-voltage circuit is configured to input a capacitance-voltage value to the second input terminal of the comparison circuit;
the output end of the comparison circuit is coupled with the first input end of the first NOR gate, the comparison circuit is configured to compare the reference voltage value with the capacitor voltage value, and the comparison result is input into the first input end of the first NOR gate;
the output end of the first NOR gate is coupled with the first input end of the logic circuit, and the first NOR gate is configured to input an indicating signal to the first input end of the logic circuit according to the comparison result and the single-side delay signal;
the second input end of the logic circuit is coupled with the modulation signal end, the output end of the logic circuit is coupled with the second input end of the control circuit, and the logic circuit is configured to output a second trigger signal; and
the output end of the control circuit is coupled with the charge pump, the control circuit is configured to output a trigger signal according to a first trigger signal and a second trigger signal, and the charge pump is controlled to switch between a first switch state and a second switch state, wherein the first switch state is that the charge pump is turned on, and the second switch state is that the charge pump is turned off.
Optionally, the comparison circuit comprises a comparator and a first inverter, wherein:
the non-inverting input end of the comparator is coupled with the second end of the reference voltage circuit, the inverting input end of the comparator is coupled with the second end of the capacitance voltage circuit, and the output end of the comparator is coupled with the first end of the first phase inverter;
the second terminal of the first inverter is coupled to the first input terminal of the first nor gate.
Furthermore, the third terminal of the reference voltage circuit is a ground terminal;
the reference voltage circuit includes a first resistor and a second resistor, wherein:
the first end of the first resistor is coupled with the fixed voltage end, and the second end of the first resistor is coupled with the non-inverting input end of the comparator and the first end of the second resistor;
the second end of the second resistor is coupled to the ground terminal.
Furthermore, the third end of the capacitor voltage circuit is a grounding end;
the capacitance-voltage circuit includes: a current source, a first capacitor, and a first transistor, wherein:
the current source is coupled with the first end of the first capacitor, the first pole of the first transistor and the inverting input end of the comparator;
the control electrode of the first transistor is coupled to the output end of the single-side delay circuit, and the second electrode of the first transistor and the second end of the first capacitor are respectively coupled to the grounding end.
Optionally, the timer is configured to output the first trigger signal according to a modulation signal sent by a modulation signal terminal when the on-duration of the first transistor is greater than a duration threshold, where the modulation signal includes a pulse width modulation signal.
Optionally, the capacitor voltage circuit includes a first transistor, a second terminal of the single-side delay circuit is coupled to a control electrode of the first transistor and a second input terminal of the first nor gate, a third terminal of the single-side delay circuit is coupled to a power supply terminal, and a fourth terminal of the single-side delay circuit is a ground terminal;
the single-side delay circuit comprises a second inverter, a second transistor, a third resistor and a second capacitor, wherein:
the first end of the second inverter is coupled with the modulation signal end, the second end of the second inverter is coupled with the control electrode of the second transistor after being inverted, and the second end of the second inverter is coupled with the control electrode of the third transistor;
a first pole of the second transistor is coupled with a common power supply end, and a second pole of the second transistor is coupled with a first end of the third resistor;
a first pole of the third transistor is coupled to the second terminal of the third resistor and the first terminal of the second capacitor, and a second pole of the third transistor is coupled to the second terminal of the second capacitor and the ground terminal.
Optionally, the logic circuit comprises: NAND gate, third inverter, reset circuit, and flip-flop, wherein:
the first input end of the NAND gate is coupled with the output end of the first NOR gate, the second input end of the NAND gate is coupled with the modulation signal end, and the output end of the NAND gate is coupled with the first end of the third inverter;
the second end of the third inverter is coupled to the first input end of the flip-flop;
the input end of the reset circuit is coupled with the modulation signal end, the output end of the reset circuit is coupled with the second input end of the trigger, and the reset circuit is configured to reset the second trigger signal to a low level according to the falling edge of the modulation signal sent by the modulation signal end;
the output end of the flip-flop is coupled to the second input end of the control circuit, and the flip-flop is configured to output a second trigger signal according to the control signal output by the second end of the third inverter and the reset signal output by the output end of the reset circuit.
Further, the reset circuit includes: a fourth transistor, a fourth resistor, a third capacitor, and a second NOR gate, wherein:
a control electrode of the fourth transistor is coupled to the modulation signal terminal, a first electrode of the fourth transistor is coupled to the second end of the fourth resistor, the first end of the third capacitor and the first input end of the second nor gate, and a second electrode of the fourth transistor is coupled to the second end of the third capacitor and the ground terminal;
a first end of the fourth resistor is coupled to a common power supply terminal;
the second input terminal of the second nor gate is coupled to the modulation signal terminal, the output terminal of the second nor gate is coupled to the second input terminal of the flip-flop, and the second nor gate is configured to input the reset signal to the second input terminal of the flip-flop.
Further, the control circuit includes a third nor gate and a fourth inverter, wherein:
a first input terminal of the third nor gate is coupled to the output terminal of the timer, a second input terminal of the third nor gate is coupled to the output terminal of the flip-flop, and an output terminal of the third nor gate is coupled to a first terminal of the fourth inverter;
the second end of the fourth inverter is coupled to the charge pump, and the fourth inverter outputs a trigger signal to control the switch of the charge pump.
A second aspect of the present invention provides a power supply circuit for a DC-DC converter, the power supply circuit being provided in the DC-DC converter and including the detection circuit for a DC-DC converter of any one of the first aspects, the power supply circuit further including: first charging circuit, second charging circuit, fourth capacitor, drive circuit, fifth transistor, first diode, inductor, and output circuit, wherein:
the first end of the first charging circuit is coupled with the input voltage end, and the second end of the first charging circuit is coupled with the second end of the second charging circuit, the first end of the fourth capacitor and the first end of the driving circuit;
the first end of the second charging circuit is coupled to the output end of the control circuit in the detection circuit, and the second charging circuit is configured to charge the fourth capacitor according to the trigger signal output by the control circuit;
the input end of the driving circuit is coupled with the modulation signal end, the output end of the driving circuit is coupled with the control electrode of the fifth transistor, and the driving circuit is configured to drive the fifth transistor according to the input modulation signal;
a first pole of the fifth transistor is coupled to the input voltage end, and a second pole of the fifth transistor is coupled to the second end of the fourth capacitor, the second end of the driving circuit, the second end of the first diode and the first end of the inductor;
the first end of the first secondary tube is coupled with a grounding end;
the second end of the inductor is coupled with the output voltage end; and
the output circuit is configured to generate an output voltage signal as a function of an inductor current flowing through the inductor.
Optionally, the first charging circuit comprises: LDO module and second diode, wherein:
the first end of the LDO module is coupled with the input voltage end, and the second end of the LDO module is coupled with the first end of the second diode;
the second terminal of the second diode is coupled to the second terminal of the second charging circuit, the first terminal of the fourth capacitor and the first terminal of the driving circuit.
Optionally, the second charging circuit comprises: charge pump and third diode, wherein:
the first end of the charge pump is coupled with the output end of a control circuit in the detection circuit, the second end of the charge pump is coupled with the first end of a third diode, and the charge pump is configured to switch between a first switch state and a second switch state according to a trigger signal output by the control circuit, wherein the first switch state is that the charge pump is started, the fourth capacitor is charged through the third diode, and the second switch state is that the charge pump is stopped;
the second terminal of the third diode is coupled to the second terminal of the first charging circuit, the first terminal of the fourth capacitor and the first terminal of the driving circuit.
Optionally, the output circuit comprises: a fifth resistor, a sixth resistor, and a fifth capacitor, wherein:
a first end of the fifth resistor is coupled with the second end of the inductor, a first end of the sixth resistor and the output voltage end, and a second end of the third resistor is coupled with the ground end;
a second end of the sixth resistor is coupled to a first end of the fifth capacitor;
the second terminal of the fifth capacitor is coupled to the ground terminal.
In a detection circuit for a DC-DC converter provided in an embodiment of the present invention, the detection circuit is provided in the DC-DC converter and includes: the circuit comprises a unilateral time delay circuit, a reference voltage circuit, a capacitor voltage circuit, a comparison circuit, a first NOR gate, a timer, a logic circuit and a control circuit, wherein the input end of the timer is coupled with a modulation signal end, the output end of the timer is coupled with a first input end of the control circuit, and the timer is configured to output a first trigger signal; the first end of the single-side delay circuit is coupled with the modulation signal end, the second end of the single-side delay circuit is coupled with the first end of the capacitor voltage circuit and the second input end of the first NOR gate, the single-side delay circuit is configured to delay the rising edge of the modulation signal sent by the modulation signal end, and the single-side delay signal is output from the output end; the first end of the reference voltage circuit is coupled with the fixed voltage end, the second end of the reference voltage circuit is coupled with the first input end of the comparison circuit, and the reference voltage circuit is configured to input a reference voltage value to the first input end of the comparison circuit; a second end of the capacitance voltage circuit is coupled to a second input end of the comparison circuit, and the capacitance voltage circuit is configured to input a capacitance voltage value to the second input end of the comparison circuit; the output end of the comparison circuit is coupled with the first input end of the first NOR gate, the comparison circuit is configured to compare the reference voltage value with the capacitor voltage value, and the comparison result is input into the first input end of the first NOR gate; detecting the reference voltage value and the capacitance voltage value through a comparison circuit, detecting that the power supply is insufficient when the capacitance voltage value is smaller than the reference voltage value, and starting a charge pump for supplying power at the moment;
an output end of the first NOR gate is coupled with a first input end of the logic circuit, and the first NOR gate is configured to input an indication signal to the first input end of the logic circuit according to the comparison result and the single-side delay signal; the second input end of the logic circuit is coupled with the modulation signal end, the output end of the logic circuit is coupled with the second input end of the control circuit, and the logic circuit is configured to output a second trigger signal; the output end of the control circuit is coupled with the charge pump, the control circuit is configured to output a trigger signal according to a first trigger signal and a second trigger signal, and the charge pump is controlled to switch between a first switch state and a second switch state, wherein the first switch state is that the charge pump is turned on, and the second switch state is that the charge pump is turned off. The control circuit controls the charge pump to be switched on and switched off according to the first trigger signal and the second trigger signal, the charge pump is controlled to be switched on to supply power to the capacitor when the power supply voltage is insufficient, higher voltage is provided, the on-resistance of the power tube can be obviously reduced, the efficiency is improved, and the problems that in the prior art, the on-resistance of the power tube is increased and the working efficiency of the circuit is reduced when the charge pump charges and supplements electricity for the BST capacitor are solved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a circuit diagram of a conventional power supply circuit for a DC-DC converter;
FIG. 2 is an exemplary block diagram of a detection circuit for a DC-DC converter provided by an embodiment of the present invention;
fig. 3 is an exemplary circuit diagram of a detection circuit for a DC-DC converter according to an embodiment of the present invention;
FIG. 4 is a waveform diagram illustrating an exemplary first trigger signal in the detection circuit according to an embodiment of the present invention;
FIG. 5 is a waveform diagram illustrating an exemplary second trigger signal in the detection circuit according to an embodiment of the present invention;
fig. 6 is an exemplary circuit diagram of a power supply circuit for a DC-DC converter according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. It should be apparent that the described embodiments are only some of the embodiments of the present invention, and not all of them. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the invention without any inventive step, also belong to the scope of protection of the invention.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein, the statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together either directly or joined through one or more intermediate components.
In all embodiments of the present invention, since the sources and drains (emitters and collectors) of the transistors are symmetrical and the on-currents between the sources and drains (emitters and collectors) of the N-type transistors and the P-type transistors are opposite in direction, in an embodiment of the present invention, the controlled middle terminal of the transistor is referred to as a control electrode, and the remaining two terminals of the transistor are referred to as a first electrode and a second electrode, respectively. The transistors employed in the embodiments of the present invention are mainly switching transistors. In addition, terms such as "first" and "second" are only used to distinguish one element (or a portion of an element) from another element (or another portion of an element).
Fig. 1 shows an exemplary circuit diagram of a supply circuit for a DC-DC converter. The DC-DC converter can convert one DC voltage into other DC voltages, wherein PWM is a power tube starting signal adopting a pulse width modulation mode, the frequency of switching pulse is constant, and the output voltage is stabilized by changing the output width of the pulse; BST-UVLO is a starting charge pump signal output when the voltage of BST is lower than a reference value VREF; the LDO module is a low dropout linear regulator, is a linear voltage reduction type power management chip and is used for stably outputting a fixed voltage; the Charge _ pump is a Charge pump and is used for supplying power to the BST capacitor Cbst under a certain condition; SBD is a Schottky diode; BST and SW represent two nodes in the circuit and their respective corresponding voltage values; vin is an input voltage, vb is a fixed voltage of Vin passing through the LDO module, vout is an output voltage, cout is an output capacitor, and Resr is an equivalent series resistor.
In the BUCK type DC-DC application, when the NMOS fet is selected as the power transistor, a BST capacitor is needed to supply power to the Driver Hside of the high side Driver of the Driver part.
In some lithium battery applications, it is desirable to maximize the time of use, and it is desirable that the system provide 100% duty cycle or near 100% duty cycle modes of operation in addition to conventional applications. When the system works at a duty ratio close to 100%, the BST capacitor Cbst basically has no charging time, and at the duty ratio of 100%, the BST capacitor Cbst completely loses the charging time, and as the turn-on time is prolonged, if no power supply is supplied, the 100% turn-on state cannot be maintained, so that a charge pump is needed to supply power to the BST capacitor, and in this case, when the charge pump is connected in to supply power to the BST capacitor, the scheme becomes a research direction of the scheme.
In order to deal with the problem of when the charge pump supplies power, in the related art, a UVLO of the BST is set to detect the BST voltage, as shown in fig. 1, the UVLO comparator is a hysteresis comparator, a reference point is a reference voltage value VREF ±, a hysteresis lower limit is VREF ", and a hysteresis upper limit is VREF +. If BST-SW < VREF-, then BST-UVLO is output to be high, which indicates that the BST capacitor Cbst is under-voltage, and the charge pump is started to work to charge the BST capacitor Cbst; if BST-SW > VREF +, the output BST _ UVLO goes low, indicating that the difference in BST capacitance voltage meets the application requirements, and the charge pump stops working.
However, this solution has an important drawback: when the voltage difference of the BST capacitor is not reduced to UVLO, the charge pump does not work, and even if the charge pump works, the charge pump cannot stop charging until the voltage difference of the BST capacitor is equal to the fixed voltage Vb. When the voltage difference of the BST capacitor is smaller than VREF < - >, the charge pump is started, and Vc is the compensation of the BST capacitor Cbst; when Vc charges and supplements the BST capacitor Cbst to be larger than VREF +, the charge pump is closed, the BST capacitor is stopped supplementing power, after the BST capacitor Cbst supplies power for the high-side power tube HS driving part for a period of time, the voltage difference of the BST capacitor is reduced to be smaller than VREF-due to voltage consumption and leakage loss. Therefore, the voltage difference of the BST capacitor is always in VREF +/-range, so that the Vgs voltage of the power tube is in the value of BST _ UVLO, the self-conduction impedance of the power tube is directly increased, and the system efficiency is reduced.
An exemplary circuit diagram of the power supply circuit is shown in fig. 6, and an exemplary circuit diagram of the detection circuit is shown in fig. 3. The BST capacitor Cbst is used for supplying power for the high-side power tube HS driving part by using the power supply circuit, and in order to charge and supplement the BST capacitor Cbst when the voltage difference of the BST capacitor is reduced, the detection circuit BST-Test circuit is used for determining when to start the charge pump to charge the BST capacitor, so that the conduction impedance of the power tube is reduced, and the working efficiency of the circuit is improved.
In a continuous conduction mode (CCM mode), in a switching period, the current of the inductor is continuous, the current cannot return to 0, and the inductor is never reset; the following first calculates the total amount of BST capacitance charge in CCM from the perspective of energy conservation.
During the Toff period, SW =0, bst capacitance is complemented by Vin through the output Vb of the LDO module, the mean value of the complemented current is denoted as Ii, and the amount of complemented charge is: ii + Toff;
in the Ton time period, the power tube is turned on, under the condition of neglecting the on-resistance of the power tube, SW = Vin, BST leakage current mean value Io, the leaked electric charge amount is Io × Ton, and the electric charge amount consumed when the grid electrode of the power tube is charged is Q tot ＝Vgs*C eq Wherein, Q tot The total charge consumed to charge the power tube gate potential from 0 to the target value Vgs; c eq ＝Q tot Vgs, the equivalent capacitance of the gate during this charge.
In the supply circuit, the precondition for keeping the BST sufficiently supplied is Ii Toff>Io*Ton+Q tot (ii) a On the contrary, as time goes on, the charge of the BST capacitor will be lost without being discharged, so as long as formula Ii Toff is satisfied<Io*Ton+Q tot The charge pump needs to be turned on.
According to the formula, the following formula is obtained:
(1) When the power tube is turned on at 100% duty cycle, toff =0, so the charge pump must be turned on;
(2) When the power tube is not 100% duty cycle, since the value of Io/Ii is very small, the term Ton can be ignored, and the above formula can be adjusted as follows: ii Toff<Qtot, wherein Q tot And = Vgs × Ceq may be calculated by a simulation model, vgs is a limit value Vb, vb is a fixed voltage output by the LDO module in a high-voltage application, a voltage difference of the BST capacitor is determined by a value of Vb, and the LDO module may be removed in a low-voltage application, where Vb = Vin. Thus, a scaling can be made to define a current source Iia = Ii/n, and an analog currentCapacity C1= C eq And/m, can obtain: iia Toff/C1<Vb m/n, and the charge pump is started under the condition, so that the requirement can be met.
The following discusses a circuit diagram satisfying the charge pump turn-on schemes in (1) and (2) described above.
Case a: for the scheme of starting the charge pump in the foregoing (1), the scheme may be implemented by using a timer, and when the timer detects that the start time Ton of the power tube exceeds a duration threshold, the charge pump is started to charge the BST capacitor, for example, the duration threshold may be set to 10us or 20us according to the actual condition of the power supply circuit;
case B: for the scheme of turning on the charge pump in (2), only a detection circuit BST _ Test satisfying the formula Iia × Toff/C1< Vb × m/n is needed, and when the voltage value Iia × Toff/C1 across the capacitor C1 is smaller than the reference voltage value Vref = Vb × m/n, the charge pump is turned on to charge the BST capacitor.
By combining a circuit satisfying the above-mentioned condition a and a circuit satisfying the above-mentioned condition B into the same detection circuit, a detection circuit for detecting a charge pump turn-on condition can be obtained, such as an exemplary block diagram and an exemplary circuit diagram of a detection circuit for a DC-DC converter provided by an embodiment of the present invention shown in fig. 2 and 3, wherein the detection circuit is disposed in the DC-DC converter and the detection circuit BST _ Test includes: unilateral time delay circuit, reference voltage circuit, electric capacity voltage circuit, comparison circuit, first NOR gate, timer, logic circuit and control circuit, wherein:
the input end of the timer is coupled to the modulation signal end PWM, the output end of the timer is coupled to the first input end of the control circuit, and the timer is configured to output a first trigger signal Start1; when the timer counts the opening time Ton of the power tube HS to be greater than the time length threshold Ta, a first trigger signal Start1 is output to the control circuit, so that the control circuit controls the charge pump to be opened.
The first end of the single-side delay circuit is coupled with the modulation signal end PWM, the second end of the single-side delay circuit is coupled with the first end of the capacitor voltage circuit and the second input end of the first NOR gate, the single-side delay circuit is configured to delay the rising edge of the modulation signal sent by the modulation signal end PWM, and a single-side delay signal Kc is output from the output end;
a first end of the reference voltage circuit is coupled to the fixed voltage terminal Vb, a second end of the reference voltage circuit is coupled to a first input end of the comparison circuit, and the reference voltage circuit is configured to input a reference voltage value Vref to the first input end of the comparison circuit;
a second terminal of the capacitance-voltage circuit is coupled to the second input terminal of the comparison circuit, and the capacitance-voltage circuit is configured to input a capacitance-voltage value to the second input terminal of the comparison circuit;
the output end of the comparison circuit is coupled with the first input end of the first NOR gate, the comparison circuit is configured to compare the reference voltage value Vref with the capacitance voltage value, and the comparison result is input to the first input end of the first NOR gate;
the output end of the first NOR gate is coupled with the first input end of the logic circuit, and the first NOR gate is configured to input the indication signal Ka to the first input end of the logic circuit according to the comparison result and the single-side delay signal Kc;
a second input end of the logic circuit is coupled to the modulation signal end PWM, and an output end of the logic circuit is coupled to a second input end of the control circuit, and the logic circuit is configured to output a second trigger signal Start2; the logic circuit outputs a second trigger signal Start2 to the control circuit, and the control circuit controls the charge pump to be turned on and off.
The output end of the control circuit is coupled to the charge pump, and the control circuit is configured to output the trigger signal Start according to the first trigger signal Start1 and the second trigger signal Start2, and control the charge pump to switch between a first switch state and a second switch state, where the first switch state is that the charge pump is turned on, and the second switch state is that the charge pump is turned off. The control circuit outputs a trigger signal Start according to the first trigger signal Start1 or the second trigger signal Start2, and controls the charge pump to be turned on and off, when the charge pump is controlled to be turned on, the charge pump charges and supplements the BST capacitor Cbst, and when the charge pump is controlled to be turned off, the charge pump is in an inoperative state and does not charge the BST capacitor Cbst.
In an alternative embodiment of the present invention, the comparison circuit includes a comparator COMP and a first inverter, wherein:
the non-inverting input end of the comparator COMP is coupled to the second end of the reference voltage circuit, the inverting input end of the comparator COMP is coupled to the second end of the capacitance voltage circuit, and the output end of the comparator COMP is coupled to the first end of the first inverter;
the second terminal of the first inverter is coupled to the first input terminal of the first nor gate.
Furthermore, the third end of the reference voltage circuit is a ground end GND; the reference voltage circuit includes a first resistor R1 and a second resistor R2, wherein:
a first end of the first resistor R1 is coupled to the fixed voltage terminal Vb, and a second end of the first resistor R1 is coupled to a non-inverting input terminal of the comparator COMP and a first end of the second resistor R2;
the second end of the second resistor R2 is coupled to the ground GND.
Furthermore, the third end of the capacitance voltage circuit is a ground end GND; the capacitance-voltage circuit includes: a current source Iia, a first capacitor C1, and a first transistor Q, wherein:
the current source Iia is coupled to the first terminal of the first capacitor C1, the first pole of the first transistor Q, and the inverting input terminal of the comparator COMP;
the control electrode of the first transistor Q is coupled to the output end of the single-side delay circuit, the second electrode of the first transistor Q and the second end of the first capacitor C1 are respectively coupled to the ground GND, and the first transistor may be an N-type transistor.
In a preferred embodiment of the present invention, the timer is configured to output the first trigger signal Start1 as a high level according to the modulation signal sent by the modulation signal terminal PWM when the on duration Ton of the first transistor Q is greater than the duration threshold Ta, and control the charge pump to be turned on to charge the BST capacitor; the modulated signal comprises a pulse width modulated signal.
In an optional embodiment of the present invention, the capacitor voltage circuit includes a first transistor Q, a second terminal of the single-side delay circuit is coupled to a control electrode of the first transistor Q and a second input terminal of the first nor gate, a third terminal of the single-side delay circuit is coupled to a power supply terminal, and a fourth terminal of the single-side delay circuit is a ground terminal GND;
the single-side delay circuit comprises a second inverter, a second transistor, a third resistor Ra and a second capacitor Ca, wherein:
the first end of the second inverter is coupled with the modulation signal end PWM, the second end of the second inverter is coupled with the control electrode of the second transistor after inversion, and the second end of the second inverter is coupled with the control electrode of the third transistor; the second transistor is a P-type transistor, and the third transistor is an N-type transistor;
a first electrode of the second transistor is coupled to a common power supply terminal, and a second electrode of the second transistor is coupled to a first end of a third resistor Ra;
a first pole of the third transistor is coupled to the second terminal of the third resistor Ra and the first terminal of the second capacitor Ca, and a second pole of the third transistor is coupled to the second terminal of the second capacitor Ca and the ground terminal GND.
The operation of the one-sided delay circuit is described below with reference to the exemplary circuit diagram of the circuit in fig. 3.
When the PWM signal changes from high level to low level, the third transistor N is turned on, the second capacitor Ca is discharged, and the discharge time is short and negligible, so the delay of the single-side delay signal Kc at the falling edge of the PWM signal is negligible;
when the PWM signal changes from low level to high level, the second transistor P is turned on, the common power supply charges the second capacitor Ca, the charging time and current are limited by the third resistor Ra, the single-side delay signal Kc is delayed at the rising edge of the PWM signal, and the specific duration of the delay is controlled by the third resistor Ra and the second capacitor Ca.
In an alternative embodiment of the invention, the logic circuit comprises: NAND gate, third inverter, reset circuit, and flip-flop, wherein:
the first input end of the NAND gate is coupled with the output end of the first NOR gate, the second input end of the NAND gate is coupled with the modulation signal end PWM, and the output end of the NAND gate is coupled with the first end of the third inverter;
the second end of the third inverter is coupled to the first input end of the flip-flop;
the input end of the reset circuit is coupled with the modulation signal end PWM, the output end of the reset circuit is coupled with the second input end of the trigger, and the reset circuit is configured to reset the second trigger signal to a low level according to the falling edge of the modulation signal sent by the modulation signal end;
the output terminal of the flip-flop is coupled to the second input terminal of the control circuit, and the flip-flop is configured to output a second trigger signal Start2 according to the control signal Kb output by the second terminal of the third inverter and the reset signal reset output by the output terminal of the reset circuit. The flip-flop may be an RS flip-flop.
Further, the reset circuit includes: a fourth transistor, a fourth resistor Rb, a third capacitor Cb, and a second nor gate, wherein:
a control electrode of the fourth transistor is coupled to the modulation signal terminal PWM, a first electrode of the fourth transistor is coupled to the second end of the fourth resistor Rb, the first end of the third capacitor Cb, and the first input terminal of the second nor gate, and a second electrode of the fourth transistor is coupled to the second end of the third capacitor Cb and the ground terminal GND;
a first terminal of the fourth resistor Rb is coupled to a common power supply terminal;
a second input terminal of the second nor gate is coupled to the modulation signal terminal PWM, an output terminal of the second nor gate is coupled to a second input terminal of the flip-flop, and the second nor gate is configured to input the reset signal reset to the second input terminal of the flip-flop.
The operating principle of the reset circuit is explained below in connection with an exemplary circuit diagram of the circuit in fig. 3.
When the PWM signal keeps the high level or keeps the low level, the reset signal reset is constantly at the low level; when the PWM signal changes from high level to low level, the voltage of the upper plate of the third capacitor Cb is pulled down in a short time, the reset signal reset is set to high level, and the second trigger signal Start2 output by the RS flip-flop is reset to low level; the time for which the reset signal reset is maintained at the high level, i.e., the time during which the upper plate of the third capacitor Cb is low, is controlled by the fourth resistor Rb and the third capacitor Cb.
Further, the control circuit includes a third nor gate and a fourth inverter, wherein:
a first input end of the third nor gate is coupled to the output end of the timer, a second input end of the third nor gate is coupled to the output end of the trigger, and an output end of the third nor gate is coupled to a first end of the fourth inverter;
the second terminal of the fourth inverter is coupled to the charge pump, and the fourth inverter outputs a trigger signal Start to control the switch of the charge pump.
The working principle of the detection circuit is set forth below in connection with an exemplary circuit diagram of the detection circuit for a DC-DC converter shown in fig. 3.
Aiming at the situation A, detecting the starting time Ton of the power tube, namely detecting the time when the PWM signal is high, and when the time exceeds a timer timing duration threshold Ta, outputting a first trigger signal Start1 to be high, controlling the trigger signal Start to be high, and starting the charge pump; when the power tube is turned off, that is, when PWM =0, the first trigger signal Start1 returns to low, and the charge pump is turned off; an exemplary waveform of the first trigger signal Start1 when the PWM signal occurs at the continuously high level exceeding the duration threshold Ta is shown in fig. 4.
For the foregoing case B, in the Toff time period, that is, in the PWM =0 time period, the current source Iia charges the C1 capacitor, kc is a single-side delay signal of the PWM signal, and when the PWM signal changes from high level to low level, kc has no delay and is synchronous with PWM; when the PWM changes from low to high, kc has a small delay time, which is later than the change of the PWM signal.
If the C1 capacitor voltage is higher than Vref (Vref = Vb × m/n) in the Toff period, i.e. Ka goes low before the PWM signal goes high, the output Kb signal is constantly low, in which state the RS flip-flop outputs the second trigger signal Start2 low, i.e. the charge pump is not turned on;
if the C1 capacitor voltage is lower than Vref (Vref = Vb × m/n) during the Toff period, ka fails to flip to low before the PWM signal goes high, the output Kb signal flips to high, and in this state, the flip-flop output Start2 is high, i.e., the charge pump is turned on; when the PWM is low again, the second trigger signal Start2 output is reset to low, the charge pump is turned off, and the determination is performed again.
Fig. 5 shows an exemplary waveform diagram of the second trigger signal Start2 in the detection circuit provided in the embodiment of the present invention, which includes a PWM signal, a Kc signal, a Ka signal, a Kb signal, and a Start2 signal, where the Kc signal is a single-side delay signal of the PWM signal, and at a rising edge of the PWM signal, the Kc signal has a small delay, and the Ka signal and the PWM signal are anded to obtain the Kb signal;
when the Toff time is longer, because the Ka signal and the PWM signal do not have the time when the Ka signal and the PWM signal are at the same high level, the Kb signal is constantly low, the second trigger signal Start2 output by the RS flip-flop is low, and the charge pump is not started;
when the Toff time is short, the rising edge of the Kb signal from low to high controls the second trigger signal Start2 to be changed into high level, the charge pump is started, the falling edge of the PWM signal from high to low resets the second trigger signal Start2 to be changed into low level, and the charge pump is closed; at the next rising edge of the Kb signal, the second trigger signal Start2 goes high, turning on the charge pump.
The detection circuit controls the charge pump to be started, vgs can be guaranteed to be maximized when the power tube is started, compared with a traditional solution, the value of BST _ UVLO in the traditional solution is obviously larger, the on-resistance of the power tube can be obviously reduced, and the working efficiency of the circuit is improved.
Fig. 6 shows an exemplary circuit diagram of a power supply circuit for a DC-DC converter, the power supply circuit being provided in the DC-DC converter and the power supply circuit including the detection circuit BST-Test circuit shown in fig. 3, the power supply circuit further including: the first charging circuit, the second charging circuit, the fourth capacitor Cbst, the driving circuit Driver _ Hside, the fifth transistor HS, the first diode SBD, the inductor L, and the output circuit, the fifth transistor HS may be an N-type transistor, a high-side power transistor, wherein:
a first end of the first charging circuit is coupled to the input voltage terminal Vin, a second end of the first charging circuit is coupled to a second end of the second charging circuit, a first end of the fourth capacitor Cbst, and a first end of the driving circuit Driver _ Hside;
a first end of the second charging circuit is coupled to an output end of the control circuit in the detection circuit, and the second charging circuit is configured to charge the fourth capacitor Cbst according to a trigger signal Start output by the control circuit; the fourth capacitor Cbst may be a bootstrap capacitor; the charge pump is started according to a trigger signal Start output by a control circuit in the detection circuit, the charge pump charges and supplements electricity for the fourth capacitor Cbst, and then the fourth capacitor Cbst supplies power for a driving circuit of the power tube, so that Vgs maximization of the power tube can be ensured when the power tube is started, and compared with a traditional solution, the conduction impedance of the power tube can be obviously reduced, and the working efficiency of the circuit is improved.
The input end of the driving circuit Driver _ Hside is coupled to the modulation signal end PWM, the output end of the driving circuit Driver _ Hside is coupled to the control electrode of the fifth transistor HS, and the driving circuit Driver _ Hside is configured to drive the fifth transistor HS according to the input modulation signal; the modulation signal of the modulation signal end PWM comprises a pulse width modulation signal.
A first pole of the fifth transistor HS is coupled to the input voltage terminal Vin, and a second pole of the fifth transistor HS is coupled to the second end of the fourth capacitor Cbst, the second end of the driving circuit Driver _ Hside, the second end of the first diode SBD, and the first end of the inductor L;
the first end of the first diode SBD is coupled with a grounding end GND; the first diode SBD may be a Schottky diode SBD;
the second end of the inductor L is coupled to the output voltage terminal Vout;
the output circuit is configured to generate an output voltage signal according to an inductor current flowing through the inductor L.
In an alternative embodiment of the present invention, the first charging circuit includes: LDO module and second diode, wherein:
the first end of the LDO module is coupled with the input voltage end Vin, and the second end of the LDO module is coupled with the first end of the second diode; after the input voltage Vin passes through the LDO module, a fixed voltage Vb can be output, and the second diode can be a Schottky diode SBD;
a second terminal of the second diode is coupled to the second terminal of the second charging circuit, the first terminal of the fourth capacitor Cbst, and the first terminal of the driving circuit Driver _ Hside.
In an alternative embodiment of the present invention, the second charging circuit includes: charge pump Charge _ pump and third diode, wherein:
the first end of the charge pump is coupled with the output end of a control circuit in the detection circuit, the second end of the charge pump is coupled with the first end of a third diode, and the charge pump is configured to switch between a first switch state and a second switch state according to a trigger signal Start output by the control circuit, wherein the first switch state is that the charge pump is started, the fourth capacitor Cbst is charged through the third diode, and the second switch state is that the charge pump is stopped; when the charge pump is started, the output voltage is Vc, the BST capacitor is charged through the third diode, the voltage difference of the BST capacitor is large, vgs is maximized when the power tube is started, the on-resistance of the power tube is reduced, and the working efficiency of the circuit is improved.
A second end of the third diode is coupled to the second end of the first charging circuit, the first end of the fourth capacitor Cbst, and the first end of the driving circuit Driver _ Hside.
In an alternative embodiment of the present invention, the output circuit includes: fifth resistor R L A sixth resistor Resr, and a fifth capacitor Cout, wherein:
fifth resistor R L Is coupled to the second end of the inductor L, the first end of the sixth resistor Resr and the output voltage terminal Vout, and the fifth resistor R L The second end of the second switch is coupled with the ground end GND;
a second terminal of the sixth resistor Resr is coupled to a first terminal of the fifth capacitor Cout;
the second terminal of the fifth capacitor Cout is coupled to the ground GND.
From the above description, it can be seen that the present invention achieves the following technical effects:
the reference voltage value and the capacitance voltage value are detected through the comparator, so that the BST capacitor under-voltage can be detected in time when the capacitance voltage value is smaller than the reference voltage value, and preparation is made for subsequently starting a charge pump to charge the BST capacitor;
the control circuit controls the charge pump to be turned on and off according to the first trigger signal and the second trigger signal, the charge pump is controlled to be turned on to supply power to the capacitor when the power supply voltage is insufficient, higher voltage is provided, the on-resistance of the power tube can be obviously reduced, the efficiency is improved, and the problems that in the prior art, the on-resistance of the power tube is increased and the working efficiency of the circuit is reduced when the charge pump charges and supplements power for the BST capacitor are solved;
the charge pump is started after the detection circuit provided by the invention judges, so that the Vgs of the power tube can be ensured to be maximized when the power tube is started, and compared with the traditional solution, the on-resistance of the power tube can be obviously reduced, and the efficiency is improved.
The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus and methods according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
As used herein and in the appended claims, the singular forms of words include the plural and vice versa, unless the context clearly dictates otherwise. Thus, when reference is made to the singular, it is generally intended to include the plural of the corresponding term. Similarly, the terms "comprising" and "including" are to be construed as being inclusive rather than exclusive. Likewise, the terms "include" and "or" should be construed as inclusive unless such interpretation is explicitly prohibited herein. Where the term "example" is used herein, particularly when it comes after a set of terms, it is merely exemplary and illustrative and should not be considered exclusive or extensive.
Further aspects and scope will become apparent from the description provided herein. It should be understood that various aspects of the present application may be implemented alone or in combination with one or more other aspects. It should also be understood that the description and specific examples herein are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure.
Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope defined by the appended claims.

Claims (10)

1. A detection circuit for a DC-DC converter, wherein the detection circuit is provided in the DC-DC converter and the detection circuit comprises: unilateral time delay circuit, reference voltage circuit, electric capacity voltage circuit, comparison circuit, first NOR gate, timer, logic circuit and control circuit, wherein:
the input end of the timer is coupled with the modulation signal end, the output end of the timer is coupled with the first input end of the control circuit, and the timer is configured to output a first trigger signal;
the first end of the single-side delay circuit is coupled to the modulation signal end, the second end of the single-side delay circuit is coupled to the first end of the capacitor voltage circuit and the second input end of the first NOR gate, and the single-side delay circuit is configured to delay the rising edge of the modulation signal sent by the modulation signal end and output a single-side delay signal from the output end;
the first end of the reference voltage circuit is coupled with a fixed voltage end, the second end of the reference voltage circuit is coupled with the first input end of the comparison circuit, and the reference voltage circuit is configured to input a reference voltage value to the first input end of the comparison circuit;
a second terminal of the capacitance voltage circuit is coupled to a second input terminal of the comparison circuit, the capacitance voltage circuit configured to input a capacitance voltage value to the second input terminal of the comparison circuit;
an output terminal of the comparison circuit is coupled to a first input terminal of the first nor gate, the comparison circuit is configured to compare the reference voltage value and the capacitor voltage value, and input a comparison result to the first input terminal of the first nor gate;
an output end of the first NOR gate is coupled to a first input end of the logic circuit, and the first NOR gate is configured to input an indication signal to the first input end of the logic circuit according to the comparison result and the single-side delay signal;
the second input end of the logic circuit is coupled with the modulation signal end, the output end of the logic circuit is coupled with the second input end of the control circuit, and the logic circuit is configured to output a second trigger signal; and
the output end of the control circuit is coupled to a charge pump, and the control circuit is configured to output a trigger signal according to the first trigger signal and the second trigger signal and control the charge pump to switch between a first switch state and a second switch state, wherein the first switch state is that the charge pump is turned on, and the second switch state is that the charge pump is turned off.
2. The detection circuit of claim 1, wherein the comparison circuit comprises a comparator and a first inverter, wherein:
the non-inverting input end of the comparator is coupled to the second end of the reference voltage circuit, the inverting input end of the comparator is coupled to the second end of the capacitance voltage circuit, and the output end of the comparator is coupled to the first end of the first inverter;
a second terminal of the first inverter is coupled to a first input terminal of the first nor gate.
3. The detection circuit of claim 2, wherein the third terminal of the reference voltage circuit is a ground terminal;
the reference voltage circuit includes a first resistor and a second resistor, wherein:
a first end of the first resistor is coupled to a fixed voltage end, and a second end of the first resistor is coupled to a non-inverting input end of the comparator and a first end of the second resistor;
the second end of the second resistor is coupled to ground.
4. The detection circuit of claim 2, wherein the third terminal of the capacitor voltage circuit is a ground terminal;
the capacitance-voltage circuit includes: a current source, a first capacitor, and a first transistor, wherein:
the current source is coupled to the first terminal of the first capacitor, the first pole of the first transistor and the inverting input terminal of the comparator;
the control electrode of the first transistor is coupled to the output end of the single-side delay circuit, and the second electrode of the first transistor and the second end of the first capacitor are respectively coupled to the ground terminal.
5. The detection circuit of claim 1, wherein the timer is configured to output the first trigger signal according to a modulation signal from a modulation signal terminal when the on-duration of the first transistor is greater than a duration threshold, and wherein the modulation signal comprises a pulse width modulation signal.
6. The detection circuit according to claim 1, wherein the capacitor voltage circuit comprises a first transistor, a second terminal of the single-side delay circuit is coupled to a control electrode of the first transistor and a second input terminal of the first nor gate, a third terminal of the single-side delay circuit is coupled to a power supply terminal, and a fourth terminal of the single-side delay circuit is a ground terminal;
the single-side delay circuit comprises a second inverter, a second transistor, a third resistor and a second capacitor, wherein:
a first end of the second inverter is coupled to the modulation signal end, a second end of the second inverter is coupled to the control electrode of the second transistor after being inverted, and a second end of the second inverter is coupled to the control electrode of the third transistor;
a first pole of the second transistor is coupled to a common power source end, and a second pole of the second transistor is coupled to a first end of the third resistor;
a first pole of the third transistor is coupled to the second terminal of the third resistor and the first terminal of the second capacitor, and a second pole of the third transistor is coupled to the second terminal of the second capacitor and ground.
7. The detection circuit of claim 1, wherein the logic circuit comprises: NAND gate, third inverter, reset circuit, and flip-flop, wherein:
the first input end of the nand gate is coupled to the output end of the first nor gate, the second input end of the nand gate is coupled to the modulation signal end, and the output end of the nand gate is coupled to the first end of the third inverter;
a second terminal of the third inverter is coupled to the first input terminal of the flip-flop;
the input end of the reset circuit is coupled with the modulation signal end, the output end of the reset circuit is coupled with the second input end of the trigger, and the reset circuit is configured to reset the second trigger signal to a low level according to the falling edge of the modulation signal sent by the modulation signal end;
an output terminal of the flip-flop is coupled to the second input terminal of the control circuit, and the flip-flop is configured to output a second trigger signal according to the control signal output by the second terminal of the third inverter and the reset signal output by the output terminal of the reset circuit.
8. The detection circuit of claim 7, wherein the reset circuit comprises: a fourth transistor, a fourth resistor, a third capacitor, and a second NOR gate, wherein:
a control electrode of the fourth transistor is coupled to the modulation signal terminal, a first electrode of the fourth transistor is coupled to the second terminal of the fourth resistor, the first terminal of the third capacitor and the first input terminal of the second nor gate, and a second electrode of the fourth transistor is coupled to the second terminal of the third capacitor and the ground terminal;
a first end of the fourth resistor is coupled to a common power supply terminal;
a second input terminal of the second nor gate is coupled to the modulation signal terminal, an output terminal of the second nor gate is coupled to a second input terminal of the flip-flop, and the second nor gate is configured to input a reset signal to the second input terminal of the flip-flop.
9. The detection circuit of claim 7, wherein the control circuit comprises a third nor gate and a fourth inverter, wherein:
a first input terminal of the third nor gate is coupled to the output terminal of the timer, a second input terminal of the third nor gate is coupled to the output terminal of the flip-flop, and an output terminal of the third nor gate is coupled to the first terminal of the fourth inverter;
the second end of the fourth inverter is coupled to the charge pump, and the fourth inverter outputs a trigger signal to control the switch of the charge pump.
10. A supply circuit for a DC-DC converter, characterized in that the supply circuit is provided in a DC-DC converter and comprises the detection circuit for a DC-DC converter of any one of claims 1 to 9, the supply circuit further comprising: first charging circuit, second charging circuit, fourth capacitor, drive circuit, fifth transistor, first diode, inductor, and output circuit, wherein:
the first end of the first charging circuit is coupled to the input voltage end, and the second end of the first charging circuit is coupled to the second end of the second charging circuit, the first end of the fourth capacitor and the first end of the driving circuit;
the first end of the second charging circuit is coupled to the output end of the control circuit in the detection circuit, and the second charging circuit is configured to charge the fourth capacitor according to a trigger signal output by the control circuit;
the input end of the driving circuit is coupled to a modulation signal end, the output end of the driving circuit is coupled to the control electrode of the fifth transistor, and the driving circuit is configured to drive the fifth transistor according to an input modulation signal;
a first pole of the fifth transistor is coupled to the input voltage terminal, and a second pole of the fifth transistor is coupled to the second terminal of the fourth capacitor, the second terminal of the driving circuit, the second terminal of the first diode, and the first terminal of the inductor;
the first end of the first secondary tube is coupled with a grounding end;
the second end of the inductor is coupled with an output voltage end; and
the output circuit is configured to generate an output voltage signal as a function of an inductor current flowing through the inductor.
CN202210814789.9A 2022-07-11 Detection circuit and power supply circuit for DC-DC converter Active CN115242055B (en)

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CN117674807A (en) * 2023-12-12 2024-03-08 上海高晶检测科技股份有限公司 Control circuit system of rejection mechanism and metal detector
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