WO2023005758A1

WO2023005758A1 - Switched-mode power supply secondary-side synchronous rectifier controller, and switched-mode power supply

Info

Publication number: WO2023005758A1
Application number: PCT/CN2022/106694
Authority: WO
Inventors: 张洞田
Original assignee: 深圳英集芯科技股份有限公司
Priority date: 2021-07-30
Filing date: 2022-07-20
Publication date: 2023-02-02
Also published as: CN115694193A; CN113315383B; CN113315383A; CN115700978A

Abstract

Disclosed in embodiments of the present application are a switched-mode power supply secondary-side synchronous rectifier controller, and a switched-mode power supply. The synchronous rectifier controller comprises: a demagnetization detection circuit, a standby determination circuit, an AND gate circuit, and a drive circuit. An input terminal of the demagnetization detection circuit is connected to one end of a synchronous rectification MOS Q2 of the switched-mode power supply. One output terminal of the demagnetization detection circuit is connected to one input terminal of the AND gate circuit, and the other output terminal of the demagnetization detection circuit is connected to an input terminal of the standby determination circuit. An output terminal of the standby determination circuit is connected to the other input terminal of the AND gate circuit. An output terminal of the AND gate circuit is connected to an input terminal of the drive circuit. An output terminal of the drive circuit is connected to a gate of the MOS Q2. The technical solution of the present application has the advantage of improving the system efficiency.

Description

Switching power supply secondary side synchronous rectification controller and switching power supply

This application claims the priority of the Chinese patent application with the application number 2021108681805 and the application name "Switching Power Supply Secondary Side Synchronous Rectification Controller and Switching Power Supply" submitted to the China Patent Office on July 30, 2021, the entire contents of which are incorporated by reference incorporated in this application.

technical field

This application relates to the technical field of switching power supplies, in particular to a secondary-side synchronous rectification controller of a switching power supply and a switching power supply.

Background technique

With the continuous increase of charging power of mobile terminals, people pay more and more attention to energy efficiency, and all countries and regions are constantly improving energy efficiency standards. The application of the synchronous rectification controller replaces the traditional Schottky diode rectification, which greatly improves the charging efficiency of the adapter and charger, so it is more and more widely used. However, the prior art of the synchronous rectification controller does improve the charging efficiency of the power system under heavy load, but it ignores that the power consumption of the synchronous rectification controller itself reduces the system efficiency when the power supply is no-load or light-load, and increases the The standby power consumption of the system wastes a lot of energy and increases energy consumption.

Contents of the invention

Therefore, in order to solve the problem of high energy consumption in the prior art, the present application proposes a secondary-side synchronous rectification controller of a switching power supply.

The application solves the above problems through the following technical means:

The present application provides a synchronous rectification controller on the secondary side of a switching power supply. The synchronous rectification controller includes: a demagnetization detection circuit, a standby judgment circuit, an AND gate circuit, and a drive circuit; wherein, the input terminal of the demagnetization detection circuit is connected to the One end of the synchronous rectification MOS Q2 of the switching power supply, one output end of the demagnetization detection circuit is connected with an input end of the AND gate circuit, and the other output end of the demagnetization detection circuit is connected with the input end of the standby judgment circuit , the output end of the standby judgment circuit is connected to the other input end of the AND gate circuit, the output end of the AND gate circuit is connected to the input end of the driving circuit, and the output end of the driving circuit is connected to the MOS Gate of Q2;

The demagnetization detection circuit is used to detect the voltage difference VDET between the drain and the source of the MOS Q2, and output the DEMAG signal through two output terminals when the VDET is lower than the set threshold;

The standby judging circuit is used to integrate the DEMAG signal and compare it with a set threshold to obtain a comparison result, and determine whether the output signal V _G-EN is valid according to the comparison result;

The AND gate circuit is used to output the V _gate signal according to the DEMAG signal and V _G-EN ;

The driving circuit is configured to judge whether to output a VG signal to the gate of the MOS Q2 to drive the MOS Q2 according to the V _gate signal.

Optionally, the demagnetization detection circuit includes: a first comparator, an inverter INV, a resistor, and a reference voltage V _DET-ref ; wherein,

The non-inverting input end of the first comparator is connected to one end of the first resistor R1, the other end of the first resistor R1 is connected to VDET, the inverting input end of the first comparator is connected to the reference voltage V _DET-ref , and the two ends of the second resistor R2 terminals are respectively connected to the non-inverting input terminal and the output terminal of the first comparator, and the output terminal of the first comparator outputs the DEMAG signal through the inverter INV.

Optionally, the standby judgment circuit includes: a current source, a MOS transistor, a clock signal CLK, a comparator, a capacitor, an OR gate circuit, a buffer circuit BUF, a D flip-flop, and an inverter; wherein,

The drain of the first MOS transistor is connected to the current source I _charge , the gate of the first MOS transistor is connected to the DEMAG signal, the source of the first MOS transistor is connected to the drain of the second MOS transistor and one end of the capacitor C1, and the gate of the second MOS transistor The pole is connected to the clock signal CLK, the source of the second MOS transistor and the other end of the capacitor C1 are grounded;

Both the non-inverting input terminals of the second comparator and the third comparator are connected to the source of the first MOS transistor, the inverting input terminal of the second comparator is connected to the voltage V _TH , and the enabling terminal of the second comparator is connected to

The inverting input terminal of the third comparator is connected to the voltage V _TL , and the enable terminal of the third comparator is connected to V _G-EN ;

The two input ends of the OR gate circuit are respectively connected to the output end of the second comparator and the output end of the third comparator, the output end of the OR gate circuit is connected to the input end of the buffer circuit BUF, and the output end of the buffer circuit BUF is connected to the D flip-flop The signal input terminal of the D flip-flop is connected to the clock signal CLK, the output terminal of the D flip-flop outputs V _G-EN , and the V _G-EN signal is output through the inverter

Signal.

Optionally, the standby judging circuit judges whether the switching power supply is in a heavy-load or light-load state in the current cycle according to the relationship between V _C1 and V _TH , V _TL .

Optionally, the standby judging circuit includes: a resistor, an operational amplifier, a MOS transistor, a clock signal CLK, a comparator, a capacitor, an OR gate circuit, a buffer circuit BUF, a D flip-flop, and an inverter; wherein,

One end of the fifth resistor R5 is connected to the DEMAG signal, the other end is connected to the non-inverting input of the operational amplifier, the inverting input of the operational amplifier is connected to the source of the first MOS transistor, and the drain of the first MOS transistor is connected to the output of the operational amplifier. The power supply terminal on the positive side of the amplifier is connected to the voltage source VCC, and the power supply terminal on the opposite side is grounded. input terminal;

One end of the second capacitor C2 is connected to the non-inverting input terminal of the operational amplifier, the other end of the second capacitor C2 is grounded, the drain of the second MOS transistor is connected to the non-inverting input terminal of the operational amplifier, and the source of the second MOS transistor is grounded. Both the gate of the second MOS transistor and the gate of the first MOS transistor are connected to the clock signal CLK;

The noninverting input terminals of the second comparator and the third comparator are connected to the output terminal V _C1 of the operational amplifier, the inverting input terminal of the second comparator is connected to the voltage V _TH , and the enable terminal of the second comparator is connected to

The two input ends of the OR gate circuit are respectively connected to the output end of the second comparator and the output end of the third comparator, the output end of the OR gate circuit is connected to the input end of the buffer circuit BUF, and the output end of the buffer circuit BUF is connected to the D flip-flop The signal input terminal of the D flip-flop is connected to the clock signal CLK, the output terminal of the D flip-flop outputs V _G-EN , and the V _G-EN signal is obtained through the inverter

Signal.

Optionally, the standby judging circuit includes: a resistor, an operational amplifier, a MOS tube, a comparator, a capacitor, an OR gate circuit, a buffer circuit BUF, a D flip-flop, and an inverter; wherein,

One end of the fifth resistor R5 is connected to the DEMAG signal, the other end is connected to the inverting input terminal of the operational amplifier, the positive input terminal of the operational amplifier is grounded, the positive side power supply terminal is connected to the voltage source VCC, the reverse side power supply terminal is connected to the voltage source -VCC, and the first capacitor C1 The two ends are respectively connected to the output terminal and the inverting input terminal of the operational amplifier;

The drain of the first MOS transistor is connected to the inverting input terminal of the operational amplifier, the source of the first MOS transistor is connected to the output terminal of the operational amplifier, and the gate of the first MOS transistor is connected to the clock signal CLK;

The inverting input terminals of the second comparator and the third comparator are both connected to the output terminal V _C1 of the operational amplifier, the non-inverting input terminal of the second comparator is connected to the voltage -V _TH , and the enabling terminal of the second comparator is connected to

The positive phase input terminal of the third comparator is connected to the voltage -V _TL , and the enable terminal of the third comparator is connected to V _G-EN ;

Signal.

Optionally, the standby judging circuit judges whether the switching power supply is in a heavy-load or light-load state in the current cycle according to the relationship between V _C1 and -V _TH , -V _TL .

The present application also provides a switching power supply, which includes: the above-mentioned secondary-side synchronous rectification controller of the switching power supply.

Optionally, the switching power supply is: a flyback converter topology circuit, a forward converter topology circuit, an LLC converter topology circuit, a half-bridge converter topology circuit, a full-bridge converter topology circuit or a push-pull converter topology circuit .

The synchronous rectification controller and its standby mode control circuit proposed in this application generate a demagnetization signal DEMAG by detecting the voltage drop at both ends of the synchronous rectification MOS, and output V _{G_EN} by detecting the length of the effective time t _on of DEMAG within a fixed time T _CLK to determine whether Switch between normal working mode and standby mode. When the synchronous rectification controller of the present application changes from heavy load to light load or no load, switching from the normal working mode to the standby mode can reduce the power consumption of the synchronous rectification controller and achieve the purpose of improving system efficiency.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those skilled in the art, other drawings can also be obtained based on these drawings without creative effort.

Fig. 1 is a schematic block diagram of a secondary side synchronous rectification controller of a switching power supply provided by the present application;

Fig. 2 is the schematic diagram of the synchronous rectification controller and its standby mode control provided by the present application;

Fig. 3 is a schematic diagram of key waveforms when the synchronous rectification controller of the present application is switched from a heavy load to a light load or no load, and the normal working mode is switched to the standby mode;

Fig. 4 is a schematic diagram of key waveforms of switching from standby mode to normal working mode when the synchronous rectification controller of the present application enters heavy load from light load or no load;

Fig. 5 is the control flowchart of the synchronous rectification controller that the present application proposes;

Fig. 6 is another control schematic diagram of the synchronous rectification controller and its standby mode proposed by the present application;

Fig. 7 is another control schematic diagram of the synchronous rectification controller and its standby mode proposed in the present application.

Detailed ways

In order to make the above purpose, features and advantages of the present application more obvious and understandable, the technical solution of the present application will be described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be pointed out that the described implementation examples are only some of the embodiments of the application, not all of the embodiments. Based on the embodiments of the application, all those skilled in the art can obtain without creative work. Other embodiments all belong to the protection scope of the present application.

Referring to Fig. 1, Fig. 1 is a schematic block diagram of the secondary side synchronous rectification controller of the switching power supply of the present application, wherein the switching power supply can be a flyback converter topology circuit, a forward converter topology circuit, an LLC converter topology circuit, a half-bridge Any one of topological circuits such as converter topological circuit, full-bridge converter topological circuit, push-pull converter topological circuit, etc., refer to Figure 1, the synchronous rectification controller includes: demagnetization detection circuit, standby judgment circuit, AND gate, drive circuit . Wherein, the input end of the demagnetization detection circuit is connected to one end of the synchronous rectification MOS Q2 of the switching power supply, one output end of the demagnetization detection circuit is connected to an input end of the AND gate circuit, and the other end of the demagnetization detection circuit The output end is connected to the input end of the standby judgment circuit, the output end of the standby judgment circuit is connected to the other input end of the AND gate circuit, and the output end of the AND gate circuit is connected to the input end of the drive circuit , the output end of the drive circuit is connected to the gate of the MOS Q2.

The demagnetization detection circuit is used to detect the voltage difference VDET between the drain and the source of the MOS Q2, and output a DEMAG signal through two output terminals when the VDET is lower than a set threshold.

The standby judging circuit is used to integrate the DEMAG signal and compare it with a set threshold to obtain a comparison result, and determine whether the output channel V _G-EN is valid according to the comparison result.

The AND gate circuit is used to output the V _gate signal according to the DEMAG signal and V _G-EN .

The synchronous rectification controller proposed in this application has two working modes: normal working mode and standby mode. The demagnetization detection circuit samples the Vds at both ends of the synchronous rectification MOS Q2 through the VDET pin, and gives a DEMAG signal when the Vds is lower than the set threshold. The standby judging circuit compares the integrated DEMAG signal with the set threshold to judge whether the current power system is under light load or no load, thereby judging whether the synchronous rectifier controller enters the standby mode, and gives whether to enable the drive output signal V _{G_EN} . V _{G_EN} and DEMAG pass through the AND gate to output Vgate. Based on the Vgate signal, the driving circuit strengthens the driving capability, and outputs the VG signal to drive the synchronous rectification MOS Q2.

FIG. 2 is a schematic diagram of the first synchronous rectification controller proposed in the present application and its standby mode control, which is a further detailed description of the synchronous rectification controller in FIG. 1 . Figure 2 shows the detailed demagnetization detection circuit principle and standby judgment circuit principle. Specifically, it may include: the demagnetization detection circuit includes: a first comparator, an inverter INV, a resistor, and a reference voltage V _DET-ref ; wherein, the positive phase input terminal of the first comparator is connected to one end of the first resistor R1, and the first resistor The other end of R1 is connected to VDET, the inverting input end of the first comparator is connected to the reference voltage V _DET-ref , and the two ends of the second resistor R2 are respectively connected to the non-inverting input end and output end of the first comparator. The output terminal of the comparator outputs the DEMAG signal through the inverter INV.

The standby judgment circuit includes: a current source, a MOS tube, a clock signal CLK, a comparator, a capacitor, an OR gate circuit, a buffer circuit BUF, a D flip-flop, and an inverter; wherein the drain of the first MOS tube is connected to the current source I _charge , The gate of the first MOS transistor is connected to the DEMAG signal, the source of the first MOS transistor is connected to the drain of the second MOS transistor and one end of the capacitor C1, the gate of the second MOS transistor is connected to the clock signal CLK, and the source of the second MOS transistor And the other end of the capacitor C1 is grounded; the non-inverting input terminals of the second comparator and the third comparator are connected to the source of the first MOS tube, the inverting input terminal of the second comparator is connected to the voltage V _TH , the second comparator The enable terminal connection

Signal.

The demagnetization detection circuit shown in Fig. 2 includes R1, R2, comparator 1 and reference voltage V _{DET_ref} . When the sampled VDET voltage drops rapidly and falls below

(For example, set about -85mV), the output of comparator 1 is low level, and after passing through the inverter INV, it outputs DEMAG high level, indicating that the start of demagnetization is detected. When the sampled VDET voltage rises gradually and is higher than

(Set about -5mV), the output of comparator 1 is high level, and the output of DEMAG is low level after passing through the inverter INV, indicating that the end of demagnetization is detected.

Figure 2 also shows the principle of the standby judgment circuit. During the demagnetization process, that is, when DEMAG is at a high level, the DEMAG signal drives the MOS Q1 to open, the current source I _charge charges the capacitor C1, and the rising level of V _C1 is:

Among them, t _ON is the duration of DEMAG high level. When DEMAG is at low level, that is, not within the demagnetization time, MOS Q1 is turned off, and V _C1 remains unchanged. Each VDET pulse will repeat the above-mentioned process once, so as to realize the voltage rise and accumulation of V _C1 during each DEMAG high level period. By detecting the relationship between the V _C1 voltage within a given time T _CLK and the set threshold V _TL /V _TH , the heavy load or light load state of the switching power supply in the current cycle can be judged, and then the synchronous rectifier is controlled to enter the normal working mode or standby mode. Both T _CLK and V _TL /V _TH here can be set, which is convenient for setting different standby mode trigger thresholds in different applications.

There are four situations in the standby judgment circuit: 1. Enter the standby mode from the normal working mode, that is, V _{G_EN changes} from the high level of the current cycle to the low level of the next CLK cycle; 2. Maintain the normal working mode, that is, the next CLK Periodically keep the current V _{G_EN} at high level; 3. Restore from standby mode to normal working mode, that is, V _{G_EN changes} from the low level of the current period to the high level of the next CLK period; 4. Keep the standby mode, that is, the next The CLK cycle keeps the current V _{G_EN} low.

Both the above-mentioned first case and the second case occur when the current V _{G_EN} is at a high level, that is, the current synchronous rectification controller is in the normal working mode, the comparator 3 enable signal V _{G_EN} is high, and the output is active. The comparator 2 enable signal

is low, the output is always low. When the rising edge of the next CLK arrives, if V _C1 >V _TL , the output of comparator 3 is high level, after the OR gate and BUF delay, the VD signal is high level, and the D flip-flop output V _{G_EN} remains at High level, that is, the second case of the standby judgment circuit: the synchronous rectification controller maintains the normal working mode. When the rising edge of the next CLK arrives, if V _C1 ≤ V _TL , the output of comparator 3 is low level, and comparator 2 is enabled due to the enable signal

is low, the output is always low, after the OR gate and BUF delay, the VD signal is low, and the D flip-flop output V _{G_EN changes} from high to low, which is the first type of standby judgment circuit Situation: Synchronous rectification controller enters standby mode from normal operation mode.

The above-mentioned third case and fourth case both occur when the current V _{G_EN} is low, that is, when the current synchronous rectification controller is in standby mode, the enable signal V _{G_EN} of the comparator 3 is low, and the output is always low. Comparator 2 enable signal

High, the output is active level. When the rising edge of the next CLK arrives, if V _C1 >V _TH , the output of comparator 2 is high level, after the OR gate and BUF delay, the VD signal is high level, and the D flip-flop output V _{G_EN changes} from low to The level turns to high level, that is, the third case of the standby judgment circuit: the synchronous rectification controller returns to the normal working mode from the standby mode. If the rising edge of the next CLK arrives, V _C1 ≤ V _TH , then the output of comparator 2 is low level, and the output of comparator 3 is always low level because the enable signal V _{G_EN} is low, through the OR gate and BUF After the delay, the VD signal is at low level, and the D flip-flop output V _{G_EN} remains at low level, which is the fourth case of the standby judgment circuit: the synchronous rectification controller maintains the standby mode.

The output signal V _{G_EN} of the standby judgment circuit and the demagnetization signal DEMAG are input to an AND gate (AND), and the AND gate outputs V _gate to the driving circuit. The driving circuit strengthens the driving ability, outputs a signal VG synchronized with V _gate to the gate of the synchronous rectification MOS Q2, and controls the switch of the synchronous rectification MOS. The above is the basic principle of implementing the synchronous rectification controller and its standby mode control in the present application.

FIG. 3 is a schematic diagram of key waveforms when the synchronous rectification controller of the present application is switched from a normal working mode to a standby mode when it changes from a heavy load to a light load or no load. At the beginning of the time, t=0, CLK sends out a pulse signal. When the pulse signal is at a high level, the MOS Q2 is turned on to discharge the C1 capacitor, and V _C1 is quickly discharged to zero, as shown in the waveform of V _C1 in Figure 3. After the CLK pulse, whenever VDET drops rapidly and satisfies "VDET<V _{DET_ref_L} ", the demagnetization signal DEMAG becomes high level, and V _{G_EN} outputs V _gate to high level through the AND gate. At the same time, the high level of the demagnetization signal DEMAG drives the MOS Q1 to open, and charges the C1 capacitor, and the rising level of V _C1 is:

Among them, t _ON is the duration of DEMAG high level. When DEMAG is low level, that is, when it is not within the demagnetization time, MOS Q1 is turned off, and VC1 remains unchanged. Each VDET pulse will repeat the above-mentioned process once, so as to realize the voltage rise and accumulation of V _C1 during each DEMAG high level period. Until the rising edge of the next CLK arrives, the cumulative rise of V _C1 does not exceed V _TL , and the output V _{G_EN} of the D flip-flop turns from high level to low level, and remains low until the next CLK arrives to achieve synchronization The rectifier controller switches from normal operating mode to standby mode.

FIG. 4 is a schematic diagram of key waveforms when the synchronous rectification controller of the present application is switched from a light load or no load to a heavy load, switching from a standby mode to a normal working mode. At the beginning of the time, t=0, CLK sends out a pulse signal. When the pulse signal is at a high level, the MOS Q2 is turned on to discharge the C1 capacitor, and V _C1 is quickly discharged to zero, as shown in the V _C1 waveform in the figure. After the CLK pulse, whenever VDET drops rapidly and satisfies "VDET<V _{DET_ref_L} ", the demagnetization signal DEMAG becomes high level, drives MOS Q1 to open, and charges C1 capacitor, and the rising level of V _C1 is:

Among them, t _ON is the duration of DEMAG high level. When DEMAG is low level, that is, when it is not within the demagnetization time, MOS Q1 is turned off, and V _C1 remains unchanged. Each VDET pulse will repeat the above-mentioned process once, so as to realize the voltage rise and accumulation of V _C1 during each DEMAG high level period. Until the next rising edge of CLK arrives, V _C1 accumulates and rises to satisfy V _C1 >V _TH , the D flip-flop output V _{G_EN changes} from low level to high level, and remains at high level until the next CLK comes, Realize the switching of the synchronous rectification controller from the standby mode to the normal working mode.

Fig. 5 is a control flow chart of the synchronous rectification controller proposed in this application. The specific implementation circuit and implementation principle of the flowchart follow the block diagram of the synchronous rectification controller in Figure 1 and the synchronous rectification controller and its standby mode control principle proposed in Figure 2. The detailed control process steps are:

Step 1: start;

Step 2: Power-on reset, initialize the sampling module, initialize each part of the logic circuit, the default VG is low;

Step 3: Enter the normal working mode, CLK pulses, V _C1 is cleared, V _{G_EN} is enabled, and VG is output normally;

Step 4: VDET detects the demagnetization time, and charges C1 within the demagnetization time;

Step 5: When the timing of T _CLK ends and the rising edge of the next CLK pulse, judge whether V _C1 is smaller than V _TL . If yes, go to step 6; if not, go to step 3;

Step 6: Enter standby mode, CLK pulses, V _C1 is cleared, V _{G_EN} is disabled, and VG has no output;

Step 7: VDET detects the demagnetization time, and charges C1 within the demagnetization time;

Step 8: When the timing of T _CLK ends and the rising edge of the next CLK pulse, judge whether V _C1 is greater than V _TH . If yes, go to step 3; if not, go to step 6.

Fig. 6 is another control schematic diagram of the synchronous rectification controller and its standby mode proposed in this application. The demagnetization detection circuit is exactly the same as the first synchronous rectification controller and its standby mode control schematic diagram proposed in Fig. 2, the difference lies in Fig. 2 The standby judgment circuit uses DEMAG to control the I _charge to charge the capacitor C1 to realize

That is, V _C1 and t _on are proportional to the first-order function relationship. The standby judging circuit as shown in Figure 6 includes: a resistor, an operational amplifier, a MOS tube, a clock signal CLK, a comparator, a capacitor, an OR gate circuit, a buffer circuit BUF, a D flip-flop, and an inverter; wherein, the fifth One end of resistor R5 is connected to the DEMAG signal, and the other end is connected to the non-inverting input of the operational amplifier. The inverting input of the operational amplifier is connected to the source of the first MOS transistor, and the drain of the first MOS transistor is connected to the output of the operational amplifier. The positive side power supply terminal is connected to the voltage source VCC, the reverse side power supply terminal is grounded, the two ends of the sixth resistor R6 are respectively connected to the inverting input terminal of the operational amplifier and the reference ground, and the two ends of the first capacitor C1 are respectively connected to the output terminal and the inverting input terminal of the operational amplifier. ; One end of the second capacitor C2 is connected to the non-inverting input terminal of the operational amplifier, the other end of the second capacitor C2 is grounded, the drain of the second MOS transistor is connected to the non-inverting input terminal of the operational amplifier, and the source of the second MOS transistor is grounded. Both the gate of the second MOS transistor and the gate of the first MOS transistor are connected to the clock signal CLK; the non-inverting input terminals of the second comparator and the third comparator are connected to the output terminal V _C1 of the operational amplifier, and the The inverting input terminal is connected to the voltage V _TH , and the enable terminal of the second comparator is connected to

The inverting input terminal of the third comparator is connected to the voltage V _TL , the enable terminal of the third comparator is connected to V _G-EN ; the two input terminals of the OR gate circuit are respectively connected to the output terminal of the second comparator and the third comparator The output end of the OR gate circuit is connected to the input end of the buffer circuit BUF, the output end of the buffer circuit BUF is connected to the signal input end of the D flip-flop, the clock port of the D flip-flop is connected to the clock signal CLK, and the output end of the D flip-flop Output V _G-EN , the V _G-EN signal is obtained through an inverter

Signal.

As shown in Figure 6, the standby judging circuit in Figure 6 is replaced by a positive-phase integral circuit composed of an operational amplifier, R5, C2, Q2, R6, C1, and Q1, and R5*C2=R6*C1, then there is

Also realize the linear function relationship in which V _C1 is directly proportional to t _on , wherein V _DEMAG is the voltage value when DEMAG is at a high level. when the value

, then the second synchronous rectification controller and its standby mode control schematic diagram proposed in this application can achieve exactly the same functions as the first synchronous rectification controller and its standby mode control schematic diagram. Refer to Figure 3 and Figure 4 for key waveforms.

Fig. 7 is another control schematic diagram of the synchronous rectification controller and its standby mode proposed in this application. The demagnetization detection circuit is exactly the same as the synchronous rectification controller and its standby mode control schematic diagram proposed in Fig. 2 and Fig. 6, as shown in Fig. 7 The standby judgment circuit includes: resistors, operational amplifiers, MOS tubes, comparators, capacitors, OR gate circuits, buffer circuits BUF, D flip-flops, and inverters; among them, one end of the fifth resistor R5 is connected to the DEMAG signal, and the other end is connected to the operation The inverting input terminal of the amplifier, the positive-phase input terminal of the operational amplifier is grounded, the positive-side power supply terminal is connected to the voltage source VCC, the reverse-side power supply terminal is connected to the voltage source -VCC, and the two ends of the first capacitor C1 are respectively connected to the output terminal and the inverting input of the operational amplifier. terminal; the drain of the first MOS transistor is connected to the inverting input terminal of the operational amplifier, the source of the first MOS transistor is connected to the output terminal of the operational amplifier, and the gate of the first MOS transistor is connected to the clock signal CLK; the second comparator and the second comparator The inverting input terminals of the three comparators are connected to the output terminal V _C1 of the operational amplifier, the non-inverting input terminal of the second comparator is connected to the voltage -V _TH , and the enabling terminal of the second comparator is connected to

The positive phase input terminal of the third comparator is connected to the voltage -V _TL , the enable terminal of the third comparator is connected to V _G-EN ; the two input terminals of the OR gate circuit are respectively connected to the output terminal of the second comparator and the third comparator The output terminal of the OR gate circuit is connected to the input terminal of the buffer circuit BUF, the output terminal of the buffer circuit BUF is connected to the signal input terminal of the D flip-flop, the clock port of the D flip-flop is connected to the clock signal CLK, and the output of the D flip-flop Terminal output V _G-EN , V _G-EN signal is obtained through the inverter

Signal.

Referring to Figure 7, the difference is that the standby judgment circuit in Figure 2 uses DEMAG to control the I _charge to charge the capacitor C1 to realize

That is, V _C1 and t _on are proportional to the primary function relationship; Figure 7 is replaced here with a positive-phase integral circuit composed of operational amplifiers, R5, C2, Q2, R6, C1, and Q1, and R5*C2=R6*C1, then there is

Also realize the linear function relationship in which V _C1 is directly proportional to t _on , wherein V _DEMAG is the voltage value when DEMAG is at a high level. In Figure 7, the inverting integral circuit composed of operational amplifier, R5, C1, and Q1 is used, then there is

Realize the first-order functional relationship in which V _C1 and t _on are negatively correlated, where V _DEMAG is the voltage value when DEMAG is at a high level. Since the VC1 output by the inverting integrator is a negative value, the input conditions of comparator 2 and comparator 3 need to be adjusted accordingly: the input reference value is changed from V _TL /V _TH to (-V _TL )/(-V _TH ), and at the same time Set the input reference as the positive input of the comparator and V _C1 as the negative input. Other parts of the standby judging circuit are consistent with those shown in Figure 2 and Figure 6 to achieve the same function.

In summary, the synchronous rectification controller and its standby mode control circuit proposed in this application generate the demagnetization signal DEMAG by detecting the voltage drop across the synchronous rectification MOS, and output the demagnetization signal DEMAG by detecting the effective time t _on of DEMAG within the fixed time T _CLK V _{G_EN} , to judge whether to switch between normal working mode and standby mode. When the synchronous rectification controller of the present application changes from heavy load to light load or no load, switching from the normal working mode to the standby mode can reduce the power consumption of the synchronous rectification controller and achieve the purpose of improving system efficiency.

This application provides three representative synchronous rectification controllers and their standby mode control circuits, which are only preferred implementation cases and are not intended to limit this application. For those skilled in the art, they can have Various changes and variations. Any modifications, replacements, improvements, etc. within the scope of the design principles and spirits proposed in this application are within the scope of protection of this application.

Claims

A secondary-side synchronous rectification controller of a switching power supply, characterized in that the synchronous rectification controller includes: a demagnetization detection circuit, a standby judgment circuit, an AND gate circuit, and a drive circuit; wherein, the input terminal of the demagnetization detection circuit is connected to One end of the synchronous rectification MOS Q2 of the switching power supply, an output end of the demagnetization detection circuit is connected with an input end of the AND gate circuit, and the other output end of the demagnetization detection circuit is connected with the input end of the standby judgment circuit connected, the output end of the standby judgment circuit is connected to the other input end of the AND gate circuit, the output end of the AND gate circuit is connected to the input end of the driving circuit, and the output end of the driving circuit is connected to the Gate of MOS Q2;

The demagnetization detection circuit is used to detect the voltage difference VDET between the drain and the source of the MOS Q2, and when the VDET is lower than the set threshold, output the DEMAG signal through two output terminals;

The standby judging circuit is used to integrate the DEMAG signal and compare it with a set threshold to obtain a comparison result, and determine whether the output signal V G-EN is valid according to the comparison result;

The AND gate circuit is used to output a V gate signal according to the DEMAG signal and V G-EN ;

The driving circuit is configured to judge whether to output a VG signal to the gate of the MOS Q2 to drive the MOS Q2 according to the V gate signal.
The secondary-side synchronous rectification controller of a switching power supply according to claim 1, wherein the demagnetization detection circuit comprises: a first comparator, an inverter INV, a resistor, and a reference voltage V DET-ref ; wherein,

The non-inverting input end of the first comparator is connected to one end of the first resistor R1, the other end of the first resistor R1 is connected to the VDET, and the inverting input end of the first comparator is connected to the reference voltage V DET- ref , both ends of the second resistor R2 are respectively connected to the non-inverting input terminal and the output terminal of the first comparator, and the output terminal of the first comparator outputs the DEMAG signal through the inverter INV.
According to the secondary side synchronous rectification controller of switching power supply according to claim 1 or 2, it is characterized in that the standby judging circuit comprises: a current source, a MOS transistor, a clock signal CLK, a comparator, a capacitor, an OR gate circuit, a buffer Circuit BUF, D flip-flop, inverter; where,

The drain of the first MOS transistor is connected to the current source I charge , the gate of the first MOS transistor is connected to the DEMAG signal, the source of the first MOS transistor is connected to the drain of the second MOS transistor and one end of the capacitor C1, the The gate of the second MOS transistor is connected to the clock signal CLK, and the source of the second MOS transistor and the other end of the capacitor C1 are grounded;

The non-inverting input terminals of the second comparator and the third comparator are both connected to the source of the first MOS transistor, the inverting input terminal of the second comparator is connected to the voltage V TH , and the enabling of the second comparator end connection
The inverting input terminal of the third comparator is connected to the voltage V TL , and the enable terminal of the third comparator is connected to V G-EN ;

The two input ends of the OR gate circuit are respectively connected to the output end of the second comparator and the output end of the third comparator, the output end of the OR gate circuit is connected to the input end of the buffer circuit BUF, and the The output end of the buffer circuit BUF is connected to the signal input end of the D flip-flop, the clock port of the D flip-flop is connected to the clock signal CLK, and the output end of the D flip-flop outputs V G-EN , V G-EN The signal is output through the inverter
Signal.
The secondary side synchronous rectification controller of the switching power supply according to claim 3, characterized in that,

The standby judging circuit judges whether the switching power supply is in a heavy-load or light-load state in the current cycle according to the relationship between V C1 and V TH , V TL .
The secondary-side synchronous rectification controller of the switching power supply according to claim 1 or 2, wherein the standby judgment circuit comprises: a resistor, an operational amplifier, a MOS transistor, a clock signal CLK, a comparator, a capacitor, or an OR gate circuit , buffer circuit BUF, D flip-flop, inverter; where,

One end of the fifth resistor R5 is connected to the DEMAG signal, the other end is connected to the non-inverting input end of the operational amplifier, the inverting input end of the operational amplifier is connected to the source of the first MOS transistor, and the drain of the first MOS transistor Connect the output terminal of the operational amplifier, the positive power supply terminal of the operational amplifier is connected to the voltage source VCC, the reverse power supply terminal is grounded, the two ends of the sixth resistor R6 are respectively connected to the inverting input terminal of the operational amplifier and the reference ground, and the first capacitor C1 The two ends are respectively connected to the output terminal and the inverting input terminal of the operational amplifier;

One end of the second capacitor C2 is connected to the non-inverting input end of the operational amplifier, the other end of the second capacitor C2 is grounded, the drain of the second MOS transistor is connected to the non-inverting input end of the operational amplifier, and the second MOS transistor The source of the MOS transistor is grounded, and the gate of the second MOS transistor and the gate of the first MOS transistor are both connected to the clock signal CLK;

The non-inverting input terminals of the second comparator and the third comparator are connected to the output terminal V C1 of the operational amplifier, the inverting input terminal of the second comparator is connected to the voltage V TH , and the enabling terminal of the second comparator connect
The inverting input terminal of the third comparator is connected to the voltage V TL , and the enable terminal of the third comparator is connected to V G-EN ;

The two input ends of the OR gate circuit are respectively connected to the output end of the second comparator and the output end of the third comparator, the output end of the OR gate circuit is connected to the input end of the buffer circuit BUF, and the The output end of the buffer circuit BUF is connected to the signal input end of the D flip-flop, the clock port of the D flip-flop is connected to the clock signal CLK, and the output end of the D flip-flop outputs V G-EN , V G-EN The signal is obtained through the inverter
Signal.
The secondary side synchronous rectification controller of the switching power supply according to claim 5, wherein,

The standby judging circuit judges whether the switching power supply is in a heavy-load or light-load state in the current cycle according to the relationship between V C1 and V TH , V TL .
According to the secondary side synchronous rectification controller of the switching power supply according to claim 1 or 2, it is characterized in that the standby judgment circuit comprises: a resistor, an operational amplifier, a MOS tube, a comparator, a capacitor, an OR gate circuit, and a buffer circuit BUF , D flip-flop, inverter; among them,

One end of the fifth resistor R5 is connected to the DEMAG signal, the other end is connected to the inverting input end of the operational amplifier, the positive input end of the operational amplifier is grounded, the positive power supply end is connected to the voltage source VCC, and the reverse power supply end is connected to the voltage source -VCC, Both ends of the first capacitor C1 are respectively connected to the output terminal and the inverting input terminal of the operational amplifier;

The drain of the first MOS transistor is connected to the inverting input terminal of the operational amplifier, the source of the first MOS transistor is connected to the output terminal of the operational amplifier, and the gate of the first MOS transistor is connected to the clock signal CLK;

The inverting input terminals of the second comparator and the third comparator are both connected to the output terminal V C1 of the operational amplifier, the non-inverting input terminal of the second comparator is connected to the voltage -V TH , and the Enable connection
The non-inverting input terminal of the third comparator is connected to the voltage -V TL , and the enable terminal of the third comparator is connected to V G-EN ;

The two input ends of the OR gate circuit are respectively connected to the output end of the second comparator and the output end of the third comparator, the output end of the OR gate circuit is connected to the input end of the buffer circuit BUF, and the The output end of the buffer circuit BUF is connected to the signal input end of the D flip-flop, the clock port of the D flip-flop is connected to the clock signal CLK, the output end of the D flip-flop outputs V G-EN , and the V G-EN signal passes through Inverter gets
Signal.
The secondary side synchronous rectification controller of the switching power supply according to claim 7, characterized in that,

The standby judging circuit judges whether the switching power supply is in a heavy-load or light-load state in the current cycle according to the relationship between V C1 and -V TH , -V TL .
A switching power supply, characterized in that the switching power supply comprises: the secondary side synchronous rectification controller of the switching power supply according to any one of claims 1-8.
The switching power supply according to claim 9, wherein the switching power supply is: a flyback converter topology circuit, a forward converter topology circuit, an LLC converter topology circuit, a half-bridge converter topology circuit, a full-bridge conversion converter topology or push-pull converter topology.