CN115700978A - Switching power supply secondary side synchronous rectification controller and switching power supply - Google Patents

Switching power supply secondary side synchronous rectification controller and switching power supply Download PDF

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Publication number
CN115700978A
CN115700978A CN202111145459.7A CN202111145459A CN115700978A CN 115700978 A CN115700978 A CN 115700978A CN 202111145459 A CN202111145459 A CN 202111145459A CN 115700978 A CN115700978 A CN 115700978A
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circuit
comparator
power supply
signal
input end
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张洞田
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Shenzhen Injoinic Technology Co Ltd
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Shenzhen Injoinic Technology Co Ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
    • H02M3/33576—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer
    • H02M3/33592—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The embodiment of the application discloses switching power supply secondary side synchronous rectification controller and switching power supply, synchronous rectification controller includes: the demagnetization detection circuit, the standby judgment circuit, the AND gate circuit and the drive circuit are connected in series; wherein, demagnetization detection circuitry's input is connected switching power supply's synchronous rectification MOS Q2's one end, demagnetization detection circuitry's an output is connected with an input of AND gate, demagnetization detection circuitry's another output with standby judges that the input of circuit is connected, standby judges that the output of circuit with another input of AND gate is connected, the output of AND gate is connected drive circuit's input, drive circuit's output is connected MOS Q2's grid. The technical scheme of this application has the advantage that promotes system efficiency.

Description

Switching power supply secondary side synchronous rectification controller and switching power supply
Technical Field
The application relates to the technical field of switching power supplies, in particular to a secondary side synchronous rectification controller of a switching power supply and the switching power supply.
Background
Along with the continuous increase of the charging power of the mobile terminal, the energy efficiency is more and more emphasized by people, and the energy efficiency standard is continuously improved in various regions of various countries. The application of the synchronous rectification controller replaces the traditional Schottky diode rectification, and the charging efficiency of the adapter and the charger is greatly improved, so that the synchronous rectification controller is more and more widely applied. However, the prior art of the synchronous rectification controller does improve the charging efficiency of the power system during heavy load, but neglects that the synchronous rectification controller consumes power when the power is in no load or light load, which reduces the system efficiency, increases the system standby power consumption, wastes much energy, and increases energy consumption.
Disclosure of Invention
Therefore, in order to solve the problem of high energy consumption in the prior art, the application provides a secondary side synchronous rectification controller of a switching power supply.
The application solves the problems through the following technical means:
the application provides a switching power supply secondary side synchronous rectification controller, synchronous rectification controller includes: the demagnetization detection circuit, the standby judgment circuit, the AND gate circuit and the drive circuit are connected in series; the input end of the demagnetization detection circuit is connected with one end of a synchronous rectification MOS Q2 of the switching power supply, one output end of the demagnetization detection circuit is connected with one input end of an AND gate circuit, the other output end of the demagnetization detection circuit is connected with the input end of a standby judgment circuit, the output end of the standby judgment circuit is connected with the other input end of the AND gate circuit, the output end of the AND gate circuit is connected with the input end of a driving circuit, and the output end of the driving circuit is connected with the grid electrode of the MOS Q2;
the demagnetization detection circuit is used for detecting a voltage difference VDET between a drain electrode and a source electrode of the MOS Q2 and outputting a DEMAG signal through two output ends when the VDET is lower than a set threshold value;
the standby judging circuit is used for integrating the DEMAG signal, comparing the DEMAG signal with a set threshold value to obtain a comparison result, and determining an output signal V according to the comparison result G-EN Whether it is valid;
the AND gate circuit is used forAccording to DEMAG signals and V G-EN Output V gate A signal;
the drive circuit is used for driving the light source according to the V gate And judging whether a VG signal is output to the grid of the MOS Q2 or not by the signal to drive the MOS Q2.
Optionally, the demagnetization detection circuit includes: first comparator, inverter INV, resistor and reference voltage V DET-ref (ii) a Wherein, the first and the second end of the pipe are connected with each other,
the positive phase input end of the first comparator is connected with one end of a first resistor R1, the other end of the first resistor R1 is connected with a VDET, and the negative phase input end of the first comparator is connected with a reference voltage V DET-ref Two ends of the second resistor R2 are respectively connected with a positive phase input end and an output end of the first comparator, and the output end of the first comparator outputs a DEMAG signal through the inverter INV.
Optionally, the standby determining circuit includes: the circuit comprises a current source, an MOS (metal oxide semiconductor) tube, a clock signal CLK, a comparator, a capacitor, an OR gate circuit, a buffer circuit BUF, a D trigger and an inverter; wherein the content of the first and second substances,
the drain electrode of the first MOS tube is connected with a current source I charge The gate of the first MOS tube is connected with a DEMAG signal, the source of the first MOS tube is connected with the drain of the second MOS tube and one end of a capacitor C1, the gate of the second MOS tube is connected with a clock signal CLK, and the source of the second MOS tube and the other end of the capacitor C1 are both grounded;
the positive phase input ends of the second comparator and the third comparator are connected with the source electrode of the first MOS transistor, and the negative phase input end of the second comparator is connected with a voltage V TH The enable terminal of the second comparator is connected
Figure BDA0003285284870000021
The inverting input end of the third comparator is connected with a voltage V TL The enabling end of the third comparator is connected with V G-EN ；
Two input ends of the OR gate circuit are respectively connected with the output end of the second comparator and the output end of the third comparator, the output end of the OR gate circuit is connected with the input end of the buffer circuit BUF, the output end of the buffer circuit BUF is connected with the signal input end of the D trigger, and the clock port of the D trigger is connected with the clock signal CThe output end of LK, D trigger outputs V G-EN ，V G-EN The signal is output through an inverter
Figure BDA0003285284870000022
A signal.
Optionally, the standby judging circuit passes through V C1 And V TH 、V TL The magnitude relation of the voltage and the current time determines whether the switching power supply is in a heavy load state or a light load state in the current period.
Optionally, the standby determining circuit includes: the circuit comprises a resistor, an operational amplifier, an MOS (metal oxide semiconductor) tube, a clock signal CLK, a comparator, a capacitor, an OR gate circuit, a buffer circuit BUF, a D trigger and an inverter; wherein the content of the first and second substances,
one end of a fifth resistor R5 is connected with a DEMAG signal, the other end of the fifth resistor R5 is connected with a positive phase input end of an operational amplifier, an inverting input end of the operational amplifier is connected with a source electrode of a first MOS tube, a drain electrode of the first MOS tube is connected with an output end of the operational amplifier, a positive side power supply end of the operational amplifier is connected with a voltage source VCC, an inverting side power supply end of the operational amplifier is grounded, two ends of a sixth resistor R6 are respectively connected with the inverting input end of the operational amplifier and a reference ground, and two ends of a first capacitor C1 are respectively connected with the output end and the inverting input end of the operational amplifier;
one end of a second capacitor C2 is connected with the positive phase input end of the operational amplifier, the other end of the second capacitor C2 is grounded, the drain electrode of a second MOS tube is connected with the positive phase input end of the operational amplifier, the source electrode of the second MOS tube is grounded, and the grid electrode of the second MOS tube and the grid electrode of the first MOS tube are both connected with a clock signal CLK;
the positive phase input ends of the second comparator and the third comparator are connected with the output end V of the operational amplifier C1 The inverting input end of the second comparator is connected with a voltage V TH The enable terminal of the second comparator is connected
Figure BDA0003285284870000031
The inverting input end of the third comparator is connected with a voltage V TL The enabling end of the third comparator is connected with V G-EN ；
Two input ends of the OR gate circuit are respectively connected with the output end of the second comparator and the output end of the third comparatorThe output end of the OR gate circuit is connected with the input end of the buffer circuit BUF, the output end of the buffer circuit BUF is connected with the signal input end of the D trigger, the clock port of the D trigger is connected with a clock signal CLK, and the output end of the D trigger outputs V G-EN ，V G-EN The signal is obtained by an inverter
Figure BDA0003285284870000032
A signal.
Optionally, the standby judging circuit passes through V C1 And V TH 、V TL The magnitude relation of the voltage and the current time determines whether the switching power supply is in a heavy load state or a light load state in the current period.
Optionally, the standby determining circuit includes: the circuit comprises a resistor, an operational amplifier, an MOS (metal oxide semiconductor) tube, a comparator, a capacitor, an OR gate circuit, a buffer circuit BUF, a D trigger and an inverter; wherein, the first and the second end of the pipe are connected with each other,
one end of the fifth resistor R5 is connected with the DEMAG signal, the other end of the fifth resistor R5 is connected with the inverting input end of the operational amplifier, the positive phase input end of the operational amplifier is grounded, the positive side power supply end is connected with a voltage source VCC, the inverting side power supply end is connected with a voltage source-VCC, and two ends of the first capacitor C1 are respectively connected with the output end and the inverting input end of the operational amplifier;
the drain electrode of the first MOS tube is connected with the inverting input end of the operational amplifier, the source electrode of the first MOS tube is connected with the output end of the operational amplifier, and the grid electrode of the first MOS tube is connected with a clock signal CLK;
the inverting input ends of the second comparator and the third comparator are connected with the output end V of the operational amplifier C1 The positive phase input end of the second comparator is connected with a voltage-V TH The enable terminal of the second comparator is connected
Figure BDA0003285284870000033
The positive phase input end of the third comparator is connected with a voltage-V TL The enabling end of the third comparator is connected with V G-EN ；
Two input ends of the OR gate circuit are respectively connected with the output end of the second comparator and the output end of the third comparator, the output end of the OR gate circuit is connected with the input end of the buffer circuit BUF, and the output end of the buffer circuit BUFThe end of the D flip-flop is connected with the signal input end of the D flip-flop, the clock port of the D flip-flop is connected with a clock signal CLK, and the output end of the D flip-flop outputs V G-EN ，V G-EN The signal is obtained by an inverter
Figure BDA0003285284870000041
A signal.
Optionally, the standby judging circuit passes through V C1 and-V TH 、-V TL The magnitude relation of the voltage and the current time determines whether the switching power supply is in a heavy load state or a light load state in the current period.
The present application further provides a switching power supply, the switching power supply includes: the secondary side synchronous rectification controller of the switching power supply.
Optionally, the switching power supply is: the converter comprises a flyback converter topology circuit, a forward converter topology circuit, an LLC converter topology circuit, a half-bridge converter topology circuit, a full-bridge converter topology circuit or a push-pull converter topology circuit.
The synchronous rectification controller and the standby mode control circuit thereof generate a demagnetization signal DEMAG by detecting the voltage drop at two ends of the synchronous rectification MOS and detecting the fixed time T CLK Internal DEMAG effective time t on Long and short output V G_EN And judging whether to switch the normal working mode and the standby mode. When the synchronous rectification controller enters light load or no load from heavy load, the normal working mode is switched to the standby mode, the power consumption of the synchronous rectification controller can be reduced, and the purpose of improving the system efficiency is achieved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic block diagram of a secondary side synchronous rectification controller of a switching power supply provided by the present application;
FIG. 2 is a schematic diagram of a synchronous rectification controller and its standby mode control provided by the present application;
FIG. 3 is a schematic diagram of a key waveform of the synchronous rectification controller of the present application switching from a normal operation mode to a standby mode when a heavy load enters a light load or a no-load;
FIG. 4 is a schematic diagram of a key waveform for switching from a standby mode to a normal operation mode when a synchronous rectification controller of the present application is under a heavy load or a light load;
fig. 5 is a control flow chart of the synchronous rectification controller proposed in the present application;
FIG. 6 is another control schematic diagram of the synchronous rectification controller and its standby mode proposed in the present application;
fig. 7 is a schematic diagram of another control scheme for the synchronous rectification controller and its standby mode.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, embodiments accompanying figures are described in detail below. It should be noted that the described embodiments are only a part of the embodiments of the present application, and not all embodiments, and all other embodiments obtained by those skilled in the art without any inventive work based on the embodiments in the present application belong to the protection scope of the present application.
Referring to fig. 1, fig. 1 is a schematic block diagram of a secondary side synchronous rectification controller of a switching power supply of the present application, where the switching power supply may be any one of topology circuits such as a flyback converter topology circuit, a forward converter topology circuit, an LLC converter topology circuit, a half-bridge converter topology circuit, a full-bridge converter topology circuit, and a push-pull converter topology circuit, and referring to fig. 1, the synchronous rectification controller includes: demagnetization detection circuit, standby judgment circuit, AND gate, drive circuit. Wherein, demagnetization detection circuitry's input is connected switching power supply's synchronous rectification MOS Q2's one end, demagnetization detection circuitry's an output and an and gate circuit's an input are connected, demagnetization detection circuitry's another output with standby judges that the input of circuit is connected, standby judges that the output of circuit with another input of and gate circuit is connected, and gate circuit's output is connected drive circuit's input, drive circuit's output is connected MOS Q2's grid.
And the demagnetization detection circuit is used for detecting the voltage difference VDET between the drain electrode and the source electrode of the MOS Q2, and outputting a DEMAG signal through two output ends when the VDET is lower than a set threshold value.
The standby judging circuit is used for integrating the DEMAG signal, comparing the DEMAG signal with a set threshold value to obtain a comparison result, and determining an output channel V according to the comparison result G-EN Whether it is valid.
The AND gate circuit is used for generating a DEMAG signal according to the DEMAG signal and the V G-EN Output V gate A signal.
The drive circuit is used for driving the drive circuit according to the V gate And judging whether a VG signal is output to the grid of the MOS Q2 or not by the signal to drive the MOS Q2.
The synchronous rectification controller provided by the application has two working modes: a normal operating mode and a standby mode. The demagnetization detection circuit samples Vds at two ends of the synchronous rectification MOS Q2 through a VDET pin, and when the Vds is lower than a set threshold value, a DEMAG signal is given. The standby judging circuit judges whether the current power supply system is in a light load or a no-load state by comparing the integral DEMAG signal with a set threshold value, so as to judge whether the synchronous rectification controller enters a standby mode or not and give out an enabling driving output signal V or not G_EN 。V G_EN And the DEMAG outputs Vgate through an AND gate. The driving circuit strengthens the driving capability on the basis of the Vgate signal and outputs a VG signal to drive the synchronous rectification MOS Q2.
Fig. 2 is a schematic diagram of a first synchronous rectification controller and a standby mode control thereof, which is provided in the present application, and further details of the synchronous rectification controller in fig. 1 are described. The detailed demagnetization detection circuit principle and the standby judgment circuit principle are given in fig. 2. The method specifically comprises the following steps: the demagnetization detection circuit includes: first comparator, inverter INV, resistor and reference voltage V DET-ref (ii) a Wherein the positive phase input end of the first comparator is connected withOne end of a first resistor R1 is connected, the other end of the first resistor R1 is connected with a VDET, and the inverting input end of the first comparator is connected with a reference voltage V DET-ref Two ends of the second resistor R2 are respectively connected with a positive phase input end and an output end of the first comparator, and the output end of the first comparator outputs a DEMAG signal through the inverter INV.
The standby judging circuit includes: the circuit comprises a current source, an MOS (metal oxide semiconductor) tube, a clock signal CLK, a comparator, a capacitor, an OR gate circuit, a buffer circuit BUF, a D trigger and an inverter; wherein the drain electrode of the first MOS tube is connected with a current source I charge The gate of the first MOS tube is connected with a DEMAG signal, the source of the first MOS tube is connected with the drain of the second MOS tube and one end of a capacitor C1, the gate of the second MOS tube is connected with a clock signal CLK, and the source of the second MOS tube and the other end of the capacitor C1 are both grounded; the positive phase input ends of the second comparator and the third comparator are connected with the source electrode of the first MOS transistor, and the negative phase input end of the second comparator is connected with a voltage V TH The enable terminal of the second comparator is connected
Figure BDA0003285284870000061
The inverting input end of the third comparator is connected with a voltage V TL The enabling end of the third comparator is connected with V G-EN ；
Two input ends of the OR gate circuit are respectively connected with the output end of the second comparator and the output end of the third comparator, the output end of the OR gate circuit is connected with the input end of the buffer circuit BUF, the output end of the buffer circuit BUF is connected with the signal input end of the D trigger, the clock port of the D trigger is connected with a clock signal CLK, and the output end of the D trigger outputs V G-EN ，V G-EN The signal is output through an inverter
Figure BDA0003285284870000062
A signal.
The demagnetization detection circuit shown in fig. 2 comprises R1, R2, comparator 1 and reference voltage V DET_ref . When the voltage of the sampled VDET rapidly drops below
Figure BDA0003285284870000063
(for example, set at about-85 mV) In the meantime, the output of the comparator 1 is low, and the DEMAG high level is output after passing through the inverter INV, indicating that the start of demagnetization is detected. When the voltage of the sampled VDET gradually rises and is higher than the voltage of the sampled VDET
Figure BDA0003285284870000071
When the voltage is set to about-5 mV, the comparator 1 outputs a high level, and outputs a DEMAG low level after passing through the inverter INV, which indicates that demagnetization is completed.
Fig. 2 also shows the principle of a standby judging circuit, and in the demagnetization process, namely when the DEMAG is at a high level, the DEMAG signal drives the MOS Q1 to be turned on, and the current source I is turned on charge Charging capacitor C1, V C1 The rising level is:
Figure BDA0003285284870000072
wherein t is ON The duration when DEMAG is high. When DEMAG is low level, namely not in demagnetization time, MOS Q1 is closed, and V C1 Remain unchanged. The above process is repeated once for each VDET pulse, thereby realizing V C1 The voltage rise accumulates during each DEMAG high. By detecting at a given time T CLK Inner V C1 Voltage and set threshold V TL /V TH The magnitude relation of the voltage and the current can judge the heavy load or light load state of the switching power supply in the current period, and then the synchronous rectifier is controlled to enter a normal working mode or a standby mode. T herein CLK And V TL /V TH The method can be set, and different standby mode trigger thresholds can be conveniently set in different applications.
The standby judging circuit has 4 situations: 1. from normal operating mode into standby mode, i.e. V G_EN The high level of the current period is converted into the low level of the next CLK period; 2. maintaining normal operating mode, i.e. maintaining current V for next CLK cycle G_EN Is at a high level; 3. from standby mode back to normal operating mode, i.e. V G_EN Changing from the low level of the current period to the high level of the next CLK period; 4. maintaining standby mode, i.e. maintaining current V for the next CLK cycle G_EN Is low.
The above-described cases 1 and 2All occur at the current V G_EN When the level is high, i.e. the synchronous rectification controller is in normal operation mode, the comparator 3 enables the signal V G_EN Is high, outputs an active level, comparator 2 enables signal
Figure BDA0003285284870000073
Low, the output is always low. When the rising edge of the next CLK comes, if V C1 >V TL If the output of the comparator 3 is high level, after the delay of the OR gate and the BUF, the VD signal is high level, and the D trigger outputs V G_EN The standby state is maintained at high level, which is the 2 nd condition of the standby judging circuit: the synchronous rectification controller keeps a normal working mode. When the rising edge of the next CLK comes, if V C1 ≤V TL Then the output of the comparator 3 is low level and the comparator 2 is enabled by the enable signal
Figure BDA0003285284870000074
The output is always low level when the voltage is low, the VD signal is low level after the time delay of an OR gate and a BUF, and the D trigger outputs V G_EN The high level is changed into the low level, which is the condition 1 of the standby judging circuit: and the synchronous rectification controller enters a standby mode from a normal working mode.
The above-mentioned cases 3 and 4 occur at the current V G_EN When the level is low, i.e. when the synchronous rectification controller is in standby mode, the comparator 3 enables the signal V G_EN Is low, the output is always low, the comparator 2 enables the signal
Figure BDA0003285284870000081
Is high, an active level is output. When the rising edge of the next CLK comes, if V C1 >V TH If the output of the comparator 2 is high level, after the delay of the OR gate and the BUF, the VD signal is high level, and the D trigger outputs V G_EN The low level is changed into the high level, which is the 3 rd condition of the standby judging circuit: the synchronous rectification controller is recovered to a normal working mode from a standby mode. If the next rising edge of CLK comes, V C1 ≤V TH Then compareThe output of the comparator 2 is low level, and the comparator 3 enables the signal V G_EN The output is always low level when the voltage is low, the VD signal is low level after the time delay of an OR gate and a BUF, and the D trigger outputs V G_EN Remains low, which is the 4 th condition of the standby determining circuit: the synchronous rectification controller maintains a standby mode.
Output signal V of standby judging circuit G_EN The demagnetization signal DEMAG is input into an AND gate (AND) together, AND the AND gate outputs V gate To the drive circuit. The driving circuit strengthens the driving capability and outputs a sum V gate The synchronous signal VG is sent to the grid of the synchronous rectification MOS Q2 to control the switch of the synchronous rectification MOS. The above is the basic principle for realizing the synchronous rectification controller and the standby mode control thereof.
Fig. 3 is a schematic diagram of a key waveform of the synchronous rectification controller switching from a normal operation mode to a standby mode when a heavy load enters a light load or a no-load state. At the beginning of the time, t =0, clk sends a pulse signal which, at high level, opens MOS Q2, discharging the C1 capacitor, V C1 Very fast discharge zero clearing, e.g. V in FIG. 3 C1 Shown in waveform. After the CLK pulse, every time the VDET rapidly falls and satisfies "VDET < V DET_ref_L When "time, the demagnetization signal DEMAG becomes high level, and V G_EN Output V via AND gate gate Is high. Meanwhile, a demagnetization signal DEMAG high level drives the MOS Q1 to be opened, the C1 capacitor is charged, and V is C1 The rising level is:
Figure BDA0003285284870000082
wherein t is ON DEMAG is high duration. When DEMAG is low, namely not in the demagnetization time, MOS Q1 is closed, and VC1 is kept unchanged. The above process is repeated once for each VDET pulse, thereby realizing V C1 The voltage rise accumulates during each DEMAG high. Until the next rising edge of CLK comes, V C1 The accumulated rise does not exceed V TL D flip-flop output V G_EN The synchronous rectification controller is switched from a high level to a low level and is kept at the low level before the next CLK comes, so that the synchronous rectification controller is switched from a normal working mode to a standby mode。
Fig. 4 is a schematic diagram of a key waveform for switching from a standby mode to a normal operation mode when the synchronous rectification controller of the present application is under a heavy load from a light load or no load. At the beginning of the time, t =0, clk sends a pulse signal which, at high level, opens MOS Q2, discharging the C1 capacitor, V C1 Very fast discharge clearing, e.g. V in the figure C1 Shown in waveform. After the CLK pulse, every time the VDET rapidly falls and satisfies "VDET < V DET_ref_L When the demagnetization signal DEMAG is changed into high level, the MOS Q1 is driven to be opened to charge the C1 capacitor, and V C1 The rising level is:
Figure BDA0003285284870000091
wherein t is ON DEMAG is high duration. When DEMAG is low level, namely not in demagnetization time, MOS Q1 is closed, and V C1 Remain unchanged. The above process is repeated once for each VDET pulse, thereby realizing V C1 The voltage rise accumulates during each DEMAG high. Until the next rising edge of CLK comes, V C1 Accumulated and rises and satisfies V C1 >V TH D flip-flop output V G_EN And the synchronous rectification controller is switched from a low level to a high level and is kept at the high level before the next CLK comes, so that the synchronous rectification controller is switched from a standby mode to a normal working mode.
Fig. 5 is a control flow chart of the synchronous rectification controller proposed in the present application. The specific implementation circuit and implementation principle of the flow chart follow the block diagram of the synchronous rectification controller in fig. 1 and the synchronous rectification controller and the standby mode control principle thereof proposed in fig. 2. The detailed control flow comprises the following steps:
step 1: starting;
and 2, step: power-on reset, initializing a sampling module, initializing logic circuits of each part, and defaulting VG to be a low level;
and step 3: enter normal mode, CLK pulses, V C1 Zero clearing, V G_EN Enabling VG to normally output;
and 4, step 4: VDET detects demagnetization time, and C1 is charged in the demagnetization time;
and 5: t is CLK When the timing is over and the next CLK pulse rises, judging V C1 Whether or not less than V TL . If yes, executing step 6; if not, executing step 3;
step 6: enter a standby mode, CLK pulses, V C1 Zero clearing, V G_EN Not enabled, VG has no output;
and 7: VDET detects demagnetization time, and C1 is charged in the demagnetization time;
and 8: t is CLK When the timing is over and the next CLK pulse rises, judging V C1 Whether or not it is greater than V TH . If yes, executing step 3; if not, step 6 is performed.
Fig. 6 is another control schematic diagram of the synchronous rectification controller and the standby mode thereof according to the present application, and the demagnetization detection circuit is the same as the first synchronous rectification controller and the standby mode control schematic diagram thereof according to fig. 2, except that the standby determination circuit in fig. 2 adopts DEMAG to control I charge Charging capacitor C1 to realize
Figure BDA0003285284870000101
I.e. V C1 And t on Proportional linear function relationship. The standby determination circuit shown in fig. 6 includes: the circuit comprises a resistor, an operational amplifier, an MOS (metal oxide semiconductor) tube, a clock signal CLK, a comparator, a capacitor, an OR gate circuit, a buffer circuit BUF, a D trigger and an inverter; one end of a fifth resistor R5 is connected with a DEMAG signal, the other end of the fifth resistor R5 is connected with a positive phase input end of an operational amplifier, an inverse phase input end of the operational amplifier is connected with a source electrode of a first MOS tube, a drain electrode of the first MOS tube is connected with an output end of the operational amplifier, a positive side power supply end of the operational amplifier is connected with a voltage source VCC, an inverse side power supply end of the operational amplifier is grounded, two ends of a sixth resistor R6 are respectively connected with the inverse phase input end of the operational amplifier and a reference ground, and two ends of a first capacitor C1 are respectively connected with the output end and the inverse phase input end of the operational amplifier; one end of a second capacitor C2 is connected with the positive phase input end of the operational amplifier, the other end of the second capacitor C2 is grounded, the drain electrode of a second MOS tube is connected with the positive phase input end of the operational amplifier, the source electrode of the second MOS tube is grounded, the grid electrode of the second MOS tube and the grid electrode of the first MOS tube are groundedThe poles are all connected with a clock signal CLK; the positive phase input ends of the second comparator and the third comparator are connected with the output end V of the operational amplifier C1 The inverting input end of the second comparator is connected with a voltage V TH The enable terminal of the second comparator is connected
Figure BDA0003285284870000102
The inverting input end of the third comparator is connected with a voltage V TL The enabling end of the third comparator is connected with V G-EN (ii) a Two input ends of the OR gate circuit are respectively connected with the output end of the second comparator and the output end of the third comparator, the output end of the OR gate circuit is connected with the input end of the buffer circuit BUF, the output end of the buffer circuit BUF is connected with the signal input end of the D trigger, the clock port of the D trigger is connected with a clock signal CLK, and the output end of the D trigger outputs V G-EN ，V G-EN The signal is obtained by an inverter
Figure BDA0003285284870000103
A signal.
As shown in fig. 6, the standby determination circuit in fig. 6 is replaced with an operational amplifier, and a positive phase integration circuit composed of R5, C2, Q2, R6, C1, and Q1, and if R5 × C2= R6 × C1, there is a circuit that has a positive phase integration circuit
Figure BDA0003285284870000111
Also realize V C1 And t on Proportional linear function relationship, where V DEMAG The voltage value is the high-level DEMAG voltage value. When taking a value
Figure BDA0003285284870000112
Meanwhile, the second synchronous rectification controller and the standby mode control schematic diagram thereof proposed in the present application can implement the same functions as the first synchronous rectification controller and the standby mode control schematic diagram thereof, and the key waveforms refer to fig. 3 and 4.
Fig. 7 is another control schematic diagram of the synchronous rectification controller and its standby mode proposed in the present application, and the demagnetization detection circuit is the same as the control schematic diagrams of the synchronous rectification controller and its standby mode proposed in fig. 2 and 6, as shown in fig. 7The standby judging circuit comprises: the circuit comprises a resistor, an operational amplifier, an MOS (metal oxide semiconductor) tube, a comparator, a capacitor, an OR gate circuit, a buffer circuit BUF, a D trigger and an inverter; one end of the fifth resistor R5 is connected with the DEMAG signal, the other end of the fifth resistor R5 is connected with the inverting input end of the operational amplifier, the positive phase input end of the operational amplifier is grounded, the positive side power supply end is connected with a voltage source VCC, the inverting side power supply end is connected with a voltage source-VCC, and two ends of the first capacitor C1 are respectively connected with the output end and the inverting input end of the operational amplifier; the drain electrode of the first MOS tube is connected with the inverting input end of the operational amplifier, the source electrode of the first MOS tube is connected with the output end of the operational amplifier, and the grid electrode of the first MOS tube is connected with a clock signal CLK; the inverting input ends of the second comparator and the third comparator are connected with the output end V of the operational amplifier C1 The positive phase input end of the second comparator is connected with a voltage-V TH The enable terminal of the second comparator is connected
Figure BDA0003285284870000113
The positive phase input end of the third comparator is connected with a voltage-V TL The enabling end of the third comparator is connected with V G-EN (ii) a Two input ends of the OR gate circuit are respectively connected with the output end of the second comparator and the output end of the third comparator, the output end of the OR gate circuit is connected with the input end of the buffer circuit BUF, the output end of the buffer circuit BUF is connected with the signal input end of the D trigger, the clock port of the D trigger is connected with the clock signal CLK, and the output end of the D trigger outputs V G-EN ，V G-EN The signal is obtained by an inverter
Figure BDA0003285284870000114
A signal.
Referring to fig. 7, the difference is that the standby determination circuit in fig. 2 adopts DEMAG control I charge Charging capacitor C1 to realize
Figure BDA0003285284870000115
I.e. V C1 And t on Proportional linear function relationship; fig. 7 is replaced by an operational amplifier, a positive phase integrating circuit composed of R5, C2, Q2, R6, C1 and Q1, and if R5 × C2= R6 × C1, then there is
Figure BDA0003285284870000116
Also realize V C1 And t on Proportional linear function relationship, where V DEMAG The voltage value is the high-level DEMAG voltage value. The inverse integration circuit composed of the operational amplifier, R5, C1 and Q1 is adopted in the place of FIG. 7, and then
Figure BDA0003285284870000121
Realization of V C1 And t on In a negative correlation of first order functional relationship, where V DEMAG The voltage value is the high-level DEMAG voltage value. Since VC1 output by the inverting integrator is a negative value, the input conditions of the comparator 2 and the comparator 3 need to be adjusted accordingly: input reference value is composed of V TL /V TH Changed to (-V) TL )/(-V TH ) While setting the input reference value to the comparator positive input, V C1 Is the negative terminal input. The rest of the standby determination circuit is identical to fig. 2 and 6, and the same function is achieved.
In summary, the synchronous rectification controller and the standby mode control circuit thereof provided by the present application generate the demagnetization signal DEMAG by detecting the voltage drop across the synchronous rectification MOS and detecting the fixed time T CLK Internal DEMAG effective time t on Long and short output V G_EN And judging whether to switch the normal working mode and the standby mode. When the synchronous rectification controller enters light load or no load from a heavy load, the synchronous rectification controller is switched to a standby mode from a normal working mode, so that the power consumption of the synchronous rectification controller can be reduced, and the purpose of improving the system efficiency is achieved.
The present application provides three representative synchronous rectification controllers and their standby mode control circuits, which are merely preferred embodiments and not intended to limit the present application, and it will be apparent to those skilled in the art that various modifications and variations can be made in the present application. It should be understood that the present invention is not limited to the particular embodiments disclosed, but is intended to cover modifications, variations, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

Claims (5)

1. A secondary side synchronous rectification controller of a switching power supply, the synchronous rectification controller comprising: the demagnetization detection circuit, the standby judgment circuit, the AND gate circuit and the drive circuit are connected in series; the input end of the demagnetization detection circuit is connected with one end of a synchronous rectification MOS Q2 of the switching power supply, one output end of the demagnetization detection circuit is connected with one input end of an AND gate circuit, the other output end of the demagnetization detection circuit is connected with the input end of a standby judgment circuit, the output end of the standby judgment circuit is connected with the other input end of the AND gate circuit, the output end of the AND gate circuit is connected with the input end of the driving circuit, and the output end of the driving circuit is connected with a grid electrode of the MOS Q2;
the demagnetization detection circuit is used for detecting a voltage difference VDET between a drain electrode and a source electrode of the MOS Q2 and outputting a DEMAG signal through two output ends when the VDET is lower than a set threshold value;
the standby judging circuit is used for integrating the DEMAG signal, comparing the DEMAG signal with a set threshold value to obtain a comparison result, and determining an output signal V according to the comparison result G-EN Whether it is valid;
the AND gate circuit is used for generating the DEMAG signal according to the DEMAG signal and the V G-EN Output V gate A signal;
the drive circuit is used for driving the drive circuit according to the V gate Judging whether a VG signal is output to the grid of the MOS Q2 or not by the signal to drive the MOS Q2;
the standby judging circuit includes: the circuit comprises a resistor, an operational amplifier, an MOS (metal oxide semiconductor) tube, a clock signal CLK, a comparator, a capacitor, an OR gate circuit, a buffer circuit BUF, a D trigger and an inverter; wherein, the first and the second end of the pipe are connected with each other,
one end of a fifth resistor R5 is connected with the DEMAG signal, the other end of the fifth resistor R5 is connected with the positive phase input end of the operational amplifier, the negative phase input end of the operational amplifier is connected with the source electrode of a first MOS tube, the drain electrode of the first MOS tube is connected with the output end of the operational amplifier, the positive side power supply end of the operational amplifier is connected with a voltage source VCC, the negative side power supply end is grounded, the two ends of a sixth resistor R6 are respectively connected with the negative phase input end and a reference ground of the operational amplifier, and the two ends of a first capacitor C1 are respectively connected with the output end and the negative phase input end of the operational amplifier;
one end of a second capacitor C2 is connected with the positive phase input end of the operational amplifier, the other end of the second capacitor C2 is grounded, the drain electrode of a second MOS tube is connected with the positive phase input end of the operational amplifier, the source electrode of the second MOS tube is grounded, and the grid electrode of the second MOS tube and the grid electrode of the first MOS tube are both connected with a clock signal CLK;
the positive phase input ends of the second comparator and the third comparator are connected with the output end V of the operational amplifier C1 The inverting input end of the second comparator is connected with a voltage V TH The enable terminal of the second comparator is connected
Figure FDA0003285284860000011
The inverting input end of the third comparator is connected with a voltage V TL The enabling end of the third comparator is connected with V G-EN ；
The two input ends of the OR gate circuit are respectively connected with the output end of the second comparator and the output end of the third comparator, the output end of the OR gate circuit is connected with the input end of the buffer circuit BUF, the output end of the buffer circuit BUF is connected with the signal input end of the D trigger, the clock port of the D trigger is connected with the clock signal CLK, and the output end of the D trigger outputs V G-EN ，V G-EN The signal is obtained by an inverter
Figure FDA0003285284860000021
A signal.
2. The secondary side synchronous rectification controller of the switching power supply according to claim 1, wherein the demagnetization detection circuit includes: first comparator, inverter INV, resistor and reference voltage V DET-ref (ii) a Wherein the content of the first and second substances,
a positive phase input end of the first comparator is connected with one end of a first resistor R1, the other end of the first resistor R1 is connected with the VDET, and an inverted phase input end of the first comparator is connected with a reference voltage V DET-ref Two ends of the second resistor R2 are respectively connected with theThe output end of the first comparator outputs a DEMAG signal through an inverter INV.
3. The secondary side synchronous rectification controller of the switching power supply as claimed in claim 1,
the standby judging circuit passes V C1 And V TH 、V TL The magnitude relation of the voltage and the current time determines whether the switching power supply is in a heavy load state or a light load state in the current period.
4. A switching power supply, characterized in that it comprises: a secondary side synchronous rectification controller of a switching power supply as claimed in any one of claims 1 to 3.
5. The switching power supply according to claim 4, wherein the switching power supply is: the converter comprises a flyback converter topology circuit, a forward converter topology circuit, an LLC converter topology circuit, a half-bridge converter topology circuit, a full-bridge converter topology circuit or a push-pull converter topology circuit.
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