WO2023005758A1 - Dispositif de commande de redresseur synchrone côté secondaire de bloc d'alimentation à découpage, et bloc d'alimentation à découpage - Google Patents

Dispositif de commande de redresseur synchrone côté secondaire de bloc d'alimentation à découpage, et bloc d'alimentation à découpage Download PDF

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WO2023005758A1
WO2023005758A1 PCT/CN2022/106694 CN2022106694W WO2023005758A1 WO 2023005758 A1 WO2023005758 A1 WO 2023005758A1 CN 2022106694 W CN2022106694 W CN 2022106694W WO 2023005758 A1 WO2023005758 A1 WO 2023005758A1
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Prior art keywords
comparator
circuit
power supply
output
gate
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PCT/CN2022/106694
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English (en)
Chinese (zh)
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张洞田
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深圳英集芯科技股份有限公司
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Publication of WO2023005758A1 publication Critical patent/WO2023005758A1/fr

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
    • H02M3/33576—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer
    • H02M3/33592—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • This application relates to the technical field of switching power supplies, in particular to a secondary-side synchronous rectification controller of a switching power supply and a switching power supply.
  • the application of the synchronous rectification controller replaces the traditional Schottky diode rectification, which greatly improves the charging efficiency of the adapter and charger, so it is more and more widely used.
  • the prior art of the synchronous rectification controller does improve the charging efficiency of the power system under heavy load, but it ignores that the power consumption of the synchronous rectification controller itself reduces the system efficiency when the power supply is no-load or light-load, and increases the The standby power consumption of the system wastes a lot of energy and increases energy consumption.
  • the present application proposes a secondary-side synchronous rectification controller of a switching power supply.
  • the present application provides a synchronous rectification controller on the secondary side of a switching power supply.
  • the synchronous rectification controller includes: a demagnetization detection circuit, a standby judgment circuit, an AND gate circuit, and a drive circuit; wherein, the input terminal of the demagnetization detection circuit is connected to the One end of the synchronous rectification MOS Q2 of the switching power supply, one output end of the demagnetization detection circuit is connected with an input end of the AND gate circuit, and the other output end of the demagnetization detection circuit is connected with the input end of the standby judgment circuit , the output end of the standby judgment circuit is connected to the other input end of the AND gate circuit, the output end of the AND gate circuit is connected to the input end of the driving circuit, and the output end of the driving circuit is connected to the MOS Gate of Q2;
  • the demagnetization detection circuit is used to detect the voltage difference VDET between the drain and the source of the MOS Q2, and output the DEMAG signal through two output terminals when the VDET is lower than the set threshold;
  • the standby judging circuit is used to integrate the DEMAG signal and compare it with a set threshold to obtain a comparison result, and determine whether the output signal V G-EN is valid according to the comparison result;
  • the AND gate circuit is used to output the V gate signal according to the DEMAG signal and V G-EN ;
  • the driving circuit is configured to judge whether to output a VG signal to the gate of the MOS Q2 to drive the MOS Q2 according to the V gate signal.
  • the demagnetization detection circuit includes: a first comparator, an inverter INV, a resistor, and a reference voltage V DET-ref ; wherein,
  • the non-inverting input end of the first comparator is connected to one end of the first resistor R1, the other end of the first resistor R1 is connected to VDET, the inverting input end of the first comparator is connected to the reference voltage V DET-ref , and the two ends of the second resistor R2 terminals are respectively connected to the non-inverting input terminal and the output terminal of the first comparator, and the output terminal of the first comparator outputs the DEMAG signal through the inverter INV.
  • the standby judgment circuit includes: a current source, a MOS transistor, a clock signal CLK, a comparator, a capacitor, an OR gate circuit, a buffer circuit BUF, a D flip-flop, and an inverter; wherein,
  • the drain of the first MOS transistor is connected to the current source I charge , the gate of the first MOS transistor is connected to the DEMAG signal, the source of the first MOS transistor is connected to the drain of the second MOS transistor and one end of the capacitor C1, and the gate of the second MOS transistor
  • the pole is connected to the clock signal CLK, the source of the second MOS transistor and the other end of the capacitor C1 are grounded;
  • Both the non-inverting input terminals of the second comparator and the third comparator are connected to the source of the first MOS transistor, the inverting input terminal of the second comparator is connected to the voltage V TH , and the enabling terminal of the second comparator is connected to The inverting input terminal of the third comparator is connected to the voltage V TL , and the enable terminal of the third comparator is connected to V G-EN ;
  • the two input ends of the OR gate circuit are respectively connected to the output end of the second comparator and the output end of the third comparator, the output end of the OR gate circuit is connected to the input end of the buffer circuit BUF, and the output end of the buffer circuit BUF is connected to the D flip-flop
  • the signal input terminal of the D flip-flop is connected to the clock signal CLK, the output terminal of the D flip-flop outputs V G-EN , and the V G-EN signal is output through the inverter Signal.
  • the standby judging circuit judges whether the switching power supply is in a heavy-load or light-load state in the current cycle according to the relationship between V C1 and V TH , V TL .
  • the standby judging circuit includes: a resistor, an operational amplifier, a MOS transistor, a clock signal CLK, a comparator, a capacitor, an OR gate circuit, a buffer circuit BUF, a D flip-flop, and an inverter; wherein,
  • One end of the fifth resistor R5 is connected to the DEMAG signal, the other end is connected to the non-inverting input of the operational amplifier, the inverting input of the operational amplifier is connected to the source of the first MOS transistor, and the drain of the first MOS transistor is connected to the output of the operational amplifier.
  • the power supply terminal on the positive side of the amplifier is connected to the voltage source VCC, and the power supply terminal on the opposite side is grounded. input terminal;
  • One end of the second capacitor C2 is connected to the non-inverting input terminal of the operational amplifier, the other end of the second capacitor C2 is grounded, the drain of the second MOS transistor is connected to the non-inverting input terminal of the operational amplifier, and the source of the second MOS transistor is grounded. Both the gate of the second MOS transistor and the gate of the first MOS transistor are connected to the clock signal CLK;
  • the noninverting input terminals of the second comparator and the third comparator are connected to the output terminal V C1 of the operational amplifier, the inverting input terminal of the second comparator is connected to the voltage V TH , and the enable terminal of the second comparator is connected to The inverting input terminal of the third comparator is connected to the voltage V TL , and the enable terminal of the third comparator is connected to V G-EN ;
  • the two input ends of the OR gate circuit are respectively connected to the output end of the second comparator and the output end of the third comparator, the output end of the OR gate circuit is connected to the input end of the buffer circuit BUF, and the output end of the buffer circuit BUF is connected to the D flip-flop
  • the signal input terminal of the D flip-flop is connected to the clock signal CLK, the output terminal of the D flip-flop outputs V G-EN , and the V G-EN signal is obtained through the inverter Signal.
  • the standby judging circuit judges whether the switching power supply is in a heavy-load or light-load state in the current cycle according to the relationship between V C1 and V TH , V TL .
  • the standby judging circuit includes: a resistor, an operational amplifier, a MOS tube, a comparator, a capacitor, an OR gate circuit, a buffer circuit BUF, a D flip-flop, and an inverter; wherein,
  • One end of the fifth resistor R5 is connected to the DEMAG signal, the other end is connected to the inverting input terminal of the operational amplifier, the positive input terminal of the operational amplifier is grounded, the positive side power supply terminal is connected to the voltage source VCC, the reverse side power supply terminal is connected to the voltage source -VCC, and the first capacitor C1 The two ends are respectively connected to the output terminal and the inverting input terminal of the operational amplifier;
  • the drain of the first MOS transistor is connected to the inverting input terminal of the operational amplifier, the source of the first MOS transistor is connected to the output terminal of the operational amplifier, and the gate of the first MOS transistor is connected to the clock signal CLK;
  • the inverting input terminals of the second comparator and the third comparator are both connected to the output terminal V C1 of the operational amplifier, the non-inverting input terminal of the second comparator is connected to the voltage -V TH , and the enabling terminal of the second comparator is connected to The positive phase input terminal of the third comparator is connected to the voltage -V TL , and the enable terminal of the third comparator is connected to V G-EN ;
  • the two input ends of the OR gate circuit are respectively connected to the output end of the second comparator and the output end of the third comparator, the output end of the OR gate circuit is connected to the input end of the buffer circuit BUF, and the output end of the buffer circuit BUF is connected to the D flip-flop
  • the signal input terminal of the D flip-flop is connected to the clock signal CLK, the output terminal of the D flip-flop outputs V G-EN , and the V G-EN signal is obtained through the inverter Signal.
  • the standby judging circuit judges whether the switching power supply is in a heavy-load or light-load state in the current cycle according to the relationship between V C1 and -V TH , -V TL .
  • the present application also provides a switching power supply, which includes: the above-mentioned secondary-side synchronous rectification controller of the switching power supply.
  • the switching power supply is: a flyback converter topology circuit, a forward converter topology circuit, an LLC converter topology circuit, a half-bridge converter topology circuit, a full-bridge converter topology circuit or a push-pull converter topology circuit .
  • the synchronous rectification controller and its standby mode control circuit proposed in this application generate a demagnetization signal DEMAG by detecting the voltage drop at both ends of the synchronous rectification MOS, and output V G_EN by detecting the length of the effective time t on of DEMAG within a fixed time T CLK to determine whether Switch between normal working mode and standby mode.
  • a demagnetization signal DEMAG by detecting the voltage drop at both ends of the synchronous rectification MOS
  • V G_EN by detecting the length of the effective time t on of DEMAG within a fixed time T CLK to determine whether Switch between normal working mode and standby mode.
  • Fig. 1 is a schematic block diagram of a secondary side synchronous rectification controller of a switching power supply provided by the present application;
  • Fig. 2 is the schematic diagram of the synchronous rectification controller and its standby mode control provided by the present application;
  • Fig. 3 is a schematic diagram of key waveforms when the synchronous rectification controller of the present application is switched from a heavy load to a light load or no load, and the normal working mode is switched to the standby mode;
  • Fig. 4 is a schematic diagram of key waveforms of switching from standby mode to normal working mode when the synchronous rectification controller of the present application enters heavy load from light load or no load;
  • Fig. 5 is the control flowchart of the synchronous rectification controller that the present application proposes
  • Fig. 6 is another control schematic diagram of the synchronous rectification controller and its standby mode proposed by the present application.
  • Fig. 7 is another control schematic diagram of the synchronous rectification controller and its standby mode proposed in the present application.
  • Fig. 1 is a schematic block diagram of the secondary side synchronous rectification controller of the switching power supply of the present application, wherein the switching power supply can be a flyback converter topology circuit, a forward converter topology circuit, an LLC converter topology circuit, a half-bridge Any one of topological circuits such as converter topological circuit, full-bridge converter topological circuit, push-pull converter topological circuit, etc., refer to Figure 1, the synchronous rectification controller includes: demagnetization detection circuit, standby judgment circuit, AND gate, drive circuit .
  • the input end of the demagnetization detection circuit is connected to one end of the synchronous rectification MOS Q2 of the switching power supply, one output end of the demagnetization detection circuit is connected to an input end of the AND gate circuit, and the other end of the demagnetization detection circuit
  • the output end is connected to the input end of the standby judgment circuit, the output end of the standby judgment circuit is connected to the other input end of the AND gate circuit, and the output end of the AND gate circuit is connected to the input end of the drive circuit , the output end of the drive circuit is connected to the gate of the MOS Q2.
  • the demagnetization detection circuit is used to detect the voltage difference VDET between the drain and the source of the MOS Q2, and output a DEMAG signal through two output terminals when the VDET is lower than a set threshold.
  • the standby judging circuit is used to integrate the DEMAG signal and compare it with a set threshold to obtain a comparison result, and determine whether the output channel V G-EN is valid according to the comparison result.
  • the AND gate circuit is used to output the V gate signal according to the DEMAG signal and V G-EN .
  • the driving circuit is configured to judge whether to output a VG signal to the gate of the MOS Q2 to drive the MOS Q2 according to the V gate signal.
  • the synchronous rectification controller proposed in this application has two working modes: normal working mode and standby mode.
  • the demagnetization detection circuit samples the Vds at both ends of the synchronous rectification MOS Q2 through the VDET pin, and gives a DEMAG signal when the Vds is lower than the set threshold.
  • the standby judging circuit compares the integrated DEMAG signal with the set threshold to judge whether the current power system is under light load or no load, thereby judging whether the synchronous rectifier controller enters the standby mode, and gives whether to enable the drive output signal V G_EN .
  • V G_EN and DEMAG pass through the AND gate to output Vgate. Based on the Vgate signal, the driving circuit strengthens the driving capability, and outputs the VG signal to drive the synchronous rectification MOS Q2.
  • FIG. 2 is a schematic diagram of the first synchronous rectification controller proposed in the present application and its standby mode control, which is a further detailed description of the synchronous rectification controller in FIG. 1 .
  • Figure 2 shows the detailed demagnetization detection circuit principle and standby judgment circuit principle.
  • the demagnetization detection circuit includes: a first comparator, an inverter INV, a resistor, and a reference voltage V DET-ref ; wherein, the positive phase input terminal of the first comparator is connected to one end of the first resistor R1, and the first resistor The other end of R1 is connected to VDET, the inverting input end of the first comparator is connected to the reference voltage V DET-ref , and the two ends of the second resistor R2 are respectively connected to the non-inverting input end and output end of the first comparator.
  • the output terminal of the comparator outputs the DEMAG signal through the inverter INV.
  • the standby judgment circuit includes: a current source, a MOS tube, a clock signal CLK, a comparator, a capacitor, an OR gate circuit, a buffer circuit BUF, a D flip-flop, and an inverter; wherein the drain of the first MOS tube is connected to the current source I charge , The gate of the first MOS transistor is connected to the DEMAG signal, the source of the first MOS transistor is connected to the drain of the second MOS transistor and one end of the capacitor C1, the gate of the second MOS transistor is connected to the clock signal CLK, and the source of the second MOS transistor And the other end of the capacitor C1 is grounded; the non-inverting input terminals of the second comparator and the third comparator are connected to the source of the first MOS tube, the inverting input terminal of the second comparator is connected to the voltage V TH , the second comparator The enable terminal connection The inverting input terminal of the third comparator is connected to the voltage V TL , and the enable terminal of the third comparator is connected to V
  • the two input ends of the OR gate circuit are respectively connected to the output end of the second comparator and the output end of the third comparator, the output end of the OR gate circuit is connected to the input end of the buffer circuit BUF, and the output end of the buffer circuit BUF is connected to the D flip-flop
  • the signal input terminal of the D flip-flop is connected to the clock signal CLK, the output terminal of the D flip-flop outputs V G-EN , and the V G-EN signal is output through the inverter Signal.
  • the demagnetization detection circuit shown in Fig. 2 includes R1, R2, comparator 1 and reference voltage V DET_ref .
  • V DET_ref reference voltage
  • the output of comparator 1 is low level, and after passing through the inverter INV, it outputs DEMAG high level, indicating that the start of demagnetization is detected.
  • the output of comparator 1 is high level, and the output of DEMAG is low level after passing through the inverter INV, indicating that the end of demagnetization is detected.
  • Figure 2 also shows the principle of the standby judgment circuit.
  • the DEMAG signal drives the MOS Q1 to open, the current source I charge charges the capacitor C1, and the rising level of V C1 is:
  • t ON is the duration of DEMAG high level.
  • DEMAG is at low level, that is, not within the demagnetization time, MOS Q1 is turned off, and V C1 remains unchanged.
  • Each VDET pulse will repeat the above-mentioned process once, so as to realize the voltage rise and accumulation of V C1 during each DEMAG high level period.
  • T CLK By detecting the relationship between the V C1 voltage within a given time T CLK and the set threshold V TL /V TH , the heavy load or light load state of the switching power supply in the current cycle can be judged, and then the synchronous rectifier is controlled to enter the normal working mode or standby mode.
  • T CLK and V TL /V TH here can be set, which is convenient for setting different standby mode trigger thresholds in different applications.
  • the above-mentioned third case and fourth case both occur when the current V G_EN is low, that is, when the current synchronous rectification controller is in standby mode, the enable signal V G_EN of the comparator 3 is low, and the output is always low. Comparator 2 enable signal High, the output is active level. When the rising edge of the next CLK arrives, if V C1 >V TH , the output of comparator 2 is high level, after the OR gate and BUF delay, the VD signal is high level, and the D flip-flop output V G_EN changes from low to The level turns to high level, that is, the third case of the standby judgment circuit: the synchronous rectification controller returns to the normal working mode from the standby mode.
  • the output signal V G_EN of the standby judgment circuit and the demagnetization signal DEMAG are input to an AND gate (AND), and the AND gate outputs V gate to the driving circuit.
  • the driving circuit strengthens the driving ability, outputs a signal VG synchronized with V gate to the gate of the synchronous rectification MOS Q2, and controls the switch of the synchronous rectification MOS.
  • FIG. 3 is a schematic diagram of key waveforms when the synchronous rectification controller of the present application is switched from a normal working mode to a standby mode when it changes from a heavy load to a light load or no load.
  • CLK sends out a pulse signal.
  • the MOS Q2 When the pulse signal is at a high level, the MOS Q2 is turned on to discharge the C1 capacitor, and V C1 is quickly discharged to zero, as shown in the waveform of V C1 in Figure 3.
  • V C1 is quickly discharged to zero, as shown in the waveform of V C1 in Figure 3.
  • the high level of the demagnetization signal DEMAG drives the MOS Q1 to open, and charges the C1 capacitor, and the rising level of V C1 is:
  • t ON is the duration of DEMAG high level.
  • DEMAG is low level, that is, when it is not within the demagnetization time, MOS Q1 is turned off, and VC1 remains unchanged.
  • Each VDET pulse will repeat the above-mentioned process once, so as to realize the voltage rise and accumulation of V C1 during each DEMAG high level period.
  • FIG. 4 is a schematic diagram of key waveforms when the synchronous rectification controller of the present application is switched from a light load or no load to a heavy load, switching from a standby mode to a normal working mode.
  • CLK sends out a pulse signal.
  • the MOS Q2 is turned on to discharge the C1 capacitor, and V C1 is quickly discharged to zero, as shown in the V C1 waveform in the figure.
  • VDET drops rapidly and satisfies "VDET ⁇ V DET_ref_L "
  • the demagnetization signal DEMAG becomes high level, drives MOS Q1 to open, and charges C1 capacitor, and the rising level of V C1 is:
  • t ON is the duration of DEMAG high level.
  • DEMAG is low level, that is, when it is not within the demagnetization time, MOS Q1 is turned off, and V C1 remains unchanged.
  • Each VDET pulse will repeat the above-mentioned process once, so as to realize the voltage rise and accumulation of V C1 during each DEMAG high level period.
  • V C1 Until the next rising edge of CLK arrives, V C1 accumulates and rises to satisfy V C1 >V TH , the D flip-flop output V G_EN changes from low level to high level, and remains at high level until the next CLK comes, Realize the switching of the synchronous rectification controller from the standby mode to the normal working mode.
  • Fig. 5 is a control flow chart of the synchronous rectification controller proposed in this application.
  • the specific implementation circuit and implementation principle of the flowchart follow the block diagram of the synchronous rectification controller in Figure 1 and the synchronous rectification controller and its standby mode control principle proposed in Figure 2.
  • the detailed control process steps are:
  • Step 1 start;
  • Step 2 Power-on reset, initialize the sampling module, initialize each part of the logic circuit, the default VG is low;
  • Step 3 Enter the normal working mode, CLK pulses, V C1 is cleared, V G_EN is enabled, and VG is output normally;
  • Step 4 VDET detects the demagnetization time, and charges C1 within the demagnetization time
  • Step 5 When the timing of T CLK ends and the rising edge of the next CLK pulse, judge whether V C1 is smaller than V TL . If yes, go to step 6; if not, go to step 3;
  • Step 6 Enter standby mode, CLK pulses, V C1 is cleared, V G_EN is disabled, and VG has no output;
  • Step 7 VDET detects the demagnetization time, and charges C1 within the demagnetization time
  • Step 8 When the timing of T CLK ends and the rising edge of the next CLK pulse, judge whether V C1 is greater than V TH . If yes, go to step 3; if not, go to step 6.
  • Fig. 6 is another control schematic diagram of the synchronous rectification controller and its standby mode proposed in this application.
  • the demagnetization detection circuit is exactly the same as the first synchronous rectification controller and its standby mode control schematic diagram proposed in Fig. 2, the difference lies in Fig. 2
  • the standby judgment circuit uses DEMAG to control the I charge to charge the capacitor C1 to realize That is, V C1 and t on are proportional to the first-order function relationship.
  • the standby judging circuit as shown in Figure 6 includes: a resistor, an operational amplifier, a MOS tube, a clock signal CLK, a comparator, a capacitor, an OR gate circuit, a buffer circuit BUF, a D flip-flop, and an inverter; wherein, the fifth One end of resistor R5 is connected to the DEMAG signal, and the other end is connected to the non-inverting input of the operational amplifier.
  • the inverting input of the operational amplifier is connected to the source of the first MOS transistor, and the drain of the first MOS transistor is connected to the output of the operational amplifier.
  • the positive side power supply terminal is connected to the voltage source VCC, the reverse side power supply terminal is grounded, the two ends of the sixth resistor R6 are respectively connected to the inverting input terminal of the operational amplifier and the reference ground, and the two ends of the first capacitor C1 are respectively connected to the output terminal and the inverting input terminal of the operational amplifier.
  • One end of the second capacitor C2 is connected to the non-inverting input terminal of the operational amplifier, the other end of the second capacitor C2 is grounded, the drain of the second MOS transistor is connected to the non-inverting input terminal of the operational amplifier, and the source of the second MOS transistor is grounded.
  • Both the gate of the second MOS transistor and the gate of the first MOS transistor are connected to the clock signal CLK; the non-inverting input terminals of the second comparator and the third comparator are connected to the output terminal V C1 of the operational amplifier, and the The inverting input terminal is connected to the voltage V TH , and the enable terminal of the second comparator is connected to The inverting input terminal of the third comparator is connected to the voltage V TL , the enable terminal of the third comparator is connected to V G-EN ; the two input terminals of the OR gate circuit are respectively connected to the output terminal of the second comparator and the third comparator
  • the output end of the OR gate circuit is connected to the input end of the buffer circuit BUF, the output end of the buffer circuit BUF is connected to the signal input end of the D flip-flop, the clock port of the D flip-flop is connected to the clock signal CLK, and the output end of the D flip-flop Output V G-EN , the V G-EN signal is obtained through an inverter Signal.
  • Fig. 7 is another control schematic diagram of the synchronous rectification controller and its standby mode proposed in this application.
  • the demagnetization detection circuit is exactly the same as the synchronous rectification controller and its standby mode control schematic diagram proposed in Fig. 2 and Fig. 6, as shown in Fig.
  • the standby judgment circuit includes: resistors, operational amplifiers, MOS tubes, comparators, capacitors, OR gate circuits, buffer circuits BUF, D flip-flops, and inverters; among them, one end of the fifth resistor R5 is connected to the DEMAG signal, and the other end is connected to the operation
  • the inverting input terminal of the amplifier the positive-phase input terminal of the operational amplifier is grounded, the positive-side power supply terminal is connected to the voltage source VCC, the reverse-side power supply terminal is connected to the voltage source -VCC, and the two ends of the first capacitor C1 are respectively connected to the output terminal and the inverting input of the operational amplifier.
  • the drain of the first MOS transistor is connected to the inverting input terminal of the operational amplifier, the source of the first MOS transistor is connected to the output terminal of the operational amplifier, and the gate of the first MOS transistor is connected to the clock signal CLK;
  • the second comparator and the second comparator The inverting input terminals of the three comparators are connected to the output terminal V C1 of the operational amplifier, the non-inverting input terminal of the second comparator is connected to the voltage -V TH , and the enabling terminal of the second comparator is connected to The positive phase input terminal of the third comparator is connected to the voltage -V TL , the enable terminal of the third comparator is connected to V G-EN ;
  • the two input terminals of the OR gate circuit are respectively connected to the output terminal of the second comparator and the third comparator
  • the output terminal of the OR gate circuit is connected to the input terminal of the buffer circuit BUF, the output terminal of the buffer circuit BUF is connected to the signal input terminal of the D flip-flop, the clock port of the D
  • the standby judgment circuit in Figure 2 uses DEMAG to control the I charge to charge the capacitor C1 to realize That is, V C1 and t on are proportional to the primary function relationship;
  • the inverting integral circuit composed of operational amplifier, R5, C1, and Q1 is used, then there is Realize the first-order functional relationship in which V C1 and t on are negatively correlated, where V DEMAG is the voltage value when DEMAG is at a high level. Since the VC1 output by the inverting integrator is a negative value, the input conditions of comparator 2 and comparator 3 need to be adjusted accordingly: the input reference value is changed from V TL /V TH to (-V TL )/(-V TH ), and at the same time Set the input reference as the positive input of the comparator and V C1 as the negative input.
  • Other parts of the standby judging circuit are consistent with those shown in Figure 2 and Figure 6 to achieve the same function.
  • the synchronous rectification controller and its standby mode control circuit proposed in this application generate the demagnetization signal DEMAG by detecting the voltage drop across the synchronous rectification MOS, and output the demagnetization signal DEMAG by detecting the effective time t on of DEMAG within the fixed time T CLK V G_EN , to judge whether to switch between normal working mode and standby mode.
  • the synchronous rectification controller of the present application changes from heavy load to light load or no load, switching from the normal working mode to the standby mode can reduce the power consumption of the synchronous rectification controller and achieve the purpose of improving system efficiency.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)
  • Rectifiers (AREA)

Abstract

Des modes de réalisation de la présente demande divulguent un dispositif de commande de redresseur synchrone côté secondaire de bloc d'alimentation à découpage, ainsi qu'un bloc d'alimentation à découpage. Le dispositif de commande de redresseur synchrone comprend : un circuit de détection de démagnétisation, un circuit de détermination de veille, un circuit de porte ET et un circuit d'attaque. Une borne d'entrée du circuit de détection de démagnétisation est connectée à une extrémité d'un MOS à redressement synchrone Q2 du bloc d'alimentation à découpage. Une borne de sortie du circuit de détection de démagnétisation est connectée à une borne d'entrée du circuit de porte ET et l'autre borne de sortie du circuit de détection de démagnétisation est connectée à une borne d'entrée du circuit de détermination de veille. Une borne de sortie du circuit de détermination de veille est connectée à l'autre borne d'entrée du circuit de porte ET. Une borne de sortie du circuit de porte ET est connectée à une borne d'entrée du circuit d'attaque. Une borne de sortie du circuit d'attaque est connectée à une grille du MOS Q2. La solution technique de la présente demande présente l'avantage d'améliorer l'efficacité du système.
PCT/CN2022/106694 2021-07-30 2022-07-20 Dispositif de commande de redresseur synchrone côté secondaire de bloc d'alimentation à découpage, et bloc d'alimentation à découpage WO2023005758A1 (fr)

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