CN216748572U

CN216748572U - Input/output low-voltage difference circuit

Info

Publication number: CN216748572U
Application number: CN202121278886.8U
Authority: CN
Inventors: 郑清良; 黄敏光; 黄卫强; 方兵洲
Original assignee: Tuoer Microelectronics Co ltd
Current assignee: Tuoer Microelectronics Co ltd
Priority date: 2021-06-08
Filing date: 2021-06-08
Publication date: 2022-06-14
Anticipated expiration: 2031-06-08

Abstract

The utility model provides an input/output low dropout circuit, comprising: the drain electrode of the first MOS tube is connected to the voltage input end; the drain electrode of the second MOS tube is connected to the source electrode of the first MOS tube, and the source electrode of the drain electrode of the second MOS tube is grounded; the drain electrode of the third MOS tube is connected to the drain electrode of the first MOS tube, and the source electrode of the third MOS tube is connected to the voltage output end; and one end of the inductor is connected to the source electrode of the first MOS tube, and the other end of the inductor is connected to the voltage output end. The utility model has ingenious design, so that when the input voltage is close to or less than the set output voltage, the deviation of the output voltage and the set output voltage is as small as possible, and compared with a common Buck mode, the utility model realizes lower voltage difference and higher efficiency of input and output; the simple control mode also makes the mode switching more stable.

Description

Input/output low-dropout circuit

Technical Field

The utility model relates to the field of circuits, in particular to an input and output low-voltage difference circuit.

Background

A conventional Buck circuit is shown in fig. 1, in which the driving signals of Q1 and Q2 are complementary, and the duty ratio of Q1 on is set as D, and V is obtained according to the magnetic balance of the inductor current in one switching period_IN×D＝V_OUTI.e. V_OUT＝V_INXd is obtained from the above formula, with the output voltage being less than the input voltage; when the input voltage VIN is close to the SET output voltage VOUT _ SET, the circuit will operate at the maximum duty cycle DMAX; at this time, V_OUT＝V_IN×D_MAXTherefore, when the input voltage continues to decrease, the output voltage also decreases; considering the influences of the actual inductance DCR, the on-resistance of the MOS and the like, the actual output voltage is smaller than VIN × Dmax, and for the occasions requiring a smaller input/output voltage difference (for example, a docking station, 5V input, and 5V or so for the power supply of an output USB port), the Buck circuit is relatively limited.

SUMMERY OF THE UTILITY MODEL

The utility model provides an input/output low dropout circuit which can effectively solve the problems.

The utility model is realized by the following steps:

an input-output low dropout circuit comprising: the drain electrode of the first MOS tube is connected with the voltage input end; the drain electrode of the second MOS tube is connected to the source electrode of the first MOS tube, and the source electrode of the second MOS tube is grounded; the drain electrode of the third MOS tube is connected to the drain electrode of the first MOS tube, and the source electrode of the third MOS tube is connected to the voltage output end; and one end of the inductor is connected to the source electrode of the first MOS tube, and the other end of the inductor is connected to the voltage output end.

As a further improvement, the voltage regulator further comprises a first capacitor, one end of the first capacitor is connected to the voltage input end, and the other end of the first capacitor is grounded.

As a further improvement, the voltage regulator further comprises a second capacitor, one end of the second capacitor is connected to the voltage output end, and the other end of the second capacitor is grounded.

As a further improvement, the first MOS transistor, the second MOS transistor and the third MOS transistor are N-channel MOS transistors.

The utility model has the beneficial effects that:

the utility model has ingenious design, so that when the input voltage is close to or less than the set output voltage, the deviation of the output voltage and the set output voltage is as small as possible, and compared with a common Buck mode, the utility model realizes lower voltage difference and higher efficiency of input and output; the simple control mode also makes the mode switching more stable.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.

Fig. 1 is a diagram of a conventional Buck circuit provided in the background art.

Fig. 2 is a circuit diagram of an input/output low dropout circuit according to an embodiment of the present invention.

Fig. 3 is a waveform diagram of an input/output low dropout circuit according to an embodiment of the present invention.

Fig. 4 is a flow chart of mode switching of an input/output low dropout circuit according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings of the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the utility model, as claimed, but is merely representative of selected embodiments of the utility model. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.

In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.

An input-output low dropout circuit comprising: a first MOS transistor Q1, wherein a drain of the first MOS transistor Q1 is connected to the voltage input terminal; a second MOS transistor Q2, a drain of the second MOS transistor Q2 is connected to the source of the first MOS transistor Q1, and a source of the second MOS transistor Q2 is grounded; a third MOS transistor Q3, a drain of the third MOS transistor Q3 is connected to the drain of the first MOS transistor Q1, and a source of the third MOS transistor Q3 is connected to a voltage output terminal; inductor L_MSaid inductance L_MIs connected to the source of the first MOS transistor Q1, the inductor L_MAnd the other end of the first switch is connected to the voltage output terminal. The utility model has ingenious design, so that when the input voltage is close to or less than the set output voltage, the deviation of the output voltage and the set output voltage is as small as possible, and compared with a common Buck mode, the utility model realizes lower voltage difference and higher efficiency of input and output; the simple control mode also makes the mode switching more stable.

The input/output low-voltage difference circuit also comprises a first capacitor C_INSaid first capacitor C_INIs connected to the voltage input terminal, the first capacitor C_INAnd the other end of the same is grounded.

A kind ofThe input-output low dropout circuit also comprises a second capacitor C_OUTSaid second capacitance C_OUTIs connected to the voltage output terminal, the second capacitor C_OUTAnd the other end of the same is grounded.

The first MOS transistor Q1, the second MOS transistor Q2 and the third MOS transistor Q3 are N-channel MOS transistors.

When V is_INWhen the output voltage is larger than the set output voltage, the circuit works in a Buck mode, Q3 is turned off, and Q1 and Q2 are alternately turned on;

when V is_INWhen the voltage is close to the set output voltage, the circuit enters a Bypass mode, Q2 is turned off, and Q1/Q3 is normally on;

the following is the mode switching process for the Buck circuit with Bypass transistor Q3:

1) when the input voltage V is_INWhen the voltage is higher, the circuit works in a Buck mode, Q3 is turned off, Q1 and Q2 are alternately turned on, and the output voltage is set voltage V_{OUT_SET}Regardless of the line impedance, the duty ratio is D ═ V_{OUT_SET}/V_IN；

2) An input voltage V_INWhen the input voltage drops to a level close to the output voltage, the duty ratio D reaches a maximum duty ratio D_MAXWhen the circuit detects that the circuit works at the maximum duty ratio for n continuous cycles (such as 3 cycles), the circuit enters a Bypass mode from a Buck mode, the circuit turns off Q2, Q1/Q3 is normally on, and the output voltage is equal to V_IN。

3) When the input voltage continues to decrease, the output voltage also decreases;

4) when the input voltage rises, the output voltage also rises;

5) when the input voltage rises, the output voltage V is enabled_OUT＞(1+k)×V_{OUT_SET}When the circuit enters a Buck mode from a Bypass mode, the circuit turns off Q3, and the Q1 and the Q2 are alternately turned on; (k is V)_OUTBeyond V_{OUT_SET}Percentage of (2)

6) When the circuit continues to rise, the circuit works in a Buck mode;

from the above process, the VI N voltage V1 for entering the Bypass mode is calculated as V_{OUT_SET}/D_MAXV for exiting Bypass mode_INThe voltage V2 is (1+ k). times.V_{OUT_SET}It is necessary to make V1 < V2 with some margin to ensure that there is no abnormal switching between the two modes.

7) Q3 may be an N-type transistor or a P-type transistor;

fig. 3 is an operation waveform of an input-output low dropout circuit.

Fig. 4 is a flowchart of an operation of the input/output low dropout circuit.

At an input voltage V_INClose to the set output voltage V_{OUT_SET}When the voltage is equal to I, Q2 is turned off, Q1/Q3 is turned on, and the voltage difference between the input voltage and the output voltage is I_O×[R_{Q3_DS_ON}//(R_{Q1_DS_ON}+DCR_{_LM})]Compared with a common Buck mode, the low-pressure difference and high efficiency of input and output are realized; the simple control mode also makes the mode switching more stable.

The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes may be made to the present invention by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. An input-output low dropout circuit, comprising:

the drain electrode of the first MOS tube is connected with the voltage input end;

the drain electrode of the second MOS tube is connected to the source electrode of the first MOS tube, and the source electrode of the second MOS tube is grounded;

the drain electrode of the third MOS tube is connected to the drain electrode of the first MOS tube, and the source electrode of the third MOS tube is connected to the voltage output end;

and one end of the inductor is connected to the source electrode of the first MOS tube, and the other end of the inductor is connected to the voltage output end.

2. An input-output low dropout circuit according to claim 1, further comprising a first capacitor, wherein one end of said first capacitor is connected to the voltage input terminal, and the other end of said first capacitor is connected to ground.

3. An input-output low dropout circuit according to claim 1, further comprising a second capacitor, wherein one end of said second capacitor is connected to said voltage output terminal, and the other end of said second capacitor is grounded.

4. The input-output low dropout voltage circuit of claim 1, wherein said first MOS transistor, said second MOS transistor and said third MOS transistor are N-channel MOS transistors.