TWI705664B - Silicon carbide power element, drive circuit and control method - Google Patents
Silicon carbide power element, drive circuit and control method Download PDFInfo
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Abstract
一種碳化矽功率元件,受一驅動器控制且具有一閘極至源極電壓以及一源極電壓,其中,該源極電壓根據該閘極至源極電壓上升而下降,或該源極電壓根據該閘極至源極電壓下降而上升,藉此抑制因該閘極至源極電壓變化而產生的一突波,從而抑制該碳化矽功率元件的串擾現象。A silicon carbide power device controlled by a driver and having a gate-to-source voltage and a source voltage, wherein the source voltage drops according to the increase of the gate-source voltage, or the source voltage according to the The gate-to-source voltage drops and rises, thereby suppressing a surge caused by the gate-to-source voltage change, thereby suppressing the crosstalk phenomenon of the silicon carbide power device.
Description
本發明為有關一種功率元件、驅動電路及控制方法,尤指一種碳化矽功率元件、驅動電路及控制方法。The present invention relates to a power element, a driving circuit and a control method, in particular to a silicon carbide power element, a driving circuit and a control method.
碳化矽功率元件具備高工作電壓、可承受較高工作溫度、低導通電阻以及高開關頻率等優點,特別是碳化矽金氧半場效電晶體(SiC MOSFET)以及碳化矽絕緣柵雙極電晶體(SiC IGBT),適合用在近來需求強大的電動車以及5G通訊領域,相關技術可見於美國發明專利公告第US9,018,640 B1號、第US9,373,713 B2號、第US10,020,368 B2號、第US10,483,389 B2 號等。Silicon carbide power components have the advantages of high operating voltage, high operating temperature, low on-resistance and high switching frequency, especially the silicon carbide gold oxide half field effect transistor (SiC MOSFET) and silicon carbide insulated gate bipolar transistor ( SiC IGBT), suitable for use in the field of electric vehicles and 5G communications that are in strong demand recently. Related technologies can be found in the US Patent Publication No. US9,018,640 B1, US9,373,713 B2, US10,020,368 B2, US10, 483,389 B2 etc.
然而,相較於傳統矽功率元件,碳化矽功率元件閘極和源極的耐電壓範圍窄,且耐負壓的能力較差,在高開關頻率下,橋臂電路容易出現串擾現象(Crosstalk)。此問題已在由Binfeng Zhang等人於IEEE Transactions On Industrial Electronics, Vol. 64, No. 11, November 2017所發表的A Magnetic Coupling Based Gate Driver for Crosstalk Suppression of SiC MOSFETs有相關的描述。目前來說,碳化矽功率元件的串擾現象仍無法獲得有效解決。有鑑於此,傳統碳化矽功率元件仍有待改良之處。However, compared with traditional silicon power devices, the gate and source of silicon carbide power devices have a narrow withstand voltage range, and are less capable of withstanding negative voltage. Under high switching frequencies, the bridge arm circuit is prone to crosstalk (Crosstalk). This problem has been described in A Magnetic Coupling Based Gate Driver for Crosstalk Suppression of SiC MOSFETs published by Binfeng Zhang et al. in IEEE Transactions On Industrial Electronics, Vol. 64, No. 11, November 2017. Currently, the crosstalk phenomenon of silicon carbide power devices cannot be effectively solved. In view of this, traditional silicon carbide power components still need to be improved.
本發明的目的,在於改善習知碳化矽功率元件容易發生串擾現象的問題。The purpose of the present invention is to improve the problem of crosstalk in conventional silicon carbide power devices.
為達上述目的,本發明提供一種碳化矽功率元件的控制方法,該方法包括以下步驟:提供一碳化矽功率元件,該碳化矽功率元件受一驅動器控制且具有一閘極至源極電壓以及一源極電壓,該源極電壓至少具有一高準位、一低準位以及一介於該高準位和該低準位之間的中間準位;以及該驅動器交替地輸出一上橋驅動訊號和一下橋驅動訊號至該碳化矽功率元件的一閘極,其中,當該閘極至源極電壓根據該上橋驅動訊號或該下橋驅動訊號上升時,將該源極電壓從該中間準位下降至該低準位或從該高準位下降至該中間準位,當該閘極至源極電壓根據該上橋驅動訊號或該下橋驅動訊號下降時,將該源極電壓從該低準位上升至該中間準位或從該中間準位上升至該高準位。To achieve the above objective, the present invention provides a silicon carbide power device control method. The method includes the following steps: providing a silicon carbide power device, the silicon carbide power device is controlled by a driver and has a gate-to-source voltage and a The source voltage has at least a high level, a low level, and an intermediate level between the high level and the low level; and the driver alternately outputs an upper bridge driving signal and A low-bridge driving signal to a gate of the silicon carbide power device, wherein when the gate-to-source voltage rises according to the high-bridge driving signal or the low-bridge driving signal, the source voltage is from the intermediate level Drop to the low level or from the high level to the intermediate level, and when the gate-to-source voltage drops according to the upper bridge drive signal or the lower bridge drive signal, the source voltage changes from the low level The level rises to the intermediate level or rises from the intermediate level to the high level.
為達上述目的,本發明還提供一種碳化矽功率元件,受一驅動器控制且具有一閘極至源極電壓以及一源極電壓,其中,該源極電壓根據該閘極至源極電壓上升而下降,或該源極電壓根據該閘極至源極電壓下降而上升,藉此抑制因該閘極至源極電壓變化而產生的一突波。To achieve the above objective, the present invention also provides a silicon carbide power device, controlled by a driver and having a gate-to-source voltage and a source voltage, wherein the source voltage is increased according to the gate-to-source voltage. Decrease, or the source voltage rises according to the drop of the gate-to-source voltage, thereby suppressing a surge caused by the change of the gate-to-source voltage.
為達上述目的,本發明更提供一種驅動電路,包括:一碳化矽功率元件,具有一閘極至源極電壓及一源極電壓;一驅動器,係控制該碳化矽功率元件;以及一補償模組,係根據該閘極至源極電壓上升而控制該源極電壓下降,或根據該閘極至源極電壓下降而控制該源極電壓上升,藉此抑制因該閘極至源極電壓變化而產生的一突波。To achieve the above objective, the present invention further provides a driving circuit, including: a silicon carbide power device with a gate-to-source voltage and a source voltage; a driver for controlling the silicon carbide power device; and a compensation module The group controls the source voltage drop according to the gate-to-source voltage rise, or controls the source voltage rise according to the gate-source voltage drop, thereby suppressing the gate-source voltage change And there is a sudden wave.
本發明藉由控制該源極電壓,以抑制因該閘極至源極電壓的變化而產生的突波,從而解決碳化矽半導體功率元件所發生串擾現象的問題。The present invention controls the source voltage to suppress the surge generated by the change of the gate-to-source voltage, thereby solving the problem of crosstalk phenomenon of silicon carbide semiconductor power devices.
有關本發明的詳細說明及技術內容,現就配合圖式說明如下:The detailed description and technical content of the present invention are described as follows in conjunction with the drawings:
本發明揭示一種碳化矽功率元件的控制方法,應用在包括一碳化矽功率元件的驅動電路,該碳化矽功率元件可以為一絕緣閘極雙極性電晶體(Insulated Gate Bipolar Transistor,IGBT)、一金屬氧化物半導體場效電晶體(Metal-Oxide-Semiconductor Field-Effect Transistor,MOSFET)、一接面場效電晶體(Junction gate Field-Effect Transistor,JFET)或其他功率元件。該碳化矽功率元件受一驅動器控制且具有一閘極至源極電壓(Vgs)以及一源極電壓(Vs)。The present invention discloses a control method of a silicon carbide power element, which is applied to a drive circuit including a silicon carbide power element. The silicon carbide power element can be an insulated gate bipolar transistor (IGBT), a metal Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), a Junction gate Field-Effect Transistor (JFET) or other power components. The silicon carbide power device is controlled by a driver and has a gate-to-source voltage (Vgs) and a source voltage (Vs).
請參閱『圖1』,為本發明一實施例應用於半橋電路的示意圖,在此以該碳化矽功率元件應用於一半橋電路作為舉例說明,該半橋電路包括一控制器10、一上橋臂電路20以及一下橋臂電路30,該上橋臂電路20包括一第一驅動器21、一第一碳化矽功率元件22、一第一電感23、一第一電阻24以及複數個第一電容25,該第一電感23和該第一電阻24串接於該第一驅動器21和該第一碳化矽功率元件22之間,該第一電容25包括一閘汲極電容251、一閘源極電容252以及一汲源極電容253。該下橋臂電路30包括包括一第二驅動器31、一第二碳化矽功率元件32、一第二電感33、一第二電阻34以及複數個第二電容35,該第二電感33和該第二電阻34串接於該第二驅動器31和該第二碳化矽功率元件32之間,該第二電容35包括一閘汲極電容351、一閘源極電容352以及一汲源極電容353。Please refer to "FIG. 1", which is a schematic diagram of an embodiment of the present invention applied to a half-bridge circuit. Here, the silicon carbide power device is applied to a half-bridge circuit as an example. The half-bridge circuit includes a
請參閱『圖2』,為根據本發明一實施例的碳化矽功率元件的電壓輸出示意圖,該源極電壓(Vs)至少具有一高準位(H)、一低準位(L)以及一介於該高準位(H)和該低準位(L)之間的中間準位(M)。在驅動時,該第一驅動器21和該第二驅動器31交替地輸出一上橋驅動訊號(Gate signal 1)和一下橋驅動訊號(Gate signal 2)至該第一碳化矽功率元件22以及該第二碳化矽功率元件32的一閘極,本發明中,當該第一碳化矽功率元件22以及該第二碳化矽功率元件32的該閘極至源極電壓(Vgs)根據該上橋驅動訊號(Gate signal 1)或該下橋驅動訊號(Gate signal 2)上升時,係控制該源極電壓(Vs)從該中間準位(M)下降至該低準位(L)或從該高準位(H)下降至該中間準位(M);當第一碳化矽功率元件22以及該第二碳化矽功率元件32的該閘極至源極電壓(Vgs)根據該上橋驅動訊號(Gate signal 1)或該下橋驅動訊號(Gate signal 2)下降時,將該源極電壓(Vs)從該低準位上升(L)至該中間準位(M)或從該中間準位(M)上升至該高準位(H)。Please refer to "Figure 2", which is a schematic diagram of the voltage output of a silicon carbide power device according to an embodiment of the present invention. The source voltage (Vs) has at least a high level (H), a low level (L), and a dielectric The middle level (M) between the high level (H) and the low level (L). During driving, the
如『圖2』所示,在時間點(t1)、(t5)時,該下橋驅動訊號(Gate signal 2)係下降,致使該閘極至源極電壓(Vgs)產生負峰值(negative peak),此時,控制該源極電壓(Vs)從該中間準位(M)上升至該高準位(H),以抑制或降低該閘極至源極電壓(Vgs)的突波(spike);在時間點(t2)、(t6)時,該上橋驅動訊號(Gate signal 1)係上升,致使該閘極至源極電壓(Vgs)產生正峰值(positive peak),此時,控制該源極電壓(Vs)從該中間準位(M)下降至該低準位(L),以抑制或降低該閘極至源極電壓(Vgs)的突波;在時間點(t3)時,該上橋驅動訊號(Gate signal 1)係下降,致使該閘極至源極電壓(Vgs)產生負峰值,此時,控制該源極電壓(Vs)從該中間準位(M)上升至該高準位(H),以抑制或降低該閘極至源極電壓(Vgs)的突波;在時間點(t4)時,該下橋驅動訊號(Gate signal 2)係上升,致使該閘極至源極電壓(Vgs)產生正峰值,此時,控制該源極電壓(Vs)從該中間準位(M)下降至該低準位(L)。『圖2』中,Vgs為未採用本發明方法的閘極至源極電壓,可明顯看到有突波的發生;Vgs’為採用本發明方法的閘極至源極電壓,可明顯看到突波受到抑制和改善。As shown in "Figure 2", at time points (t1) and (t5), the lower bridge drive signal (Gate signal 2) drops, causing the gate-to-source voltage (Vgs) to produce a negative peak (Vgs) ), at this time, the source voltage (Vs) is controlled to rise from the middle level (M) to the high level (H) to suppress or reduce the gate-to-source voltage (Vgs) spike ); At time points (t2) and (t6), the upper bridge drive signal (Gate signal 1) rises, causing the gate-to-source voltage (Vgs) to generate a positive peak. At this time, control The source voltage (Vs) drops from the middle level (M) to the low level (L) to suppress or reduce the gate-to-source voltage (Vgs) surge; at time point (t3) , The upper bridge drive signal (Gate signal 1) drops, causing the gate-to-source voltage (Vgs) to generate a negative peak value. At this time, the source voltage (Vs) is controlled to rise from the middle level (M) to The high level (H) is used to suppress or reduce the gate-to-source voltage (Vgs) surge; at the time point (t4), the lower bridge drive signal (Gate signal 2) rises, causing the gate The pole-to-source voltage (Vgs) generates a positive peak value. At this time, the source voltage (Vs) is controlled to drop from the intermediate level (M) to the low level (L). In "Figure 2", Vgs is the gate-to-source voltage without using the method of the present invention, and the occurrence of surge can be clearly seen; Vgs' is the gate-to-source voltage using the method of the present invention, which can be clearly seen The surge is suppressed and improved.
請參閱『圖3』,為本發明一實施例的邏輯方塊示意圖,用以說明控制方法的判斷和操作機制。本實施例中,先經由方塊41或方塊42判斷該上橋驅動訊號(Gate signal 1)為上升或下降,以及方塊43或方塊44判斷該下橋驅動訊號(Gate signal 2)為上升或下降。方塊41以及方塊43判斷後將關聯於驅動訊號上升的一第一結果傳送至方塊45,方塊42以及方塊44判斷後將關聯於驅動訊號下降的一第二結果傳送至方塊46,本實施例中,方塊45和方塊46為一或閘。若任一該第一結果的輸出為有效時,則將觸發方塊47,即控制該源極電壓(Vs)下降;反之,若任一該第二結果的輸出為有效時,則將觸發方塊48,即控制該源極電壓(Vs)上升,從而達到抑制或降低該閘極至源極電壓(Vgs)的突波的效果。Please refer to "FIG. 3", which is a schematic logic block diagram of an embodiment of the present invention to illustrate the judgment and operation mechanism of the control method. In this embodiment, firstly,
請參閱『圖4』,為本發明另一實施例的邏輯方塊示意圖,相較於『圖3』,本實施例多了方塊491、方塊492以及方塊493,當方塊491偵測到該上橋驅動訊號(Gate signal 1)或該下橋驅動訊號(Gate signal 2)的波形發生變化時將改變輸出(即邊緣觸發(Edge trigger)),而透過方塊492致使該源極電壓(Vs)的上升或下降發生一延遲,該延遲即該源極電壓(Vs)的上升或下降持續的時間,最終觸發方塊493而讓該源極電壓(Vs)的上升或下降持續一段時間。Please refer to "FIG. 4", which is a schematic diagram of the logic block of another embodiment of the present invention. Compared with "FIG. 3", this embodiment has
發明中,該上橋驅動訊號(Gate signal 1)及該下橋驅動訊號(Gate signal 2)的偵測以及該閘極至源極電壓(Vgs)的控制可由一補償模組來執行,該補償模組包括一第一補償單元以及一第二補償單元,該第一補償單元偵測該上橋驅動訊號(Gate signal 1)以及該下橋驅動訊號(Gate signal 2),當該閘極至源極電壓(Vgs)基於該上橋驅動訊號(Gate signal 1)或該下橋驅動訊號(Gate signal 2)上升時,控制該源極電壓(Vs)下降,該第二補償單元偵測該上橋驅動訊號(Gate signal 1)或該下橋驅動訊號(Gate signal 2),當該閘極至源極電壓(Vgs)基於該上橋驅動訊號(Gate signal 1)或該下橋驅動訊號(Gate signal 2)下降時,控制該源極電壓上升(Vs)。請參閱『圖5』,為本發明一實施例的電路結構示意圖,本實施例採用一三階閘極驅動器(Three level gate driver)作為該補償模組舉例說明,包括一驅動器21、一碳化矽功率元件22、一第一電感23、一第一電阻24、複數個第一電容25、一第一放大器26以及一第二放大器27,該第一電感23和該第一電阻24串接於該驅動器21和該碳化矽功率元件22之間,該第一電容25包括一閘汲極電容251、一閘源極電容252以及一汲源極電容253。該驅動器21輸出一驅動訊號至該碳化矽功率元件22,該驅動訊號可為一正電壓或一負電壓。該第一放大器26和該第二放大器27分別接收一第一輸入訊號261以及一第二輸入訊號271,該第一輸入訊號261以及該第二輸入訊號271係關聯於該驅動訊號,舉例來說,當該驅動訊號為該正電壓時,該第一輸入訊號261以及該第二輸入訊號271均為一低電平,該源極電壓下降;當該驅動訊號為該負電壓時,該第一輸入訊號261以及該第二輸入訊號271均為一高電平,該源極電壓上升(第0階);當該驅動訊號為該正電壓時,該第一輸入訊號261以及該第二輸入訊號271均為一低電平,該源極電壓下降(第1階);當該驅動訊號變化為該負電壓或變化為該正電壓後,該第一輸入訊號261以及該第二輸入訊號271分別為該高電平以及該低電平,或該低電平以及該高電平,該源極電壓保持不變(第2階)。In the invention, the detection of the gate signal (Gate signal 1) and the gate signal (Gate signal 2) and the control of the gate-to-source voltage (Vgs) can be performed by a compensation module. The compensation The module includes a first compensation unit and a second compensation unit. The first compensation unit detects the upper bridge drive signal (Gate signal 1) and the lower bridge drive signal (Gate signal 2), and when the gate goes to the source When the pole voltage (Vgs) rises based on the upper bridge drive signal (Gate signal 1) or the lower bridge drive signal (Gate signal 2), the source voltage (Vs) is controlled to decrease, and the second compensation unit detects the upper bridge Drive signal (Gate signal 1) or the lower bridge drive signal (Gate signal 2), when the gate-to-source voltage (Vgs) is based on the upper bridge drive signal (Gate signal 1) or the lower bridge drive signal (Gate signal) 2) When it falls, the source voltage is controlled to rise (Vs). Please refer to "FIG. 5", which is a schematic diagram of the circuit structure of an embodiment of the present invention. This embodiment uses a three-level gate driver as an example of the compensation module, including a
請參閱『圖6』,為本發明又一實施例的邏輯方塊示意圖,係以Cambridge Scanner單擊電路舉例說明,方塊61(G1 Rising Flag)和方塊62(G2 Rising Flag)分別表示該上橋驅動訊號(Gate signal 1)和該下橋驅動訊號(Gate signal 2)為上升,方塊63採用一反或閘,方塊64則為一第一單擊觸發器。方塊65(G1 Dropping Flag)和方塊66(G2 Dropping Flag)分別表示該上橋驅動訊號(Gate signal 1)和該下橋驅動訊號(Gate signal 2)為下降,方塊67採用一或閘,方塊68則為一第二單擊觸發器。其中,方塊64的第一單擊觸發器包括一反及閘641、一電容642、一電阻643以及一反閘644,方塊68的第二單擊觸發器包括一或閘681、一電容682、一電阻683以及一反閘684。Please refer to "FIG. 6", which is a schematic diagram of a logic block diagram of another embodiment of the present invention. The Cambridge Scanner click circuit is taken as an example. Block 61 (G1 Rising Flag) and block 62 (G2 Rising Flag) respectively represent the upper bridge drive The signal (Gate signal 1) and the lower bridge drive signal (Gate signal 2) are rising,
請參閱『圖7』,為本發明另一實施例的電路結構示意圖,相較於『圖5』,本實施例中採用一D型正反器(D-latch flip-flop)28,該D型正反器(D-latch flip-flop)28耦接至一邏輯單元70,其中,該D型正反器28根據該邏輯單元70產生的一第一輸入訊號281以及一第二輸入訊號282而決定一輸出283,該邏輯單元70的邏輯方塊示意圖則參閱『圖8』,方塊71、72分別代表該上橋驅動訊號(Gate signal 1)和該下橋驅動訊號(Gate signal 2),方塊73為一延遲器,方塊74、75為一或閘,方塊76、77為一反向器。該上橋驅動訊號(Gate signal 1)和該下橋驅動訊號(Gate signal 2)輸入該邏輯單元70後將產生CLK訊號、/CLK訊號、DCLK訊號以及/DCLK訊號,其中,CLK訊號、DCLK訊號係該第一輸入訊號281,而輸入該D型正反器28的D端子,/CLK訊號、/DCLK訊號係該第二輸入訊號282,而輸入該D型正反器28的CLK端子,『圖9』為根據『圖7』的實施例的電壓輸出示意圖。Please refer to "FIG. 7", which is a schematic diagram of the circuit structure of another embodiment of the present invention. Compared with "FIG. 5", a D-latch flip-
請參閱『圖10』,為本發明一實施例的流程示意圖。將該上橋驅動訊號(Gate signal 1)和該下橋驅動訊號視為一脈衝寬度調變訊號(PWM signal),當該脈衝寬度調變訊號的狀態發生變化(方塊81)時,會被偵測到且調整源極電壓(Vs)為上升或下降(方塊82),且,將引發該閘極至源極電壓(Vgs)發生變化(方塊83),而該閘極至源極電壓(Vgs)的改變將使汲極至源極電壓(Vds)也發生變化(方塊84),並造成該閘極至源極電壓(Vgs)發生振鈴(Ringing)現象(方塊85),其中,該汲極至源極電壓(Vds)的變化將產生密勒效應(Miller effect)(方塊86)。最終,由於該源極電壓(Vs)會基於該脈衝寬度調變訊號的變化而調整,從而抑制或降低該閘極至源極電壓(Vgs)的突波(方塊87)。Please refer to "Figure 10", which is a schematic flowchart of an embodiment of the present invention. The upper bridge driving signal (Gate signal 1) and the lower bridge driving signal are regarded as a pulse width modulation signal (PWM signal), and when the state of the pulse width modulation signal changes (block 81), it will be detected Measure and adjust the source voltage (Vs) to rise or fall (Block 82), and cause the gate-to-source voltage (Vgs) to change (Block 83), and the gate-to-source voltage (Vgs) ) Will cause the drain-to-source voltage (Vds) to also change (block 84), and cause the gate-to-source voltage (Vgs) to ring (block 85), wherein the drain The change to the source voltage (Vds) will produce the Miller effect (block 86). Finally, since the source voltage (Vs) is adjusted based on the change of the pulse width modulation signal, the gate-to-source voltage (Vgs) surge is suppressed or reduced (block 87).
綜上,本發明藉由控制該源極電壓,以抑制因該閘極至源極電壓(Vgs)的變化而產生的突波,從而解決碳化矽半導體功率元件所發生串擾現象的問題。In summary, the present invention controls the source voltage to suppress the surge caused by the change of the gate-to-source voltage (Vgs), thereby solving the problem of crosstalk phenomenon of silicon carbide semiconductor power devices.
10:控制器 20:上橋臂電路 21:第一驅動器 22:第一碳化矽功率元件 23:第一電感 24:第一電阻 25:第一電容 251:閘汲極電容 252:閘源極電容 253:汲源極電容 26:第一放大器 261:第一輸入訊號 27:第二放大器 271:第二輸入訊號 28:D型正反器 281:第一輸入訊號 282:第二輸入訊號 283:輸出訊號 30:下橋臂電路 31:第二驅動器 32:第二碳化矽功率元件 33:第二電感 34:第二電阻 35:第二電容 351:閘汲極電容 352:閘源極電容 353:汲源極電容 41、42、43、44、45、46、47、48、491、492、493:方塊 61、62、63、64、65、66、67、68:方塊 641:反及閘 642:電容 643:電阻 644:反閘 681:或閘 682:電容 683:電阻 684:反閘 70:邏輯單元 71、72、73、74、75、76、77、81、82、83、84、85、86、87:方塊 Gate signal 1:上橋驅動訊號 Gate signal 2:下橋驅動訊號 Vs:源極電壓 Vgs 、Vgs’:閘極至源極電壓 H:高準位 M:中間準位 L:低準位 10: Controller 20: Upper arm circuit 21: first drive 22: The first silicon carbide power element 23: The first inductance 24: first resistance 25: The first capacitor 251: gate and drain capacitance 252: gate source capacitance 253: Drain source capacitance 26: The first amplifier 261: First input signal 27: second amplifier 271: second input signal 28: D-type flip-flop 281: The first input signal 282: second input signal 283: Output signal 30: lower arm circuit 31: second drive 32: The second silicon carbide power element 33: second inductor 34: second resistor 35: second capacitor 351: gate and drain capacitance 352: gate source capacitance 353: Drain source capacitance 41, 42, 43, 44, 45, 46, 47, 48, 491, 492, 493: cube 61, 62, 63, 64, 65, 66, 67, 68: cube 641: reverse and gate 642: Capacitor 643: Resistance 644: Reverse Gate 681: or gate 682: Capacitor 683: Resistance 684: Reverse Gate 70: Logic Unit 71, 72, 73, 74, 75, 76, 77, 81, 82, 83, 84, 85, 86, 87: cube Gate signal 1: Upper bridge drive signal Gate signal 2: lower bridge drive signal Vs: source voltage Vgs, Vgs’: gate-to-source voltage H: High level M: Middle level L: Low level
『圖1』,為本發明一實施例應用於半橋電路的電路結構示意圖。 『圖2』,為根據本發明的碳化矽功率元件的電壓輸出示意圖。 『圖3』,為本發明一實施例的邏輯方塊示意圖。 『圖4』,為本發明另一實施例的邏輯方塊示意圖。 『圖5』,為本發明一實施例的電路結構示意圖。 『圖6』,為本發明又一實施例的邏輯方塊示意圖。 『圖7』,為本發明另一實施例的電路結構示意圖。 『圖8』,為『圖7』的邏輯方塊示意圖。 『圖9』,為根據『圖7』的實施例的電壓輸出示意圖。 『圖10』,為本發明一實施例的操作流程示意圖。 "Figure 1" is a schematic diagram of a circuit structure applied to a half-bridge circuit according to an embodiment of the present invention. "Figure 2" is a schematic diagram of the voltage output of the silicon carbide power device according to the present invention. "Figure 3" is a schematic diagram of a logic block of an embodiment of the present invention. "Figure 4" is a schematic diagram of a logic block of another embodiment of the present invention. "Figure 5" is a schematic diagram of the circuit structure of an embodiment of the present invention. "Figure 6" is a schematic diagram of a logic block of another embodiment of the present invention. "Figure 7" is a schematic diagram of the circuit structure of another embodiment of the present invention. "Figure 8" is the logical block diagram of "Figure 7". "Figure 9" is a schematic diagram of voltage output according to the embodiment of "Figure 7". "Figure 10" is a schematic diagram of the operation flow of an embodiment of the present invention.
Gate signal 1:上橋驅動訊號 Gate signal 1: Upper bridge drive signal
Gate signal 2:下橋驅動訊號 Gate signal 2: lower bridge drive signal
Vs:源極電壓 Vs: source voltage
Vgs、Vgs’:閘極至源極電壓 Vgs, Vgs’: gate-to-source voltage
H:高準位 H: High level
M:中間準位 M: Middle level
L:低準位 L: Low level
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US20110285378A1 (en) * | 2010-05-18 | 2011-11-24 | Shuji Tamaoka | Drive device |
US9059697B2 (en) * | 2013-04-08 | 2015-06-16 | Fujitsu Semiconductor Limited | Drive circuit and drive method for driving normally-on-type transistor |
US20190158084A1 (en) * | 2017-11-23 | 2019-05-23 | Infineon Technologies Ag | Method and electronic circuit for driving a transistor device |
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US20110285378A1 (en) * | 2010-05-18 | 2011-11-24 | Shuji Tamaoka | Drive device |
US9059697B2 (en) * | 2013-04-08 | 2015-06-16 | Fujitsu Semiconductor Limited | Drive circuit and drive method for driving normally-on-type transistor |
US20190158084A1 (en) * | 2017-11-23 | 2019-05-23 | Infineon Technologies Ag | Method and electronic circuit for driving a transistor device |
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