TWI705664B - Silicon carbide power element, drive circuit and control method - Google Patents

Abstract

A silicon carbide power device controlled by a driver and having a gate-to-source voltage and a source voltage, wherein the source voltage drops according to the increase of the gate-source voltage, or the source voltage according to the The gate-to-source voltage drops and rises, thereby suppressing a surge caused by the gate-to-source voltage change, thereby suppressing the crosstalk phenomenon of the silicon carbide power device.

Description

Silicon carbide power element, drive circuit and control method

The present invention relates to a power element, a driving circuit and a control method, in particular to a silicon carbide power element, a driving circuit and a control method.

Silicon carbide power components have the advantages of high operating voltage, high operating temperature, low on-resistance and high switching frequency, especially the silicon carbide gold oxide half field effect transistor (SiC MOSFET) and silicon carbide insulated gate bipolar transistor ( SiC IGBT), suitable for use in the field of electric vehicles and 5G communications that are in strong demand recently. Related technologies can be found in the US Patent Publication No. US9,018,640 B1, US9,373,713 B2, US10,020,368 B2, US10, 483,389 B2 etc.

However, compared with traditional silicon power devices, the gate and source of silicon carbide power devices have a narrow withstand voltage range, and are less capable of withstanding negative voltage. Under high switching frequencies, the bridge arm circuit is prone to crosstalk (Crosstalk). This problem has been described in A Magnetic Coupling Based Gate Driver for Crosstalk Suppression of SiC MOSFETs published by Binfeng Zhang et al. in IEEE Transactions On Industrial Electronics, Vol. 64, No. 11, November 2017. Currently, the crosstalk phenomenon of silicon carbide power devices cannot be effectively solved. In view of this, traditional silicon carbide power components still need to be improved.

The purpose of the present invention is to improve the problem of crosstalk in conventional silicon carbide power devices.

To achieve the above objective, the present invention provides a silicon carbide power device control method. The method includes the following steps: providing a silicon carbide power device, the silicon carbide power device is controlled by a driver and has a gate-to-source voltage and a The source voltage has at least a high level, a low level, and an intermediate level between the high level and the low level; and the driver alternately outputs an upper bridge driving signal and A low-bridge driving signal to a gate of the silicon carbide power device, wherein when the gate-to-source voltage rises according to the high-bridge driving signal or the low-bridge driving signal, the source voltage is from the intermediate level Drop to the low level or from the high level to the intermediate level, and when the gate-to-source voltage drops according to the upper bridge drive signal or the lower bridge drive signal, the source voltage changes from the low level The level rises to the intermediate level or rises from the intermediate level to the high level.

To achieve the above objective, the present invention also provides a silicon carbide power device, controlled by a driver and having a gate-to-source voltage and a source voltage, wherein the source voltage is increased according to the gate-to-source voltage. Decrease, or the source voltage rises according to the drop of the gate-to-source voltage, thereby suppressing a surge caused by the change of the gate-to-source voltage.

To achieve the above objective, the present invention further provides a driving circuit, including: a silicon carbide power device with a gate-to-source voltage and a source voltage; a driver for controlling the silicon carbide power device; and a compensation module The group controls the source voltage drop according to the gate-to-source voltage rise, or controls the source voltage rise according to the gate-source voltage drop, thereby suppressing the gate-source voltage change And there is a sudden wave.

The present invention controls the source voltage to suppress the surge generated by the change of the gate-to-source voltage, thereby solving the problem of crosstalk phenomenon of silicon carbide semiconductor power devices.

The detailed description and technical content of the present invention are described as follows in conjunction with the drawings:

The present invention discloses a control method of a silicon carbide power element, which is applied to a drive circuit including a silicon carbide power element. The silicon carbide power element can be an insulated gate bipolar transistor (IGBT), a metal Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), a Junction gate Field-Effect Transistor (JFET) or other power components. The silicon carbide power device is controlled by a driver and has a gate-to-source voltage (Vgs) and a source voltage (Vs).

Please refer to "FIG. 1", which is a schematic diagram of an embodiment of the present invention applied to a half-bridge circuit. Here, the silicon carbide power device is applied to a half-bridge circuit as an example. The half-bridge circuit includes a controller 10 and a top A bridge arm circuit 20 and a lower bridge arm circuit 30. The upper bridge arm circuit 20 includes a first driver 21, a first silicon carbide power element 22, a first inductor 23, a first resistor 24, and a plurality of first capacitors 25. The first inductor 23 and the first resistor 24 are connected in series between the first driver 21 and the first silicon carbide power element 22, and the first capacitor 25 includes a gate-drain capacitor 251 and a gate-source The capacitor 252 and a drain-source capacitor 253. The lower bridge arm circuit 30 includes a second driver 31, a second silicon carbide power element 32, a second inductor 33, a second resistor 34, and a plurality of second capacitors 35. The second inductor 33 and the first Two resistors 34 are connected in series between the second driver 31 and the second silicon carbide power device 32. The second capacitor 35 includes a gate-drain capacitor 351, a gate-source capacitor 352 and a drain-source capacitor 353.

Please refer to "Figure 2", which is a schematic diagram of the voltage output of a silicon carbide power device according to an embodiment of the present invention. The source voltage (Vs) has at least a high level (H), a low level (L), and a dielectric The middle level (M) between the high level (H) and the low level (L). During driving, the first driver 21 and the second driver 31 alternately output an upper bridge driving signal (Gate signal 1) and a lower bridge driving signal (Gate signal 2) to the first silicon carbide power device 22 and the second A gate of two silicon carbide power devices 32. In the present invention, when the gate-to-source voltage (Vgs) of the first silicon carbide power device 22 and the second silicon carbide power device 32 is based on the upper bridge drive signal When (Gate signal 1) or the lower bridge drive signal (Gate signal 2) rises, the source voltage (Vs) is controlled to drop from the intermediate level (M) to the low level (L) or from the high level The level (H) drops to the intermediate level (M); when the gate-to-source voltage (Vgs) of the first silicon carbide power device 22 and the second silicon carbide power device 32 is based on the upper bridge drive signal (Gate signal 1) or the lower bridge drive signal (Gate signal 2) drops, the source voltage (Vs) rises from the low level (L) to the middle level (M) or from the middle level (M) ) Rise to the high level (H).

As shown in "Figure 2", at time points (t1) and (t5), the lower bridge drive signal (Gate signal 2) drops, causing the gate-to-source voltage (Vgs) to produce a negative peak (Vgs) ), at this time, the source voltage (Vs) is controlled to rise from the middle level (M) to the high level (H) to suppress or reduce the gate-to-source voltage (Vgs) spike ); At time points (t2) and (t6), the upper bridge drive signal (Gate signal 1) rises, causing the gate-to-source voltage (Vgs) to generate a positive peak. At this time, control The source voltage (Vs) drops from the middle level (M) to the low level (L) to suppress or reduce the gate-to-source voltage (Vgs) surge; at time point (t3) , The upper bridge drive signal (Gate signal 1) drops, causing the gate-to-source voltage (Vgs) to generate a negative peak value. At this time, the source voltage (Vs) is controlled to rise from the middle level (M) to The high level (H) is used to suppress or reduce the gate-to-source voltage (Vgs) surge; at the time point (t4), the lower bridge drive signal (Gate signal 2) rises, causing the gate The pole-to-source voltage (Vgs) generates a positive peak value. At this time, the source voltage (Vs) is controlled to drop from the intermediate level (M) to the low level (L). In "Figure 2", Vgs is the gate-to-source voltage without using the method of the present invention, and the occurrence of surge can be clearly seen; Vgs' is the gate-to-source voltage using the method of the present invention, which can be clearly seen The surge is suppressed and improved.

Please refer to "FIG. 3", which is a schematic logic block diagram of an embodiment of the present invention to illustrate the judgment and operation mechanism of the control method. In this embodiment, firstly, block 41 or block 42 determines whether the upper bridge driving signal (Gate signal 1) is rising or falling, and block 43 or block 44 determines whether the lower bridge driving signal (Gate signal 2) is rising or falling. After the judgment of block 41 and block 43, a first result related to the increase of the driving signal is transmitted to block 45. After the judgment of block 42 and block 44, a second result related to the decrease of the driving signal is transmitted to block 46. In this embodiment , Block 45 and Block 46 are an OR gate. If the output of any of the first results is valid, block 47 will be triggered, that is, the source voltage (Vs) will be controlled to drop; on the contrary, if the output of any of the second results is valid, block 48 will be triggered , That is, the source voltage (Vs) is controlled to rise, so as to achieve the effect of suppressing or reducing the gate-to-source voltage (Vgs) surge.

Please refer to "FIG. 4", which is a schematic diagram of the logic block of another embodiment of the present invention. Compared with "FIG. 3", this embodiment has more blocks 491, 492, and 493. When block 491 detects the upper bridge When the waveform of the driving signal (Gate signal 1) or the lower bridge driving signal (Gate signal 2) changes, the output (ie, edge trigger) will be changed, and the source voltage (Vs) will rise through block 492 Or, a delay occurs when the source voltage (Vs) rises or falls. The delay is the duration of the rise or fall of the source voltage (Vs), and finally block 493 is triggered to allow the source voltage (Vs) to rise or fall for a period of time.

In the invention, the detection of the gate signal (Gate signal 1) and the gate signal (Gate signal 2) and the control of the gate-to-source voltage (Vgs) can be performed by a compensation module. The compensation The module includes a first compensation unit and a second compensation unit. The first compensation unit detects the upper bridge drive signal (Gate signal 1) and the lower bridge drive signal (Gate signal 2), and when the gate goes to the source When the pole voltage (Vgs) rises based on the upper bridge drive signal (Gate signal 1) or the lower bridge drive signal (Gate signal 2), the source voltage (Vs) is controlled to decrease, and the second compensation unit detects the upper bridge Drive signal (Gate signal 1) or the lower bridge drive signal (Gate signal 2), when the gate-to-source voltage (Vgs) is based on the upper bridge drive signal (Gate signal 1) or the lower bridge drive signal (Gate signal) 2) When it falls, the source voltage is controlled to rise (Vs). Please refer to "FIG. 5", which is a schematic diagram of the circuit structure of an embodiment of the present invention. This embodiment uses a three-level gate driver as an example of the compensation module, including a driver 21, a silicon carbide The power element 22, a first inductor 23, a first resistor 24, a plurality of first capacitors 25, a first amplifier 26 and a second amplifier 27 are connected in series with the first inductor 23 and the first resistor 24 Between the driver 21 and the silicon carbide power device 22, the first capacitor 25 includes a gate-drain capacitor 251, a gate-source capacitor 252 and a drain-source capacitor 253. The driver 21 outputs a driving signal to the silicon carbide power device 22, and the driving signal can be a positive voltage or a negative voltage. The first amplifier 26 and the second amplifier 27 respectively receive a first input signal 261 and a second input signal 271. The first input signal 261 and the second input signal 271 are related to the driving signal, for example , When the driving signal is the positive voltage, the first input signal 261 and the second input signal 271 are both a low level, the source voltage drops; when the driving signal is the negative voltage, the first The input signal 261 and the second input signal 271 are both a high level, and the source voltage rises (0th order); when the driving signal is the positive voltage, the first input signal 261 and the second input signal 271 is a low level, the source voltage drops (first order); when the driving signal changes to the negative voltage or changes to the positive voltage, the first input signal 261 and the second input signal 271 are respectively For the high level and the low level, or the low level and the high level, the source voltage remains unchanged (second order).

Please refer to "FIG. 6", which is a schematic diagram of a logic block diagram of another embodiment of the present invention. The Cambridge Scanner click circuit is taken as an example. Block 61 (G1 Rising Flag) and block 62 (G2 Rising Flag) respectively represent the upper bridge drive The signal (Gate signal 1) and the lower bridge drive signal (Gate signal 2) are rising, block 63 uses an inverted OR gate, and block 64 is a first click trigger. Block 65 (G1 Dropping Flag) and block 66 (G2 Dropping Flag) respectively indicate that the upper bridge drive signal (Gate signal 1) and the lower bridge drive signal (Gate signal 2) are falling. Block 67 uses an OR gate, and block 68 It is a second click trigger. Wherein, the first click trigger in block 64 includes an inverter 641, a capacitor 642, a resistor 643, and an inverter 644, and the second click trigger in block 68 includes an OR gate 681, a capacitor 682, A resistor 683 and a reverse gate 684.

Please refer to "FIG. 7", which is a schematic diagram of the circuit structure of another embodiment of the present invention. Compared with "FIG. 5", a D-latch flip-flop 28 is used in this embodiment. The D-latch flip-flop 28 is coupled to a logic unit 70. The D-latch flip-flop 28 is based on a first input signal 281 and a second input signal 282 generated by the logic unit 70 To determine an output 283, the logic block diagram of the logic unit 70 is shown in "Figure 8." Blocks 71 and 72 represent the upper bridge drive signal (Gate signal 1) and the lower bridge drive signal (Gate signal 2), respectively. 73 is a retarder, blocks 74 and 75 are an OR gate, and blocks 76 and 77 are an inverter. After the upper bridge drive signal (Gate signal 1) and the lower bridge drive signal (Gate signal 2) are input to the logic unit 70, a CLK signal, a /CLK signal, a DCLK signal, and a /DCLK signal are generated. Among them, the CLK signal, the DCLK signal The first input signal 281 is input to the D terminal of the D-type flip-flop 28, and the /CLK signal and /DCLK signal are the second input signal 282, which is input to the CLK terminal of the D-type flip-flop 28, " Fig. 9 is a schematic diagram of voltage output according to the embodiment of Fig. 7.

Please refer to "Figure 10", which is a schematic flowchart of an embodiment of the present invention. The upper bridge driving signal (Gate signal 1) and the lower bridge driving signal are regarded as a pulse width modulation signal (PWM signal), and when the state of the pulse width modulation signal changes (block 81), it will be detected Measure and adjust the source voltage (Vs) to rise or fall (Block 82), and cause the gate-to-source voltage (Vgs) to change (Block 83), and the gate-to-source voltage (Vgs) ) Will cause the drain-to-source voltage (Vds) to also change (block 84), and cause the gate-to-source voltage (Vgs) to ring (block 85), wherein the drain The change to the source voltage (Vds) will produce the Miller effect (block 86). Finally, since the source voltage (Vs) is adjusted based on the change of the pulse width modulation signal, the gate-to-source voltage (Vgs) surge is suppressed or reduced (block 87).

In summary, the present invention controls the source voltage to suppress the surge caused by the change of the gate-to-source voltage (Vgs), thereby solving the problem of crosstalk phenomenon of silicon carbide semiconductor power devices.

10: Controller 20: Upper arm circuit 21: first drive 22: The first silicon carbide power element 23: The first inductance 24: first resistance 25: The first capacitor 251: gate and drain capacitance 252: gate source capacitance 253: Drain source capacitance 26: The first amplifier 261: First input signal 27: second amplifier 271: second input signal 28: D-type flip-flop 281: The first input signal 282: second input signal 283: Output signal 30: lower arm circuit 31: second drive 32: The second silicon carbide power element 33: second inductor 34: second resistor 35: second capacitor 351: gate and drain capacitance 352: gate source capacitance 353: Drain source capacitance 41, 42, 43, 44, 45, 46, 47, 48, 491, 492, 493: cube 61, 62, 63, 64, 65, 66, 67, 68: cube 641: reverse and gate 642: Capacitor 643: Resistance 644: Reverse Gate 681: or gate 682: Capacitor 683: Resistance 684: Reverse Gate 70: Logic Unit 71, 72, 73, 74, 75, 76, 77, 81, 82, 83, 84, 85, 86, 87: cube Gate signal 1: Upper bridge drive signal Gate signal 2: lower bridge drive signal Vs: source voltage Vgs, Vgs’: gate-to-source voltage H: High level M: Middle level L: Low level

"Figure 1" is a schematic diagram of a circuit structure applied to a half-bridge circuit according to an embodiment of the present invention. "Figure 2" is a schematic diagram of the voltage output of the silicon carbide power device according to the present invention. "Figure 3" is a schematic diagram of a logic block of an embodiment of the present invention. "Figure 4" is a schematic diagram of a logic block of another embodiment of the present invention. "Figure 5" is a schematic diagram of the circuit structure of an embodiment of the present invention. "Figure 6" is a schematic diagram of a logic block of another embodiment of the present invention. "Figure 7" is a schematic diagram of the circuit structure of another embodiment of the present invention. "Figure 8" is the logical block diagram of "Figure 7". "Figure 9" is a schematic diagram of voltage output according to the embodiment of "Figure 7". "Figure 10" is a schematic diagram of the operation flow of an embodiment of the present invention.

Gate signal 1: Upper bridge drive signal

Gate signal 2: lower bridge drive signal

Vs: source voltage

Vgs, Vgs’: gate-to-source voltage

H: High level

M: Middle level

L: Low level

Claims (6)

A method for controlling a silicon carbide power element, the method comprising the following steps: providing a silicon carbide power element, the silicon carbide power element is controlled by a driver and has a gate-to-source voltage and a source voltage, the source voltage At least a high level, a low level, and an intermediate level between the high level and the low level; and the driver alternately outputs an upper bridge driving signal and a lower bridge driving signal to the silicon carbide A gate of a power device, wherein when the gate-to-source voltage rises according to the upper bridge drive signal or the lower bridge drive signal, the source voltage drops from the intermediate level to the low level or from The high level drops to the intermediate level, and when the gate-to-source voltage drops according to the upper bridge drive signal or the lower bridge drive signal, the source voltage rises from the low level to the intermediate level Or rise from the middle level to the high level. A silicon carbide power device controlled by a driver and having a gate-to-source voltage and a source voltage. The driver alternately outputs an upper bridge drive signal and a lower bridge drive signal to a gate of the silicon carbide power device , Wherein the source voltage drops according to the gate-to-source voltage rise, or the source voltage rises according to the gate-source voltage drop, thereby suppressing the gate-to-source voltage change. Of a sudden wave. The silicon carbide power device according to claim 2, wherein the source voltage has at least a high level, a low level, and an intermediate level between the high level and the low level, wherein, When the gate-to-source voltage rises according to the upper bridge drive signal or the lower bridge drive signal, the source voltage drops from the intermediate level to the low level or from the high level to the intermediate level When the gate-to-source voltage drops according to the upper bridge drive signal or the lower bridge drive signal, the source voltage rises from the low level to the intermediate level or from the intermediate level to the High level. A driving circuit, including: A silicon carbide power device having a gate-to-source voltage and a source voltage; a driver that controls the silicon carbide power device; and a compensation module that receives an alternate output from the driver The upper bridge drive signal and the lower bridge drive signal, and the compensation module causes the gate-to-source voltage to rise according to the upper-bridge drive signal and the lower-bridge drive signal to control the source voltage to drop, or according to the gate-to-source voltage The source voltage drops to control the source voltage to rise, thereby suppressing a surge caused by the gate-to-source voltage change. The driving circuit according to claim 4, wherein the compensation module includes a first compensation unit and a second compensation unit, and the first compensation unit detects the upper bridge driving signal and the lower bridge driving signal, and when the When the gate-to-source voltage rises based on the upper bridge drive signal or the lower bridge drive signal, the source voltage is controlled to drop, the second compensation unit detects the upper bridge drive signal and the lower bridge drive signal, and when the gate When the pole-to-source voltage is lowered based on the upper bridge driving signal or the lower bridge driving signal, the source voltage is controlled to rise. The driving circuit according to claim 4, wherein the compensation module includes a D-type flip-flop.

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