JP7384409B2 - Gate drive circuit and power supply circuit - Google Patents

Description

The present invention relates to a gate drive circuit that drives a gate terminal of a switching element, and particularly relates to a GaN-HEMT.

GaN-based high electron mobility transistors (GAN-HEMTs), which are next-generation power semiconductors, have lower on-resistance and better high-frequency characteristics than conventional Si (Silicon) devices. - Power supply circuits (power conversion circuits) using HEMT are expected to be used in a wide range of applications because they can be made smaller, lighter, and more efficient. Since only majority carriers are involved in conduction in GaN-HEMTs, there is no loss due to reverse recovery, making it possible to further improve the efficiency of power supply circuits such as PFC (Power Factor Correction) circuits.

However, GaN-HEMTs have problems that conventional Si devices do not have, such as a tendency to cause false ignition phenomena and a large reverse conduction loss during reflux operation.

The mechanism of the erroneous firing phenomenon will be explained with reference to FIGS. 10 and 11. FIG. 10 shows a half-bridge type power supply circuit (half-bridge circuit) 100 including two switching elements S1 and S2 that are GaN-HEMTs, and FIG. 11 shows a low-side switching element S2. When the high-side switching element S1 is turned on, a high dV/dt is generated at the drain terminal of the low-side switching element S2. Due to this high dV/dt, a mirror current i _miller flows to the gate resistance Rg and the internal gate resistance via the mirror capacitance Cgd of the switching element S2. If the gate voltage generated at this time exceeds the threshold voltage of the switching element S2, an unintended turn-on of the switching element S2, that is, an erroneous firing occurs.

While the threshold voltage of a conventional Si device is about 3V to 4V, the threshold voltage of a GaN-HEMT is low, about 1V to 2V, so that false firing is more likely to occur. If a false ignition phenomenon occurs in the power supply circuit and both high-side and low-side switching elements S1 and S2 are turned on at the same time, a through current will flow into the device, resulting in large power loss, and in the worst case, the device will be destroyed. Countermeasures against erroneous firing phenomena are essential.

As a conventional method to prevent erroneous ignition, a common method is to apply a negative voltage to the gate terminal to turn off the switching element.

Next, reverse conduction loss during reflux operation will be explained with reference to FIGS. 10 and 12. In the half-bridge circuit 100 shown in FIG. 10, during the dead time when the switching elements S1 and S2 are OFF, the current _ISD circulates through the loop of the inductor L, the capacitor Cout, and the switching element S2. As a result, the current _ISD reversely conducts the switching element S1.

FIG. 12(a) is an equivalent circuit when the switching element S2 is in reverse conduction, and FIG. 12(b) is a graph showing the reverse conduction characteristics of the GaN-HEMT. Since the GaN-HEMT is a horizontal device without a body diode, it is a device with reverse conduction characteristics that depend on V _GS . There are parasitic capacitances Cgd and Csd between the source and drain of the switching element S2. When V _GS is 0 V, the potential difference across Cgs is 0 V, and when current flows from the source at this time, parasitic capacitance Cgd and parasitic capacitance Csd are charged, and when V _GD reaches the threshold voltage V _th , the channel is closed. It is formed. Current flows through the formed channel and the voltage drop between the source and drain is expressed as V _SD =V _GD =V _th . This is the principle of reverse conduction in GaN-HEMT. When a negative voltage is applied to the gate, the parasitic capacitance Cgd is charged via the parasitic capacitance Cgs, resulting in a voltage drop equal to the voltage applied to the parasitic capacitance Cgs, that is, _VGS . Therefore, _VSD when a negative voltage is applied is expressed by the following equation.
V _SD = V _GD - V _GS (1)
For this reason, in the case of GaN-HEMTs, the conventional method of simply using a negative voltage to prevent false ignition causes an increase in reverse conduction loss.

On the other hand, a technique has been proposed in which a negative voltage is applied when the switching element is turned off, and 0V is applied during the subsequent dead time to prevent false firing phenomena and reduce reverse conduction loss (for example, Non-patent documents 1 to 3). That is, Non-Patent Documents 1 to 3 disclose configurations in which three levels of voltage, positive voltage, negative voltage, and 0V, can be applied to the gate terminal of a switching element. 13 to 15 show gate drive circuits 200, 300, and 400 described in Non-Patent Documents 1 to 3, respectively.

Zhi-Liang Zhang, "Three-Level Gate Drivers for eGaN‐HEMTs in Resonant Converters", 2017 Achim Seidel, "A Fully Integrated Three-Level 11.6nC Gate Driver Supporting GaN Gate Injection Transistors", 2018 "GaN-Tr Application Note (PGA26E07BA)", Panasonic Semiconductor Solutions Co., Ltd, 2019

A gate drive circuit 200 described in Non-Patent Document 1 shown in FIG. 13 is connected to a mid-level generator 201 in order to drive the gate terminal of the switching element S1 at three levels. The intermediate voltage generation circuit 201 uses a power supply V _X -V _Z that is different from the power supply voltage V _CC used for the gate drive circuit 200. That is, in Non-Patent Document 1, there is a problem that the circuit area increases because an additional power supply V _X -V _Z is required.

The gate drive circuit 300 described in Non-Patent Document 2 shown in FIG. 14 requires only the power supply VDRV to drive the gate terminal of the switching element S1. It is also connected to the terminal. Therefore, as shown by the broken line arrow, there is a possibility that the source current of the switching element S1 flows into the gate drive circuit 300, which poses a reliability problem.

A gate drive circuit 400 described in Non-Patent Document 3 shown in FIG. 15 includes resistors Rin, Rg_on, Rg_off, and a capacitor Cs in addition to two transistors T401 and T402. Since the resistance value of the resistor Rin is high (1500Ω) and the resistance values of the resistors Rg_on and Rg_off are low, when the switching element S1 is turned on, a current flows through the resistor Rg_on and the capacitor Cs, charge is stored in the capacitor Cs, and the resistance value of the resistors Rg_on and Rg_off is low. When charging is completed, a current flows through the resistor Rin. At the time of turn-off, the capacitor Cs is discharged and a current flows from the capacitor Cs to the resistor Rg_off, so that a negative voltage is applied to the gate terminal of the switching element S1 due to the potential difference in the capacitor Cs. When the discharge of the capacitor Cs ends, the gate voltage of the switching element S1 becomes 0V. Thereafter, at the time of turn-on, since the potential difference in the capacitor Cs is 0V, a positive voltage is immediately applied to the gate terminal of the switching element S1.

However, if the capacitor Cs is turned on after being turned off but before the discharge of the capacitor Cs is completed, there will be a potential difference between the electrodes of the capacitor Cs, so the gate voltage of the switching element S1 will be a positive voltage only after the capacitor Cs is recharged. (Since the resistance value of the resistor Rin is very high, current flows through the capacitor Cs and no current flows through the resistor Rin until the capacitor Cs is recharged.) Therefore, there is a problem that the gate drive circuit 400 is not suitable for high frequency operation.

The present invention has been made to solve the above problems, and can prevent false ignition phenomena and reduce reverse conduction loss, and has a simple configuration, high reliability, and high frequency operation. The purpose of this invention is to provide a gate drive circuit that is highly efficient.

In order to solve the above problems, a gate drive circuit according to the present invention is a gate drive circuit that drives a gate terminal of a switching element, and includes first to fifth transistors and a capacitor, and includes a first transistor and a capacitor. The first controlled terminal of the first transistor and the first controlled terminal of the third transistor are connected to the first potential, and the second controlled terminal of the first transistor is connected to the first controlled terminal of the second transistor. a second controlled terminal of the second transistor is connected to a second potential lower than the first potential; A controlled terminal is connected to the gate terminal of the switching element and a first controlled terminal of the fourth transistor, and a second controlled terminal of the fourth transistor is connected to the second electrode of the capacitor and the first controlled terminal of the fourth transistor. The second controlled terminal of the fifth transistor is connected to the second potential.

According to the present invention, it is possible to provide a gate drive circuit that can prevent false ignition phenomena and reduce reverse conduction loss, has a simple configuration, is highly reliable, and is capable of high-frequency operation.

FIG. 1 is a circuit diagram of a gate drive circuit according to an embodiment of the present invention. These are waveforms of a control signal that controls a gate drive circuit, a gate-source voltage, and a drain-source voltage of a switching element. FIG. 3 is a circuit diagram showing the operation of the gate drive circuit at turn-on. FIG. 3 is a circuit diagram showing the operation of the gate drive circuit during turn-off. FIG. 3 is a circuit diagram showing the operation of the gate drive circuit during dead time. FIG. 6 is a circuit diagram of a gate drive circuit according to a modification of the present invention. FIG. 2 is a circuit diagram of a conventional gate drive circuit used as a comparative example of the present invention. FIG. 2 is a circuit diagram of a lower half-bridge circuit. These are the waveforms of the gate-source voltage and drain-source voltage of the switching element during turn-off. FIG. 2 is a circuit diagram of a half-bridge type power supply circuit. FIG. 3 is an explanatory diagram of a false firing phenomenon. FIG. 3 is an explanatory diagram of reverse conduction loss during reflux operation. FIG. 2 is a circuit diagram of a conventional gate drive circuit. FIG. 2 is a circuit diagram of a conventional gate drive circuit. FIG. 2 is a circuit diagram of a conventional gate drive circuit.

Embodiments of the present invention will be described below with reference to the accompanying drawings. Note that the present invention is not limited to the embodiments described below.

(Circuit configuration)
FIG. 1 is a circuit diagram of a gate drive circuit 1 according to an embodiment of the present invention. Gate drive circuit 1 drives the gate terminal of switching element S1, which is a GaN-HEMT.

The gate drive circuit 1 includes first to sixth transistors T1 to T6, a capacitor Csub, and a gate resistor Rg. The first and third transistors T1 and T3 are PMOS transistors, and the second and fourth to sixth transistors T2 and T4 to T6 are NMOS transistors.

The source terminal (first controlled terminal) of the first transistor T1 and the source terminal (first controlled terminal) of the third transistor T3 are connected to a power supply potential (first potential) VDD. The drain terminal (second controlled terminal) of the first transistor T1 is connected to the drain terminal (first controlled terminal) of the second transistor T2 and the first electrode of the capacitor Csub. A source terminal (second controlled terminal) of the second transistor T2 is connected to a ground potential (second potential). The drain terminal (second controlled terminal) of the third transistor T3 is connected to the gate terminal of the switching element S1 and the drain terminal (first controlled terminal) of the fourth transistor T4. The source terminal (second controlled terminal) of the fourth transistor T4 is connected to the second electrode of the capacitor Csub and the drain terminal (first controlled terminal) of the fifth transistor T5. The source terminal (second controlled terminal) of the fifth transistor T5 is connected to the ground potential via the sixth transistor T6. That is, the source terminal of the fifth transistor T5 is connected to the drain terminal of the sixth transistor T6, and the source terminal of the sixth transistor T6 is connected to the ground potential.

As described above, the gate drive circuit 1 has a simple configuration because it has six transistors, one capacitor, and two control signals. Further, unlike the conventional gate drive circuit 200 shown in FIG. 13, since additional power supplies VX-VZ are not required, the circuit area can be small. Furthermore, unlike the conventional gate drive circuit 300 shown in FIG. 14, the gate drive circuit 1 is connected only to the gate terminal of the switching element S1, so that current does not flow from the switching element S1 to the gate drive circuit 1. There are no problems with reliability.

(Operating principle)
The operating principle of the gate drive circuit 1 will be explained below. A control signal SigA is applied to each gate terminal of the first to fourth transistors T1 to T4, and a control signal SigB is applied to each gate terminal of the fifth and sixth transistors T5 and T6. FIG. 2 shows waveforms of the control signals SigA, SigB, the gate-source voltage V _GS and the drain-source voltage V _DS of the switching element S1.

(turn on)
At time t1, control signal SigB is at high level, and control signal SigA changes from high level to low level. As a result, transistors T1, T3, T5, and T6 are turned ON, and as shown in FIG. flows to the gate terminal of. The other current flows to ground potential through transistor T1, capacitor Csub, and transistors T5 and T6. At this time, charge is accumulated in the capacitor Csub, and a potential difference is generated.

(turn off)
At time t2, control signal SigA becomes high level, and control signal SigB becomes low level. As a result, transistors T1, T3, T5, and T6 are turned off, while transistors T2 and T4 are turned on. As a result, as shown in FIG. 4, the charge in the capacitor Csub is discharged, and a current flows from the gate terminal of the switching element S1 to the ground potential through the transistor T4, the capacitor Csub, and the transistor T2. As a result, the gate-source voltage _VGS of the switching element S1 becomes a negative voltage, thereby preventing an erroneous firing phenomenon.

(dead time)
At time t3, control signal SigB is raised to high level. As a result, the transistors T5 and T6 are turned on, and as shown in FIG. 5, a current flows from the ground potential on the transistor T6 side to the gate terminal of the switching element S1, and the gate-source voltage _VGS is clamped to 0V. Therefore, reverse conduction loss during reflux operation is reduced.

As described above, by turning ON/OFF the transistors T1 to T6, three levels of voltage, positive voltage, negative voltage, and 0V, are applied to the gate terminal of switching element S1. This makes it possible to prevent erroneous ignition phenomena and reduce reverse conduction loss.

After the dead time, at time t4, when the control signal SigA falls to a low level, the switching element S1 is turned on, and the current shown in FIG. 4 flows. Here, even if the discharge of the capacitor Csub is not completed and the charge remains, the current passing through the capacitor Csub does not flow to the gate terminal of the switching element S1, as shown by the broken line arrow, and this current is Separately, a current indicated by a solid arrow flows to the gate terminal of the switching element S1. Therefore, even if the current indicated by the broken line arrow stops during the recharging period of the capacitor Csub, the driving of the switching element S1 is not affected. That is, even if the switching element S1 is turned on before the capacitor Csub is completely discharged, the switching element S1 operates normally, so high frequency operation from several hundred kHz to several MHz is possible.

On the other hand, in a conventional gate drive circuit 400 shown in FIG. 15, a capacitor Cs is directly connected to the gate terminal of the switching element S1. Therefore, if a switching operation is performed before the capacitor Cs is completely discharged during the off period, the switching element S1 cannot be turned on unless the capacitor Cs is recharged, and the turn-on time becomes longer. Therefore, when operated at a high frequency, the high-speed switching performance of the GaN-HEMT cannot be fully exploited.

As described above, the gate drive circuit 1 according to the present embodiment can prevent false firing phenomena and reduce reverse conduction loss, has a simple configuration, is highly reliable, and is capable of high frequency operation. It has the following characteristics.

(Modified example)
Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various changes can be made without departing from the spirit thereof.

FIG. 6 is a circuit diagram of a gate drive circuit 1' according to a modification of the present invention. The gate drive circuit 1' has a configuration in which the gate drive circuit 1 shown in FIG. 1 further includes first and second resistors R1 and R2. The first resistor R1 is connected to the gate terminal (control terminal) of the fifth transistor T5, and the second resistor R2 is connected to the gate terminal (control terminal) of the sixth transistor T6.

As shown in FIG. 2, by raising the control signal SigB to a high level at time t3, the gate-source voltage _VGS of the switching element S1 is clamped to 0V, but in reality it momentarily exceeds about 1V. Shoot (0.98V in the example below (FIG. 9)). In the gate drive circuit 1' shown in FIG. 6, the rise speed of the control signal SigB is slowed down by the first and second resistors R1 and R2, and the time it takes for the transistors T5 and T6 to switch from OFF to ON becomes longer. This suppresses the rise in voltage V _GS due to overshoot, and can reliably prevent voltage V _GS from exceeding the threshold voltage of switching element S1.

Note that in the gate drive circuit 1 shown in FIG. 1, one of the fifth and sixth transistors T5 and T6 may be omitted.

In the example, it was evaluated whether the gate drive circuit 1 of the present invention shown in FIG. 1 can prevent false firing phenomena and reduce reverse conduction loss compared to conventional gate drive circuits. A 4.7 nF ceramic capacitor was used as the capacitor Csub of the gate drive circuit 1.

As shown in FIG. 7, the conventional gate drive circuit uses a gate drive circuit 11 including a PMOS transistor T11, an NMOS transistor T12, and a gate resistor Rg. Specifically, a gate drive circuit (SI8275GB) manufactured by SILABS was used, and the negative voltage VEE was set to -2.5V.

In addition, as a power supply circuit for evaluation, a lower half bridge circuit shown in FIG. 8 was used. As the switching elements S1 and S2 constituting the half-bridge circuit, GaN-HEMT (GS66504B-E01 (V _{th (typ)} = 1.3 V) manufactured by GaN Systems was used. The input voltage Vin was 50 V, the input current was 4 A, the inductance of the inductor L was 100 μH, the switching frequency was 500 kHz, and the dead time was 100 ns.

In the example, the gate drive circuit 1 shown in FIG. 1 was used as the two gate drive circuits that drive the switching elements S1 and S2. In the comparative example, the gate drive circuit 11 shown in FIG. 7 was used for the two gate drive circuits. Then, the gate-source voltage Vgs and drain-source voltage Vds of the low-side switching element S2 were measured.

FIG. 9 shows the waveforms of the voltages Vgs and Vds of the switching element S2 at the time of turn-off. In the example using the gate drive circuit 1, since the switching element S2 is driven with a negative voltage at the time of turn-off, the gate voltage oscillation due to the mirror current that occurs when switching the switching element S1 is suppressed to 0.98V, and the threshold value is The voltage (1.3V) was not exceeded. On the other hand, in the comparative example using the gate drive circuit 11, the gate voltage oscillation was 1.6V, which exceeded the threshold voltage.

In addition, the evaluation results of voltage drop Vsd and reverse conduction loss during dead time were 3.77 V and 11.4 W, respectively, for the conventional gate drive circuit 11, whereas the gate drive circuit 1 of the present invention had 2. It was .34V and 8.7W. In this way, the gate drive circuit 1 reduced the reverse conduction loss by 23.7% compared to the gate drive circuit 11 by suppressing the voltage drop.

As described above, it has been found that the gate drive circuit 1 of the present invention can prevent erroneous firing and reduce reverse conduction loss.

The gate drive circuit according to the present invention is suitable for driving a GaN-HEMT, but is not limited thereto, and can also be applied to, for example, driving a Si-based semiconductor device.

1 Gate drive circuit 1' Gate drive circuit 2 Gate drive circuit Csub Capacitor R1 First resistor R2 Second resistor Rg Gate resistor S1 Switching element S2 Switching element T1 First transistor T2 Second transistor T3 Third transistor T4 Fourth transistor T5 Fifth transistor T6 Sixth transistor

Claims (7)

A gate drive circuit that drives a gate terminal of a switching element,
comprising first to fifth transistors and a capacitor,
a first controlled terminal of the first transistor and a first controlled terminal of the third transistor are connected to a first potential;
a second controlled terminal of the first transistor is connected to a first controlled terminal of the second transistor and a first electrode of the capacitor;
a second controlled terminal of the second transistor is connected to a second potential that is lower than the first potential;
a second controlled terminal of the third transistor is connected to the gate terminal of the switching element and the first controlled terminal of the fourth transistor;
a second controlled terminal of the fourth transistor is connected to the second electrode of the capacitor and the first controlled terminal of the fifth transistor;
A gate drive circuit, wherein a second controlled terminal of the fifth transistor is connected to a second potential. The gate drive circuit according to claim 1, further comprising a first resistor connected to a control terminal of the fifth transistor. further comprising a sixth transistor;
3. The gate drive circuit according to claim 1, wherein the second controlled terminal of the fifth transistor is connected to the second potential via the sixth transistor. 4. The gate drive circuit according to claim 3, further comprising a second resistor connected to a control terminal of the sixth transistor. the first and third transistors are PMOS transistors,
5. The gate drive circuit according to claim 1, wherein the second, fourth to sixth transistors are NMOS transistors. a switching element;
and a gate drive circuit that drives a gate terminal of the switching element,
A power supply circuit, wherein the gate drive circuit is the gate drive circuit according to claim 1. 7. The power supply circuit according to claim 6, wherein the switching element is a GaN-based high electron mobility transistor.

Images