US20190158084A1 - Method and electronic circuit for driving a transistor device - Google Patents
Method and electronic circuit for driving a transistor device Download PDFInfo
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- US20190158084A1 US20190158084A1 US16/194,013 US201816194013A US2019158084A1 US 20190158084 A1 US20190158084 A1 US 20190158084A1 US 201816194013 A US201816194013 A US 201816194013A US 2019158084 A1 US2019158084 A1 US 2019158084A1
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
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- 238000010586 diagram Methods 0.000 description 4
- 238000001816 cooling Methods 0.000 description 3
- 230000003213 activating effect Effects 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/06—Modifications for ensuring a fully conducting state
- H03K17/063—Modifications for ensuring a fully conducting state in field-effect transistor switches
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/567—Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
- H03K2217/0027—Measuring means of, e.g. currents through or voltages across the switch
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
- H03K2217/0036—Means reducing energy consumption
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
- H03K2217/0081—Power supply means, e.g. to the switch driver
Abstract
Description
- This disclosure in general relates to a method and an electronic circuit for driving a transistor device.
- Voltage controlled transistor devices such as MOSFETs (Metal Oxide Semiconductor Field-Eflfect-Transistor) or IGBTs (Insulated Gate Bipolar Transistors) are widely used as electronic switches in various types of applications. Conduction losses that occur in an on-state of the transistor device are dependent on an on-resistance of the transistor device and a load current flowing through the transistor device. The “on-resistance” is the electrical resistance of the transistor device in the on-state. The conduction losses are proportional to the on-resistance and the square of the load current. In high current applications such as electric vehicles, where load currents of several hundred amperes may occur, such conduction losses can be considerable. There is therefore a need to reduce the conduction losses.
- One example relates to a method. The method includes driving a transistor device in an on-state by applying a drive voltage higher than a threshold voltage of the transistor device to a drive input, and adjusting a voltage level of the drive voltage based on a load signal that represents a current level of a load current through the transistor device. The current level is an actual current level or an expected current level of the load current.
- Another example relates to an electronic circuit with a drive circuit. The drive circuit is configured to generate a drive voltage higher than a threshold voltage of a transistor device at a drive output configured to have a drive input of the transistor device connected thereto, and adjust a voltage level of the drive voltage based on a load signal that represents a current level of a load current through the transistor device. The current level is an actual current level or an expected current level of the load current.
- Examples are explained below with reference to the drawings. The drawings serve to illustrate certain principles, so that only aspects necessary for understanding these principles are illustrated. The drawings are not to scale. In the drawings the same reference characters denote like features.
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FIG. 1 shows one example of an electronic circuit including a transistor device and a drive circuit configured to drive the transistor device; -
FIG. 2 shows a flowchart that illustrates one example of a method for driving the transistor device in an on-state; -
FIG. 3 is a graph that illustrates a dependency of an on-resistance of the transistor device on a drive voltage received at a drive input of the transistor device; -
FIG. 4 shows one example of a timing diagram of a load current through the transistor device; -
FIG. 5 illustrates one example of adjusting a voltage level of the drive voltage dependent on a load signal; -
FIG. 6 illustrates another example of adjusting a voltage level of the drive voltage dependent on a load signal; -
FIG. 7 illustrates yet another example of adjusting a voltage level of the drive voltage dependent on a load signal; -
FIG. 8 illustrates one example of adjusting the drive voltage when the load signal exceeds a maximum threshold; -
FIG. 9 illustrates obtaining the load signal based on measuring the load current; -
FIG. 10 illustrates obtaining the load signal based on measuring a voltage across a load path of the transistor device; -
FIG. 11 illustrates one example in which the load signal is obtained from a load connected in series with the transistor device; -
FIG. 12 shows one example of the drive circuit; -
FIG. 13 shows another example of the drive circuit; -
FIG. 14 shows one example of a driver included in the drive circuits illustrated inFIGS. 12 and 13 ; -
FIG. 15 shows one example of an adjustable voltage source; -
FIG. 16 shows another example of an adjustable voltage source; -
FIG. 17 shows a drive circuit with a boost circuit; -
FIG. 18 shows one example of the boost circuit; and -
FIG. 19 shows timing diagrams that illustrate operation of the boost circuit shown inFIG. 18 . - In the following detailed description, reference is made to the accompanying drawings. The drawings form a part of the description and for the purpose of illustration show examples of how the invention may be used and implemented. It is to be understood that the features of the various embodiments described herein may be combined with each other, unless specifically noted otherwise.
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FIG. 1 shows one example of an electronic circuit that includes atransistor device 1 and adrive circuit 2 configured to drive thetransistor device 1. Thetransistor device 1 is a voltage controlled transistor device that is configured to switch on or off dependent on a drive voltage VGS received at a drive input of thetransistor device 1. Thetransistor device 1 switches on (enters an on-state) when the drive voltage VGS exceeds a threshold voltage (which is referred to as Vth in the following) and switches off (enters an off-state) when the drive voltage VGS falls below the threshold voltage Vth. Thetransistor device 1 includes acontrol node 11 and a load path between afirst load node 12 and asecond load node 13. In the example shown inFIG. 1 , the drive input of thetransistor device 1 includes thecontrol node 11 and thefirst load node 12, that is, the drive voltage VGS is received by thetransistor device 1 between thecontrol node 11 and thefirst load node 12. This, however, is only an example. According to another example (not shown) the drive input includes the control node of the transistor device and a further node separate from the first load node and the second load node of the transistor device. - Just for the purpose of illustration, the
transistor device 1 shown inFIG. 1 is a MOSFET, more specifically, a n-type. A gate node of this MOSFET forms thecontrol node 11, a source node forms thefirst load node 12, and a drain node forms thesecond load node 13. According to one example, theMOSFET 1 is a silicon (Si) based MOSFET. That is, the MOSFET is fabricated based on monocrystalline silicon. According to another example, the MOSFET is a silicon carbide (SiC) based MOSFET. In this example, the MOSFET is manufactured based on monocrystalline silicon carbide. Implementing the transistor device as an n-type MOSFET is only an example. According to another example, thetransistor device 1 is implemented as a p-type MOSFET, according to yet another example, the transistor device is implemented as an IGBT. According to one example, thetransistor device 1 has a voltage blocking capability of several hundred volts. According to one example, the voltage blocking capability is higher than 400 V, higher than 600 V, or higher than 800 V. The “voltage blocking capability” is defined as the voltage level of a load voltage between thesecond load node 13 and thefirst load node 12 that thetransistor device 1 can withstand in the off-state without being damaged or destroyed. - Referring to
FIG. 1 , thedrive circuit 2 includes a drive output configured to be connected to thedrive input transistor device 1 and to provide the drive voltage VGS. In this example, the drive output includes afirst output node 21 configured to be coupled to thecontrol node 11 and asecond output node 22 configured to be coupled to the second load node 12 (or an equivalent circuit node of the transistor device 1). Thedrive circuit 2 is configured to drive thetransistor device 1, either in the on-state by generating the drive voltage VGS with a voltage level higher than the threshold voltage Vth, or in the off-state by generating the drive voltage VGS with a voltage level lower than the threshold voltage Vth. Whether thedrive circuit 2 drives thetransistor device 1 in the on-state or in the off-state can be dependent on various parameters. According to one example (illustrated in dashed lines inFIG. 1 ) thedrive circuit 2 receives a control signal SCTRL and operates thetransistor device 1 in the on-state or in the off-state dependent on the control signal SCTRL. According to another example, thedrive circuit 2 operates thetransistor device 1 in the on-state whenever a supply voltage VSUPPLY received at supply nodes 23, 24 (illustrated in dashed lines inFIG. 1 ) exceeds a predefined voltage level. The supply voltage VSUPPLY is used in the drive circuit to generate the drive voltage VGS. - Independent of how the drive circuit is triggered to operate the
transistor device 1 in the on-state, referring toFIG. 2 , driving thetransistor device 1 in the on-state includes applying the drive voltage VGS at thedrive input FIG. 2 ), and adjusting the voltage level of the drive voltage based on a load signal SL (102 inFIG. 2 ). In the electronic circuit shown inFIG. 1 , the load signal SL is received by thedrive circuit 2. The load signal SL represents a current level of a load current IL through thetransistor device 1. This current level may be an actual current level, that is, a current level of an instantaneous current IL flowing through thetransistor device 1. According to another example, the load signal Si, represents an expected current level of the load current IL. In this example, the voltage level of the drive voltage VGS may already be adjusted before the current level of the load current IL changes. Examples of how the load signal SL can be generated are explained herein further below. - According to one example, driving the
transistor device 1 in the on-state includes driving the transistor device in the on-state for more than one second (1 s), more than one minute, more than ten minutes, more than one hour (1 h), or even more than one day (1 d). In particular, adjusting the voltage level of the drive voltage based on the load signal SL includes increasing the voltage level of the drive voltage VGS when the load signal SL indicates that the load current has increased or will increase. Such increasing of the drive voltage VGS in the on-state when the load current IL increases can help to reduce conduction losses occurring in thetransistor device 1. These conduction losses, in the case of a unipolar transistor such as, e. g., a MOSFET, are essentially given by -
P C =R DS _ ON ·I L 2 (1), - where PC denotes the conduction losses, RDS _ ON denotes an on-resistance of the
transistor device 1, and IL denotes the load current. As can be seen from equation (1), the conduction losses PC are proportional to the on-resistance RDS _ ON of thetransistor device 1 and proportional to the square of the load current. The “on-resistance” of thetransistor device 1 is the electrical resistance of thetransistor device 1 in the on-state. This on-resistance RDS _ ON is dependent on the drive voltage VGS and, within a given range of the drive voltage VGS, decreases as the drive voltage VGS increases. This is schematically illustrated inFIG. 3 , which shows a graph that illustrates a dependency of the on-resistance RDS _ ON the drive voltage VGS.FIG. 3 illustrates the on-resistance RDS _ ON over the drive voltage VGS in a voltage range of the drive voltage VGS that is higher than the threshold voltage Vth. As can be seen fromFIG. 3 , there is a range of the drive voltage VGS in which the on-resistance RDS _ ON decreases as the drive voltage VGS increases. - Increasing the drive voltage VGS, however, may reduce the statistical lifetime or increase the failure rate. Each voltage level of the drive voltage VGS is associated with a statistical lifetime and a failure rate. That is, the probability that a transistor device will fail within the statistical lifetime is given by the failure rate. In other words. in a plurality of samples, a percentage of these, given by the failure rate, will fail within the statistical lifetime. For example, the probability that the
transistor device 1 will fail within a predefined time period (statistical lifetime) T1 when operated with a drive voltage having a first voltage level VGS1 is p1. Operating the transistor device with the drive voltage having a second voltage level VGS2 higher than the first voltage level VGS1 may increase the failure rate. That is, a probability p2 that thetransistor device 1, when operated with the higher drive voltage VGS2, will fail within the first time period T1 is higher than the first probability p1. This is equivalent to a reduction of the statistical lifetime. That is, a time period T2 for which thetransistor device 1 can be operated in the on-state at the higher gate voltage VGS2 and has first probability p1 of failing is shorter than the first time period T1. For this reason, it may be undesirable to permanently operate thetransistor device 1 at a high drive voltage such as the higher voltage VGS2. - However, in many applications high load current peaks that may require an increase of the drive voltage VGS in order to at least partially counteract an increase of the conduction losses are relatively short as compared to an overall duration of the on-state. This is schematically illustrated in
FIG. 4 that shows a timing diagram of the load current IL. In this example, the load current IL is below a certain current level IL1 for most of the time. Nevertheless, there are several current peaks that exceed this current level IL1. A signal waveform of the type shown inFIG. 4 is the typical waveform of an overall current flowing into a motor of an electric vehicle. The time periods with the current peaks represent those time periods in which the vehicle accelerates. - Referring to equation (1), the conduction losses increase proportionally to the square of the load current. The conduction losses are associated with a heating of the
transistor device 1. In order to avoid overheating, thetransistor device 1 may including cooling means (not shown in the drawings) such as, for example, a heat conducting carrier. Dimensions of this cooling system may be designed such that the cooling system is capable of handling dissipated power that occurs when the load current is at a maximum level, as may occur during the current peaks shown inFIG. 4 , although these current peaks may not be of a long duration. An increase of the dissipated power may increase the temperature of thetransistor device 1. wherein such increase of the temperature may result in an increase of the on-resistance which, in turn, further increases the dissipated power. Thus, a kind of positive feedback takes place. Increasing the gate-source voltage VGS when the load current increases reduces the on-resistance. This may help to avoid or at least reduce an increase of the dissipated power, so as to avoid or reduce the positive feedback described above. - The voltage level of the drive voltage VGS may be varied based on the load signal SL in various ways. Some examples are explained with reference to
FIGS. 5, 6 and 7 herein below. Each of these figures illustrates the drive voltage VGS over the load signal SL in the on-state of the transistor device. In each of these examples, the voltage level of the drive voltage VGS is selected from an interval that ranges from a minimum level VGS _ MIN to a maximum level VGS _ MAX. - In the example shown in
FIG. 5 , only two different voltage levels are used to drive thetransistor device 1 in the on-state, the minimum level VGS _ MIN, when the load signal SL is below a first threshold SL1, and the maximum level VGS _ MAX, when the load signal SL exceeds the first level SL1. Optionally, changing the voltage level based on the load signal SL includes a hysteresis, so that the drive voltage VGS increases from the minimum level VGS _ MIN to the maximum level VGS _ MAX when the load signal SL exceeds the first threshold SL1, and the drive voltage VGS changes from the maximum level VGS _ MAX back to the minimum level VGS _ MIN when the load signal SL falls below a threshold SL1′, that is, lower than the first threshold SL1. - According to one example, the minimum level VGS _ MIN and the maximum level VGS _ MIN are such that the statistical lifetime of the
transistor device 1 associated with the maximum level VGS _ MAX is shorter than a statistical lifetime associated with the minimum level VGS _ MIN. Referring to the above, the statistical lifetime is associated with a given failure rate, that is, the statistical lifetime is the time period in which, from a plurality of samples of transistor devices of the same type, a percentage, given by the given failure rate, will fail. According to one example, the given failure rate associated with the statistical lifetime is less than 10−2 (1%), less than 10−3 (0.1%), less than 10−4, less than 10−5, less than 10−6 (1 ppm, part per million), or even below. According to one example, the minimum level VGS _ MIN is selected such that the statistical lifetime (associated with the given failure rate) is more than 10 years, more than 50 years, or more than 100 years. In the following, TL(VGS _ MIN, pFAILURE) denotes the statistical lifetime associated with the minimum gate-source voltage VGS _ MIN (that is, when thetransistor device 1 is operated with the minimum gate-source voltage VGS _ MIN) and the given failure rate pFAILURE. According to one example, the maximum level VGS _ MAX of the gate-source voltage is such that a statistical lifetime TL(VGS _ MAX, pFAILURE) associated with the maximum level VGS _ MAX and the given failure rate pFAILURE is less than the statistical lifetime TL(VGS _ MIN, pFAILURE) associated with the minimum level, that is, -
T L(V GS _ MAX ,p FAILURE)=c·T L(V GS _ MIN ,p FAILURE) (2), - where c is a constant smaller than 1 (c<1). According to one example, the failure rate pFAILURE is selected from between 10−2 and 10−6 and maximum level VGS _ MAX is such that c is less than 0.1 (10−1), less than 0.01 (10−2), or even less than 0.001 (10−3). The statistical lifetime TL(VGS _ MAX, pFAILURE) associated with the maximum level VGS _ MAX may reach or may be even lower than an expected operational lifetime of an application in which the transistor device is employed. However, due to the short time duration for which the maximum level VGS _ MAX needs to be applied to the
transistor device 1, this significantly lower statistical lifetime associated with the maximum level should not cause the transistor device to fail within the expected operational lifetime of the application. -
FIG. 6 shows a modification of the example shown inFIG. 5 . In the example shown inFIG. 6 , the load signal SL is not compared with only one threshold SL1, as shown inFIG. 5 , but is compared with N thresholds, where N is an integer greater than one (N>1), and the transistor device is driven using one of N+1 different voltage levels based on comparing the load signal SL with theses N thresholds. Just for the purpose of explanation, N=3 in the example shown inFIG. 6 . In this example, the drive voltage VGS has a first level, which is the minimum level VGS _ MIN in this example, when the load signal SL is below a first threshold SL1. Further, the drive voltage VGS has a second level VGS _ 2 when the load signal SL is between the first level SL1 and a second level SL2, a third level VGS _ 3 when the load signal SL is between the second level SL2 and a third level (the N-th level in this example), and a fourth level ((N+1)-th level) when the load signal SL exceeds the third level SLN. The fourth level corresponds to the maximum level VGS _ MAX in this example. As in the example shown inFIG. 5 , the drive voltage VGS may change between the individual voltage levels in accordance with hysteresis curves. That is, the drive voltage VGS may change from the second level VGS _ 2 back to the first level VGS _ MIN when the load signal SL falls below a threshold lower than the first threshold SL1, the driver voltage VGS may change from the third level VGS _ 3 back to the second level VGS _ 2 when the load signal SL falls below a threshold SL2′ lower than the second threshold SL2, and so on. Further, SL1<SL2<SL3<SLN and VGS _ MIN<VGS _ 2<VGS _ 3<VGS _ MAX. - In the example shown in
FIG. 7 , the voltage level of the gate voltage VGS continuously increases between the minimum level VGS _ MIN and the maximum level VGS _ MAX when the load signal SL is between a lower threshold SLL and an upper threshold SLH. When the load signal SL is below the lower threshold SLL, the drive voltage VGS has the minimum level VGS _ MIN, and when the load signal SL is higher than the upper threshold SLH the drive voltage VGS has the maximum level VGS _ MAX. In the example shown inFIG. 7 , the voltage level of the drive voltage VGS linearly increases as the load signal SL increases between the lower level SLL and the upper level SLH. This, however, is only an example. The voltage level of the drive voltage VGS may increase in any other way as well. Further examples of how the drive voltage VGS may increase based on the load signal are illustrated in dashed and dotted lines inFIG. 7 . - According to one example illustrated in
FIG. 8 , the voltage level of the drive voltage VGS may be reduced to the minimum level VGS _ MIN when the load signal SL exceeds a predefined maximum level SLX. This change of the drive voltage VGS to the minimum level VGS _ MIN is independent of how the drive voltage VGS may have increased to the maximum level VGS _ MAX. The drive scheme illustrated inFIG. 8 may therefore be combined with any of the drive schemes explained with reference toFIGS. 5,6 and 7 . - Referring to the above, the load signal SL represents a current level of the load current IL, wherein the load signal SL may represent an instantaneous current level of the load current IL or an expected current level of the load current. Examples of how the load signal SL may be generated are explained with reference to
FIGS. 9, 10 and 11 below. - According to one example shown in
FIG. 9 , generating the load signal SL includes measuring the load current IL using acurrent sensor 31. Thecurrent sensor 31 can be any type of current sensor suitable for measuring the load current IL flowing through thetransistor device 1. Thecurrent sensor 31 is, for example, a current sensor integrated in thetransistor device 1, a current sensor having a shunt resistor connected in series with the load path of thetransistor device 1, a current sensor including a magnetic sensor like a Hall sensor or a sensor using magneto-resistive effects, an inductive current sensor, or the like. According to one example, the load signal SL generated by thecurrent sensor 31 is monotonic dependent or even proportional to the load current IL. - According to another example shown in
FIG. 10 , generating the load signal SL includes measuring a load path voltage V1 (which, in a MOSFET, is usually referred to as drain-source voltage) using a voltage sensor. Any type of voltage sensor suitable for measuring the load path voltage can be used. The load path voltage V1 does not directly represent the load current IL but is given by the on-resistance RON _ DS multiplied with the load current IL, V1=RDS _ ON·IL. Nevertheless, the load path voltage V1 indicates when the load current IL increases because such an increase of the load current IL results in a corresponding increase of the load path voltage V1. As the on-resistance RON _ DS increases as the temperature increases, e. g., due to higher power dissipation in the transistor device, generating the load signal SL based on the load path voltage V1 also helps to reduce losses and thus reduce the operating temperature of thetransistor device 1. Generating the load signal SL based on the load path voltage may, in particular, be used in connection with a method that adjusts two or more discrete voltage levels of the drive voltage VGS. Examples of such methods are illustrated inFIGS. 5 and 6 . - According to another example shown in
FIG. 11 , the load signal SL is provided by aload 42 connected in series with the load path 12-13 of thetransistor device 1. In this example, a series circuit with thetransistor device 1 and the load is connected to a DC (direct current) power source such as a battery. Theload 42 can be any type of electrical load and may include further transistor devices. According to one example, theload 42 includes an electrical motor and an inverter configured to drive the motor using a DC voltage V41 received from theDC power source 41 via thetransistor device 1. In the circuit shown inFIG. 11 , thetransistor device 1 may act as a battery switch which only serves to connect theload 42 to thebattery 41 or to disconnect theload 42 from thebattery 41. The load current IL is only defined by the operation of theload 42. That is, dependent on an operating state of theload 42. the load current IL, in the on-state of thetransistor device 1. may vary within a great range. The load current IL may vary, for example, from between 0 A and several 100 A. The load signal SL may be generated by a controller inside theload 42, wherein this controller is configured to control operation of theload 42. When theload 42 includes a motor of a vehicle, for example, the controller may accelerate the motor based on a corresponding signal received from an accelerator pedal. Upon receipt of a signal indicating that it is desired to accelerate the motor, the controller may change the load signal SL transmitted to thedrive circuit 2 before the controller accelerates the motor. -
FIG. 12 shows one example of thedrive circuit 2 in greater detail. In this example, thedrive circuit 2 includes anadjustable voltage source 6 that receives the load signal SL and is configured to generate a variable first voltage V6 based on the load signal SL. Thefirst voltage source 6 is connected between thesecond output node 22 and afirst input 51 of adriver 5. Asecond input 52 of thedriver 5 is connected to thesecond output node 22 directly or via an optionalsecond voltage source 7. The optionalsecond voltage source 7 is configured to generate a second voltage V7. Anoutput 54 of thedriver 5 is connected to thefirst output node 21. In order to drive thetransistor device 1 in the on-state, thedriver 5 connects thevoltage source 6 to thefirst output node 21 so that the drive voltage VGS received by thetransistor device 1 essentially equals the first voltage V6 provided by thefirst voltage source 6. In this example, the drive voltage VGS can be adjusted by adjusting the voltage V6 based on the node signal SL To switch off thetransistor device 1, thedriver 5 internally connects itssecond input 52 with thefirst output node 21. In this case, the drive voltage VGS is zero whensecond voltage source 7 is omitted, or essentially equals the inverted second voltage −V7. Whether thedriver 5 drives thetransistor device 1 in the on-state or the off-state is dependent on a drive signal S5 received at adrive input 53 of thedriver 5. This drive signal S5 may be any type of signal indicating that it is desired to switch on or switch off thetransistor device 1. According to one example, this drive signal S5 equals the control signal SCTRL explained with reference toFIG. 1 or is based on this control signal SCTRL. According to another example, the drive signal S5 is dependent on a supply voltage VSUPPLY received by thedrive circuit 2 betweensupply nodes 23, 24 explained with reference toFIG. 1 . -
FIG. 13 shows a drive circuit according to another example. Thedrive circuit 2 shown inFIG. 13 is different from thedrive circuit 2 shown inFIG. 12 in that theoutput 54 of the driver is connected tosecond output node 22 instead of thefirst output node 21. Further, thevoltage source 6 is connected between thefirst output node 21 and thefirst input 51 of thedriver 5. Thesecond input 52 of thedriver 5 is connected to thefirst output node 21, either directly or via the optional second voltage source V7. -
FIG. 14 shows one example of thedriver 5 in greater detail. For explanation purposes, thefirst voltage source 6, the optionalsecond voltage source 7, and thetransistor 1 are also illustrated inFIG. 14 . Just for the purpose of illustration, thedriver 5 and thevoltage sources FIG. 12 . Nevertheless. thedriver 5 shown inFIG. 15 may be used in a configuration as shown inFIG. 13 as well. - Referring to
FIG. 14 , thedriver 5 includes afirst switch 55 connected between thefirst input 51 and thefirst output 55, and asecond switch 56 connected between thesecond input 52 and theoutput 54. Acontrol circuit 57 generates control signals S55, S56 received by theswitches switches control circuit 57 generates the control signals S55, S56 based on the drive signal S5. Whenever the drive signal S5 indicates that it is desired to switch on thetransistor device 1, thecontrol circuit 57 generates the control signals S55, S56 such that thefirst switch 55 switches on and thesecond switch 56 switches offt so that thefirst voltage source 6 is connected between thefirst output node 21 and thesecond output node 22. When the drive signal SS5 indicates that it is desired to switch off thetransistor device 1, thecontrol circuit 57 generates the control signals S55, S56 such that thefirst switch 55 switches off and thesecond switch 56 switches on, so that the drive voltage VGS is either zero or −V7. Any type of electronic switch, such as any type of transistor, may be used to implement thefirst switch 55 and thesecond switch 56. - The adjustable
first voltage source 6 may be implemented in various ways. Examples of how thefirst voltage source 6 may be implemented are explained with reference toFIGS. 15 and 16 below. - According to
FIG. 15 , thevoltage source 6 may include avoltage regulator 63 that receives a supply voltage VSUP and is configured to generate the first voltage V6 betweenoutput nodes first voltage source 6 based on the supply voltage VSUP. The supply voltage VSUP received by thevoltage regulator 63 may be the supply voltage VSUPPLY received by thesupply nodes 23, 24 of the drive circuit 2 (seeFIG. 1 ) or may be a supply voltage VSUP generated based on this supply voltage VSUPPLY received by thedrive circuit 2. Thevoltage regulator 63 receives a reference signal SREF that defines the voltage level of the output voltage V6 generated by thevoltage regulator 63 based on the supply voltage VSUP. Optionally, anoutput capacitor 64 is coupled between theoutput nodes mapping circuit 65 generates the reference signal SREF based on the load signal SL. That is, themapping circuit 65 maps the load signal SL on the reference signal SREF, wherein thevoltage regulator 63 generates the first voltage V6 based on the reference signal SREF and wherein, in the on-state of thetransistor device 1, the drive voltage VGS equals the first voltage V6. Themapping circuit 65 may map the load signal SL on the reference signal SREF based on any of the examples explained with reference toFIGS. 5 to 7 . That is, themapping circuit 65 may generate only two different signal levels of the reference signal SREF based on the node signal SL in order to achieve only two different voltage levels of the drive voltage VGS. Or themapping circuit 65 may generate several discrete signal levels of the reference signal SREF based on the load signal SL in order to achieve more than two different voltage levels of the drive voltage VGS. Or themapping circuit 65 may generate the reference signal SREF in accordance with curves as illustrated inFIG. 7 . -
FIG. 16 shows afirst voltage source 6 according to another example. In this example, thevoltage source 6 receives the supply voltage VSUP and includes at least one charge pump 66 1, 66 M. Just for the purpose of illustration, two charge pumps 66 1, 66 M are shown inFIG. 1 . Each of these charge pumps 66 1, 66 M receives the supply voltage VSUP and generates an output voltage V66 1, V66 M higher than the supply voltage VSUP. A multiplexer 67 receives the supply voltage VSUP and the output voltage V66 1, V66 M from each of the charge pumps 66 1, 66 M. Themultiplexer 67 outputs one of the supply voltage VSUP and the output voltages V66 1, V66 M of the charge pumps 66 1, 66 M as the first voltage V6. A select signal SSEL defines which of the voltages received by themultiplexer 67 is to be output as the first voltage V6. This select signal SSEL is generated by amapping circuit 68 based on the load signal SL. Theadjustable voltage source 6 shown inFIG. 16 can generate the first voltage V6 and, therefore, the drive voltage VGS in accordance with a drive scheme shown inFIG. 6 (with the difference being thatFIG. 6 shows four different voltage levels, while the circuit shown inFIG. 16 can generate only three different voltage levels). The drive voltage VGS has the minimum level VGS _ MIN when the first voltage V6 equals the supply voltage VSUP, the drive voltage VGS has the maximum level when the first voltage V6 equals the voltage V66 M, and the drive voltage VGS has a voltage level between the minimum level VGS _ MIN and a maximum level VGS _ MAX when the first voltage V6 equals the voltage V66 1. -
FIG. 17 shows adrive circuit 2 according to another example. In this example, the first voltage V6 provided by thefirst voltage source 6 is substantially constant. Aboost circuit 8 connected between theoutput 54 of thedriver 5 and the first andsecond output nodes boost circuit 8 has a first input connected to theoutput 54 of thedriver 5, and asecond input 82 coupled to thesecond input 52 of thedriver 5 via thesecond voltage source 7. InFIG. 17 , V8 denotes a voltage between thefirst input node 81 and thesecond input node 82 of theboost circuit 8. - The
boost circuit 8 is configured to generate the drive voltage VGS in two different ways. In a first operating mode, which is the operating mode in which thetransistor device 1 is operated in the off-state, the boost circuit generates the drive voltage VGS such that it essentially equals the input voltage V8. Theboost circuit 8 is in the first operating mode when the input voltage V8 is negative, that is, when the input voltage V8 equals −V7. In a second operating mode, which is the operating mode in which thetransistor device 1 is operated in the on-state, the boost circuit generates the drive voltage VGS such that it is dependent on the input voltage V8 and dependent on the load signal SL. Theboost circuit 8 is in the second operating mode when the input voltage V8 is positive, that is, when the input voltage V8 equals the first voltage V6. - One example of the
boost circuit 8 is shown inFIG. 18 . In this example, theboost circuit 8 includes a capacitive voltage divider with afirst capacitor 82 1 and asecond capacitor 82 2 connected between thefirst output node 21 and thesecond output node 22. Acapacitor 85 connected in parallel with theoutput nodes transistor device 84 is connected between thefirst input node 81 of theboost circuit 8 and thefirst output node 21, and a control node of thetransistor 84 is connected to thesecond input node 82 of theboost circuit 8 so that thetransistor device 84 receives the input voltage V8 of theboost circuit 8 as a drive voltage. Thistransistor device 84 is configured such that it is an off-state when the input voltage V8 is positive. Arectifier element 87 is connected in parallel with thetransistor device 84 and is connected such that it allows a current to flow from theinput boost circuit 8 to theoutput transistor device 84 is MOSFET such as (as illustrated) an n-type enhancement MOSFET. In this case, a gate node of the MOSFET is connected to thesecond input node 82 and a source node of the MOSFET is connected to thefirst input node 81. A MOSFET may include an internal diode (usually referred to as body diode). Therectifier element 87 as shown inFIG. 18 can be the internal body diode of theMOSFET 84 or an additional diode connected in parallel with the load path of theMOSFET 84. If thediode 87 is an additional diode, it can be a bipolar diode or a Schottky diode. - Further, the
boost circuit 8 includes anelectronic switch 83 connected between thefirst input node 81 and a tap of thecapacitive voltage divider mapping circuit 86 drives theelectronic switch 83 dependent on the load signal SL. - The function of the
boost circuit 8 shown inFIG. 18 becomes apparent fromFIG. 19 that shows timing diagrams of the drive signal S5 received by thedriver 5, the control signal S83 generated by themapping circuit 86, the input voltage V8 of the boost circuit and the drive voltage VGS. When the drive signal S5 has a signal level indicating that it is desired to drive thetransistor device 1 in the off-state, thedriver 5 connects thesecond voltage source 7 between theinput nodes boost circuit 8. Consequently, the input voltage V8 is the inverted second voltage −V7. In this operating state, thetransistor device 84 is in the on-state, so that the drive voltage VGS substantially equals −V7. When the drive signal S5 indicate that it is desired to switch on thetransistor device 1, thedriver 5 connects thefirst voltage source 6 between theinput nodes boost circuit 8, so that the input voltage V8 essentially equals the first voltage V6. This is shown at a first time instance t1 inFIG. 19 . Thetransistor device 84 switches off when the voltage V8 increases to the first voltage V6. Via therectifier element 87 the input voltage V8 is passed through to theoutput node voltage divider mapping circuit 84 switches onswitch 83, the drive voltage is boosted from a first level (minimum level) represented by the first voltage V6 to a second level (maximum level). The boost circuit is therefore configured to drive thetransistor device 1 with one of two different voltage levels. The second level is given by V6+V82, wherein V82 is the voltage acrosscapacitor 82 1 of the voltage divider. This voltage V82 is given by -
- where C1 is the capacitance of
capacitor 82 1 and C2 is the capacitance ofcapacitor 82 2. - Optionally, there may be at least one resistive element coupled to the
capacitive voltage divider capacitive voltage divider switch 83. In this case, activating theswitch 83 causes the drive voltage VGS to rapidly increase (as shown inFIG. 19 ), wherein the at least one resistive element causes the drive voltage VGS to slowly decrease. According to one example, the at least one resistive element includes a first resistive element 88 1 connected in parallel with thefirst capacitor 82 1 and a second resistive element 88 2 connected in parallel with thesecond capacitor 82 2. According to one example, a resistance of the second resistive element 88 2 is smaller than a resistance of the first resistive element 88 1. According to one example, the resistance of the second resistive element 88 2 is less than 10%, less than 5%, or less than 1% of the resistance of the first resistive element 88 1 so that thesecond capacitor 82 2 is discharged faster than thefirst capacitor 82 1. According to one example, capacitances of thefirst capacitor 82 1 and thesecond capacitor 82 2 differ by less than 30% of the capacitance of the smaller one of the twocapacitors transistor device 1 with the higher voltage level, the mapping circuit may deactivateswitch 83 for a certain time period in which the second capacitor 88 2 is further discharged and then again activate theswitch 83 to boost the drive voltage VGS. Additionally or alternatively to the first and second resistive element 88 1, 88 2. a resistive element (not shown) is connected in parallel with thecapacitive voltage divide output nodes
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TWI705664B (en) * | 2020-01-08 | 2020-09-21 | 大陸商上海瀚薪科技有限公司 | Silicon carbide power element, drive circuit and control method |
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US7154240B2 (en) * | 2004-03-03 | 2006-12-26 | Denso Corporation | Load-driving device and method of driving load |
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