JP2016136805A - Semiconductor switching element drive circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a drive circuit for a semiconductor switching element, capable of adjusting a voltage, applied to a semiconductor switching element, in a manner to have a correct level without using a protection element.SOLUTION: At the drive of a transistor T1 connected between a battery 2 and a load by a drive circuit 15, a booster circuit 23 configuring a voltage adjustment circuit 12 boosts a voltage V2 supplied from a DC power supply 16, to generate a drive voltage to be applied to the gate of a transistor T5. When at least one of a voltage V1 of the battery 2 and the voltage V2 is fluctuated, an input voltage adjustment unit 21 adjusts a voltage Vgs applied between the source and the gate of the transistor T5 and the gate through the booster circuit 23, in a manner not to exceed a preset upper-limit value.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a drive circuit for driving a voltage-driven semiconductor switching element connected between a power supply and a load.

  For example, an H bridge circuit or an inverter circuit that drives a load such as a motor includes a half bridge circuit connected between a pair of power supply lines. As a semiconductor switching element constituting the upper arm of the half bridge circuit, a voltage drive type element such as an N channel type MOS transistor or an IGBT (Insulated Gate Bipolar Transistor) may be used. Such a drive circuit for driving a transistor includes a booster circuit for boosting an on-drive voltage applied to the gate of the transistor.

  In addition, a DC voltage supplied to a pair of power supply lines (hereinafter also referred to as a load DC voltage) is generally used to drive various other loads. Therefore, the load DC voltage may vary greatly depending on the state of those loads. If the driving circuit is supplied with such a large load DC voltage, the transistor may not be driven or the transistor may be damaged due to the influence of the fluctuation. For this reason, the drive circuit is normally operated by receiving a supply of a stabilized DC voltage (hereinafter also referred to as a drive DC voltage) different from the load DC voltage. That is, the DC voltages supplied to the pair of power supply lines and the drive circuit are often in separate systems (see, for example, Patent Documents 1 and 2).

  In the case of the above configuration, when the load DC voltage decreases during the period in which the transistor is turned on, the potential of the source, which is the load-side terminal, also decreases, for example, in the case of a MOS transistor. On the other hand, the driving circuit operates normally upon receiving the driving DC voltage, and outputs an ON driving voltage boosted by a predetermined value with respect to the driving DC voltage to the gate of the transistor. As a result, the potential difference between the gate and the source of the transistor becomes higher than that in a steady state, and the transistor may fail if the potential difference increases beyond the withstand voltage.

JP 2001-43990 A Japanese Patent Application No. 2013-226945

  In order to prevent the breakdown of the transistor due to the application of an overvoltage exceeding the withstand voltage, a countermeasure is generally taken in which a clamp element such as a Zener diode is arranged between the gate and the source. However, there are problems such as heat generation of the element and cost increase as a result of selecting the element size in consideration of energy tolerance.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a driving circuit for a semiconductor switching element that can be adjusted so that a voltage applied to the semiconductor switching element is at an appropriate level without using a protective element. It is to provide.

  According to the semiconductor switching element drive circuit of the first aspect, the voltage-driven semiconductor switching element connected between the first power source and the load is driven. The booster circuit boosts the voltage V2 supplied from the second power supply, thereby generating a driving voltage to be applied to the conduction control terminal of the semiconductor switching element. The voltage adjustment circuit is configured to apply a voltage (terminal) between the potential reference side conduction terminal and the conduction control terminal of the semiconductor switching element when at least one of the voltage V1 of the first power supply and the voltage V2 fluctuates. (Referred to as an inter-voltage) is adjusted so as not to exceed a preset upper limit value.

  That is, if at least one of the voltages V1 and V2 varies, and the voltage between the terminals of the semiconductor switching element tends to increase, the voltage between the terminals does not exceed the upper limit due to the action of the voltage adjustment circuit. Adjusted. Therefore, it is possible to prevent an overvoltage from being applied to the semiconductor switching element.

The figure which is 1st Embodiment and shows the structure of a drive circuit Operation timing chart Diagram showing only the configuration of the booster circuit Booster circuit timing chart The figure which shows the detailed structure of an input voltage adjustment part (the 1) The figure which shows the detailed structure of an input voltage adjustment part (the 2) Diagram showing the configuration of the motor drive system The figure which is 2nd Embodiment and shows the structure of a drive circuit The figure which is 3rd Embodiment and shows the structure of a drive circuit The figure which is 4th Embodiment and shows the structure of a drive circuit Operation timing chart The figure which is 5th Embodiment and shows the structure of a drive circuit The figure which shows the structural example of a voltage adjustment circuit (the 1) The figure which shows the structural example of a voltage adjustment circuit (the 2) Diagram showing a booster circuit as a model Timing chart showing change in boost voltage according to change in charge current Operation timing chart of drive circuit The figure which is 6th Embodiment and shows the structure of a drive circuit The figure which shows the structural example of a voltage adjustment circuit (the 1) The figure which shows the structural example of a voltage adjustment circuit (the 2) Operation timing chart of drive circuit The figure which is 7th Embodiment and shows the structure of a drive circuit Diagram showing a booster circuit as a model Timing chart showing change in boost voltage according to change in resistance value Operation timing chart of drive circuit The figure which is 8th Embodiment and shows the structure of a drive circuit Timing chart showing change in boost voltage according to change in charging time Operation timing chart of drive circuit The figure which is 9th Embodiment and shows the structure of a drive circuit Operation timing chart The figure which is 10th Embodiment and shows the structure of a drive circuit The figure which is 11th Embodiment and shows the structure of a drive circuit The figure which is 12th Embodiment and shows the detailed structure of an input voltage adjustment part. Operation timing chart showing a modification of the first embodiment

(First embodiment)
A motor drive system 1 of the present embodiment shown in FIG. 7 is used in an ECU (Electronic Control Unit) mounted on a vehicle such as an automobile, for example, and a pair of power supply lines 3, 4 from an in-vehicle battery 2 (first power supply). Is converted into a three-phase AC voltage and supplied to the motor 5 for driving. The DC voltage V1 has a steady value of about 12V, for example, but may be reduced to about 6V due to the influence of cranking or the like that occurs when the vehicle returns from the idling stop state.

  The motor drive system 1 includes a main circuit unit 6 and a drive unit 7. The main circuit unit 6 includes three half bridge circuits 8 to 10 and a capacitor 11 connected between the power supply lines 3 and 4. The six transistors T1 to T6 (semiconductor switching elements) constituting the half bridge circuits 8 to 10 are all N-channel MOS transistors, for example. Although illustration is omitted, free-wheeling diodes are respectively connected between the drains and sources of the transistors T1 to T6. Nodes N <b> 1 to N <b> 3 that serve as output terminals of the half-bridge circuits 8 to 10 are connected to respective phase terminals of the motor 5. The capacitor 11 is arranged to smooth the voltage between the power supply lines 3 and 4.

  The drive unit 7 includes a voltage adjustment circuit 12 and gate drive units 13 and 14. The voltage adjustment circuit 12 and the gate drive unit 13 constitute a drive circuit 15 that drives the transistors T1 to T3 (corresponding to switching elements) on the upper arm side. The voltage adjustment circuit 12 is supplied with a DC voltage V1 and a stabilized DC voltage V2 output from a DC power supply 16 (second power supply) that is different from the DC voltage V1. The value of the DC voltage V2 is the same as the steady value of the DC voltage V1. The voltage adjustment circuit 12 outputs a boosted voltage VRG obtained by boosting the DC voltage V2 to the gate drive unit 13.

  When a control signal instructing off driving is given from a control unit (not shown), the gate driving unit 13 gives a voltage (off driving voltage) lower than the source voltage to the gate of the transistor T1. Further, when a control signal instructing on driving is given, the gate driving unit 13 gives a voltage higher than the DC threshold voltage V1 by a gate threshold voltage (on driving voltage = boosted voltage VRG) to the gate of the transistor T1. The same applies to the portion for driving the transistors T2 and T3.

  When the control signal instructing off driving is given from the control unit, the gate driving unit 14 gives a voltage (off driving voltage) lower than the source voltage to the gate of the transistor T4. Further, when a control signal instructing on driving is given, the gate driving unit 14 gives a voltage higher than the source voltage by a gate threshold voltage (on driving voltage = DC voltage V2) to the gate of the transistor T4. The same applies to the portion for driving the transistors T5 and T6.

  As shown in FIG. 1, the voltage adjustment circuit 12 of the drive circuit 15 includes an input voltage adjustment unit 21 and a booster circuit 23 indicated by an amplifier (or a comparator) and a variable power supply symbol. The detailed configuration of the input voltage adjustment unit 21 is shown in FIG. 5 or FIG. 6 to be described later. The inverting input terminal of the amplifier is connected to the positive terminal of the battery 2, and the inverting input terminal is connected to the positive terminal of the DC power supply 16. Yes. The output voltage Vo of the input voltage adjustment unit 21 is supplied to the booster circuit 23.

  The booster circuit 23 is configured as a charge pump circuit by a series circuit of diodes 24 and 25, an oscillation circuit 26, a buffer 27, and a capacitor 28. The output voltage Vo of the variable power source 22 is input to the anode of the diode 24. The cathode of the diode 25 is an output terminal of the boosted voltage VRG, and is connected to a reference potential, for example, ground (hereinafter referred to as ground) via a capacitor 29. The output terminal of the oscillation circuit 26 is connected to the input terminal of the buffer 27, and the output terminal of the buffer 27 is connected to the anode of the diode 25 via the capacitor 28.

In the gate driving units 13 and 14, the control signals input from the control unit are simply represented by symbols of the oscillation circuits.
As shown in FIG. 3, the boosted voltage VRG output from the booster circuit 23 is charged to the input voltage Vo when the terminal voltage of the capacitor 28 is VCPM and the forward voltage of the diodes 23 and 24 is Vf. ,
VRG = Vo + VCPM−Vf−Vf = 2Vo−2Vf (1)
It becomes. Then, as shown in FIG. 4, if the terminal voltage VCPM is not charged until it becomes equal to the input voltage Vo,
VRG <2Vo-2Vf
It becomes. Therefore, the input voltage adjustment unit 21 limits the boosted voltage VRG supplied as the drive voltage to the gate drive unit 13 by controlling the output voltage Vo according to the potential difference between the input voltages V1 and V2.

  For example, as shown in FIG. 5, the input voltage adjustment unit 21 (A) includes an AMP (amplifier) 1 and includes a differential amplifier circuit 30 that differentially amplifies the voltages V1 and V2 and AMPs 2 to 5. And a combination of non-inverting amplifier circuits 31 to 34. The voltage V7 input to the non-inverting input terminal of the non-inverting amplifier circuit 34 is the output voltage V4 of the differential amplifier circuit 30, the output voltages V5 and V6 of the non-inverting amplifier circuits 32 and 33, and the resistance elements R5 to R7, respectively. It is the voltage added through.

The output voltage Vo of the non-inverting amplifier circuit 34 is
Vo = (R8 + R9) / R8 × V7 (2)
The output voltages V3 to V6 of the amplifier circuits 30 to 33 are respectively V3 = (R1 ′ + R2 ′) / R1 ′ × VBG (3)
V4 = R2 / R1 × (V1-V2) (4)
V5 = R4 / R3 × (V2-V3) (5)
V6 = (R3 ′ + R4 ′) / R3 ′ × VBG (6)
It becomes. VBG is a band gap reference voltage.

The input voltage V7 to the non-inverting amplifier circuit 34 is
V7 = (R6 × R7 × V4 + R7 × R5 × V5 + R5 × R6 × V6)
/ (R5 × R6 + R6 × R7 + R7 × R5) (7)
It becomes. For example, if R1 to R8 = R and (R8 + R9) / R8 = 3 are set, the output voltage Vo is
Vo = (V1-V2) + (V2-V3) + V6 (8)
It becomes.

  For example, as illustrated in FIG. 6, the input voltage adjustment unit 21 (B) is configured by a combination of a plurality of comparators 35, a logic circuit 36, and a non-inverting amplifier circuit 38 using an amplifier 37. A series circuit composed of a plurality of resistance elements 39 is connected between the positive terminal of the battery 2 and the ground, and a plurality of resistance elements 40 are connected between the positive terminal of the DC power supply 16 and the ground. A series circuit is connected.

  The non-inverting input terminal of each comparator 35 is connected in common to the common connection point of the resistor elements 40 (1) and 40 (2), and the inverting input terminal of each comparator 35 is connected to the resistor element 39 (1) and the resistor element 39 (1), respectively. The common connection point 39 (2), the common connection point of the resistance elements 39 (2) and 39 (3), the common connection point of the resistance elements 39 (3) and 39 (4), and so on. The output terminals of the comparators 35 are connected to the input terminals of the logic circuit 36, respectively.

  A band gap reference voltage VBG is applied to the inverting input terminal of the amplifier 37, and the non-inverting input terminal is connected to the ground through a series circuit including a plurality of resistance elements 41, and the resistance element 42 is connected to the inverting input terminal. To the output terminal of the amplifier 37. Switches 43 (2) to 43 (n) are connected in parallel to both ends of the resistance elements 41 (2) to 41 (n), respectively. The logic circuit 36 controls on / off of the switches 43 (2) to 43 (n) according to the output signal of each comparator 35.

That is, the plurality of comparators 35 change the output signal to a binary level of high and low according to the potential difference between the voltages V1 and V2. The logic circuit 36 controls the on / off of each of the switches 43 (2) to 43 (n) according to the levels of the output signals, so that the gain of the non-inverting amplifier circuit 38 changes. As a result, the output voltage Vo is a voltage obtained by multiplying the voltage VRG by a predetermined gain.
In addition, the input voltage adjustment unit 21 adopts a configuration in which, for example, the voltages V1 and V2 are read by A / D conversion, a difference voltage is obtained by microcomputer software, and the output voltage Vo is determined according to the difference voltage. be able to.

Next, the operation of this embodiment will be described using the input voltage adjusting unit 21 (A) shown in FIG. The forward voltage Vf is set to 0.7V, the output voltages V3 and V6 are set to 14V and 11.7V, respectively.
R2 / R1 = R4 / R3 = 0.5
R5 to R7 = R
(R8 + R9) / R8 = 3
Set to. At this time, when V1 = V2 = 14V in the steady state as in the region 1 shown in FIG. 2, Vo = 0.5 × (14−14) + 0.5 × from the equations (2) and (7). (14-14) + 11.7 = 11.7 [V]
It becomes. Then, the boosted voltage VRG output from the booster circuit 23 is VRG = 2Vo-2Vf = 2 (11 + Vf) -2Vf = 22 [V] according to the equation (1).
It becomes. For example, when the breakdown voltage of the gate-source voltage Vgs of the transistor T1 is 10V, the maximum value of the voltage Vgs is set to 8V, for example. That is,
Vgs = VRG-V1 = 8V
Control to be

From this state, when the voltage V1 drops to 10 V in the region 2, the output voltage Vo is accordingly Vo = 0.5 × (10−14) + 0.5 × (14−14) + 11.7 = 9.7 [V ]
The boosted voltage VRG becomes 18V and the gate-source voltage Vgs is maintained at 8V.

When the voltage V1 returns to 14V in the region 3 and the voltage V2 decreases to 10V, the output voltage Vo is calculated as follows: Vo = 0.5 × (14−10) + 0.5 × (10−14) + 11.7 = 11.7 [V]
However, since the power supply voltage of the AMP5 is V2, Vo = V2 = 10 [V]. The boosted voltage VRG becomes (20-2Vf) V. At this time, the gate-source voltage Vgs is less than 8 V, but there is no problem in turning on the transistor T1. However, when the shortage of the voltage Vgs becomes a problem, a configuration for temporarily boosting the voltage may be employed (for example, refer to the third embodiment).

Subsequently, in the region 4 where the voltage V2 returns to 14V and then increases to 16V, the output voltage Vo is Vo = 0.5 × (14−16) + 0.5 × (16−14) + 11.7 = 11. .7 [V]
To maintain. Although not shown, when the potential relationship of region 4 is reversed,
Vo = 0.5 × (16−14) + 0.5 × (14−14) + 11.7 = 12.7 [V]
become.

As described above, according to the present embodiment, when the transistor T1 connected between the battery 2 and the motor 5 is driven by the drive circuit 15, the booster circuit 23 that constitutes the voltage adjustment circuit 12 includes the DC power supply 16 By boosting the supplied voltage V2, a driving voltage to be applied to the gate of the transistor T1 is generated. The input voltage adjustment unit 21 determines that the voltage Vgs applied between the source and gate of the transistor T1 via the booster circuit 23 when at least one of the voltage V1 of the battery 2 and the voltage V2 fluctuates. Adjust so as not to exceed the preset upper limit. Therefore, it is possible to prevent an overvoltage from being applied to the transistor T1.
In this case, the input voltage adjustment unit 21 (A) decreases the voltage Vo input to the booster circuit 23 as the difference between the two voltages increases under the initial condition (V1 ≦ V2). Overvoltage protection can be performed reliably.

(Second Embodiment)
Hereinafter, the same parts as those in the first embodiment are denoted by the same reference numerals, description thereof will be omitted, and different parts will be described. The drive circuit 44 according to the second embodiment shown in FIG. 8 is obtained by adding diodes 45 and 46 to the drive circuit 15 according to the first embodiment. Has been. Further, these cathodes are commonly connected to the power input terminal of the voltage adjustment circuit 12 and supplied to the input voltage adjustment unit 21 as an operation power supply. That is, with regard to the input voltage adjustment unit 21 (A) shown in FIG. 5, the power for operation is supplied to the AMPs 1 to 5 from the cathodes of the diodes 45 and 46 instead of the power source V2.

  According to the second embodiment configured as described above, the higher voltage of the voltages V1 and V2 is supplied to the voltage adjustment circuit 12 as an operation power supply. Therefore, even when V1> V2, the output voltage Vo can be adjusted with the voltage V1 side as a reference.

(Third embodiment)
As shown in FIG. 9, the drive circuit 51 of the third embodiment includes a booster circuit 52, and the booster circuit 52 is configured such that the boosting capability of the charge pump circuit can be changed. Instead of the output voltage Vo of the input voltage adjustment unit 21, the voltage V <b> 2 is directly supplied to the booster circuit 52. The booster circuit 52 includes a first booster 53 (1) and a second booster 53 (2). The input terminal of the BUF (buffer) (2) constituting the second booster 53 (2) is connected to the input terminal of the BUF (1) constituting the first booster 53 (1) via the changeover switch 54 and the ground. It can be connected to.

  The changeover control of the changeover switch 54 is performed by the output signal of the comparator 55. The voltage V1 is applied to the non-inverting input terminal of the comparator 55 and the voltage V2 is applied to the inverting input terminal. Further, the voltage V2 is applied to the operating power supply for the BUF (1) and BUF (2) via the variable current sources I (1) and I (2). The current control of the variable current sources I (1) and I (2) (constant current circuit) is performed by the output signal of the differential amplifier circuit 56 (voltage adjustment circuit) indicated by the symbol of the amplifier. A voltage V1 is applied to the non-inverting input terminal, and a voltage V2 is applied to the inverting input terminal.

  Next, the operation of the third embodiment will be described. In the case of (V1 ≦ V2), the booster circuit 52 has the input terminal of the second booster 53 (2) connected to the ground, and performs the boosting operation in only one stage by the first booster 53 (1). In the case of (V1> V2), the input terminal of the second booster 53 (2) is connected to the input terminal of the BUF (1) and boosted in two stages including the second booster 53 (2). It will begin to work.

  Further, when the potential difference between the voltages V1 and V2 increases due to the output voltage of the differential amplifier circuit 56, the current supplied from the variable current sources I (1) and I (2) is narrowed down, so that the capacitors C (1), The boosting capability of the booster circuit 52 is lowered by reducing the charging current amount of C (2). As a result, the voltage Vgs applied to the gate of the transistor T5 is lowered.

  As described above, according to the third embodiment, the differential amplifier circuit 56 includes the capacitor C (1) constituting the booster circuit 52 as the difference between the two voltages increases under the initial condition (V1 ≦ V2). ), C (2) charging current amount is reduced. Specifically, the current value supplied from the variable current sources I (1) and I (2) for supplying the charging current to the capacitors C (1) and C (2) is reduced. Therefore, the same effect as the first embodiment can be obtained. In addition, since the booster circuit 52 changes the boosting capability according to the magnitude relationship between the voltages V1 and V2, the transistor T1 can be driven even when (V1> V2).

(Fourth embodiment)
As shown in FIG. 10, the drive circuit 61 of the fourth embodiment has a configuration in which a SINK circuit 62 (voltage drop means) is added to the drive circuit 15 of the first embodiment. In the SINK circuit 62, the drain is connected to the output terminal of the booster circuit 23 through the resistance element 63, the source is connected to the ground, the N-channel MOSFET 64 (semiconductor switching element), and the output terminal is connected to the gate of the FET 64. And a comparator 65. The inverting input terminal of the comparator 65 is connected to the positive terminal of the battery 2, and the non-inverting input terminal is connected to the output terminal of the booster circuit 23 via the resistance element 66 and connected to the ground via the resistance element 67. Has been. That is, the voltage adjustment circuit 68 is configured by adding the SINK circuit 62 to the voltage adjustment circuit 12 of the first embodiment.

  Next, the operation of the fourth embodiment will be described. As shown in FIG. 11, in the case of using the drive circuit 15 of the first embodiment, even if the region 2 where (V2> V1) is reached, the voltage due to the control delay of the voltage adjustment circuit 12, the size of the load, etc. It is assumed that the boosted voltage VRG cannot be lowered by the control of Vo alone. In that case, in the voltage adjustment circuit 68 of the fourth embodiment, the FET 64 is turned on by the output signal So of the comparator 65 when the potential of the non-inverting input terminal of the comparator 65 that has divided the boosted voltage VRG becomes higher than the voltage V1. Thus, the boosted voltage VRG is forcibly lowered.

  As described above, according to the fourth embodiment, the voltage adjustment circuit 68 includes the SINK circuit 62 disposed between the voltage output terminal of the booster circuit 23 and the ground, and both of them are satisfied under the initial condition (V1 ≦ V2). The boosted voltage VRG is lowered as the voltage difference increases. Specifically, the SINK circuit 62 is compared with the series circuit of the resistor element 63 and the FET 64 connected between the voltage output terminal and the ground with the divided potential of the voltage V1 and the boosted voltage VRG. The comparator 65 is configured to control the conduction state. Therefore, even when there is a control delay of the input voltage adjusting unit 21, the boosted voltage VRG can be quickly reduced.

(Fifth embodiment)
As shown in FIG. 12, in the drive circuit 71 of the fifth embodiment, power is supplied to the buffer 27 constituting the booster circuit 72 that is a charge pump circuit via a variable current source 73 (constant current circuit). The current control of the variable current source 73 is performed by a voltage adjustment circuit 74 indicated by an amplifier or comparator symbol.

  When the voltage adjustment circuit 74 is an amplifier, for example, the configuration shown in FIG. 13 is adopted as the variable current source 73 (A). A series circuit of a resistance element 75 and a PNP transistor 76 is connected between the power supply (V 2) and the ground, and a common connection point thereof is connected to the base of the NPN transistor 77. The emitter of the NPN transistor 77 is connected to the ground via a resistance element 78 (resistance value R). A mirror pair of PNP transistors 79 a and 79 b is formed on the power supply side, and the collector of the transistor 79 a is connected to its own base and the collector of the transistor 77.

  In the above configuration, when the output voltage Vin of the voltage adjustment circuit 74 is applied to the base of the transistor 76, IOUT = Vin / R is output from the collector of the transistor 79b. Therefore, if the output voltage Vin is {Vin = (V1-V2) + VBG}, a variable current IOUT corresponding to the voltage difference between the voltages V1 and V2 can be obtained.

  Further, when the voltage adjustment circuit 74 is an amplifier, for example, a configuration shown in FIG. 14 is adopted as the variable current source 73 (B). In this configuration, the resistance element 78 of the variable current source 73 (A) is replaced with a series circuit of resistance elements 78a and 78b (resistance values Ra and Rb), and a switch 80 is connected to both ends of the resistance element 78b. A band gap reference voltage VBG is applied to the base of the transistor 76. When the resistance value of the series circuit is Rx, IOUT = VBG / Rx is output from the collector of the transistor 79b. If the on / off state of the switch 80 is controlled according to the output voltage of the voltage adjusting circuit 74, the resistance value Rx can be switched between Ra and (Ra + Rb). It is done.

  As shown in FIG. 15, when the booster circuit is modeled and the terminal voltage of the capacitor C is V, V = IT · T / C. As shown in FIG. 16, if the time T for charging the capacitor C by the current source is constant, the terminal voltage V is proportional to the magnitude of the charging current I. Even when V_I1 reaches the power supply voltage Va in the case of the current value (I1> I2), the voltage Vb rising at V_I2 becomes (<Va).

  Next, the operation of the fifth embodiment will be described. As shown in FIG. 17, the current values I1 and I2 are set to currents that can rise to voltages Va (= 8V) and Vb (= 4V) in the charging time T, respectively. In the region of V1 = V2 = 14 [V], the boost voltage VRG becomes (14 + 8 =) 22 [V] due to the current value I1. When the voltage drops to V1 = 10 [V] from this state, the boosted voltage VRG is changed to (14 + 4 =) 18 [V] by switching to the current value I2.

  In the region of V1 = 14 [V] and V2 = 10 [V], the current value is I1, but the boosted voltage VRG remains at (10 + 8 = 18 [V]). However, in this case, if the current value I3 can be increased to the voltage Vc (= 10V) in the charging time T, the boosted voltage VRG can reach 20V.

  As described above, according to the fifth embodiment, the voltage adjustment circuit 74 charges the capacitor 28 built in the booster circuit 23 as the difference between the two voltages increases under the initial condition (V1 ≦ V2). Reduce the amount of current. Specifically, the current value of the variable current source 73 that supplies the charging current to the capacitor 28 is lowered. Thereby, the boosted voltage VRG can be lowered.

(Sixth embodiment)
As shown in FIG. 18, in the drive circuit 81 of the sixth embodiment, power is supplied to the buffer 27 constituting the booster circuit 82 which is a charge pump circuit via a variable voltage source 83 (constant voltage circuit). The voltage control of the variable voltage source 83 is performed by the voltage adjustment circuit 74 as in the fifth embodiment.

  When the voltage adjustment circuit 74 is an amplifier, for example, a configuration shown in FIG. 19A is adopted as the variable voltage source 83 (A). If the drain of the N-channel MOSFET is connected to the power supply and the output voltage Vin of the voltage adjusting circuit 74 is applied to the gate, the output voltage Vo from the source becomes (= Vin−Vt) (source follower output). Vt is the threshold voltage of the FET. Further, as shown in FIG. 19B, if the N-channel MOSFET is replaced with an NPN transistor, an emitter follower output is obtained, and the output voltage Vo from the emitter becomes (= Vin−Vf). Vf is the base-emitter voltage of the transistor.

  When the voltage adjustment circuit 74 is a comparator, the configuration shown in FIG. 20 is adopted as the variable voltage source 83 (B). The anodes of the two diodes are commonly connected to the current source IREF, and the series circuit of the resistance elements 78a and 78b and the switch 80 shown in FIG. The switch 80 is turned on and off. Then, the output voltage Vo from the other cathode can be controlled by (= IREF × Rx). A diode or a Zener diode may be used in place of the resistance element 78.

  Next, the operation of the sixth embodiment will be described. As shown in FIG. 21, in the region of V1 = V2 = 14 [V], the power supply voltage Vo of the buffer 27 is controlled to be (8 + 2Vf) [V]. Then, the boost voltage VRG becomes 14 + 8 + 2Vf−2Vf = 22 [V]. When the voltage drops from this state to V1 = 10 [V], the power supply voltage Vo is controlled to be (4 + 2Vf) [V]. Then, the boosted voltage VRG becomes (14 + 4 + 2Vf−2Vf =) 18 [V].

In the region of V1 = 14 [V] and V2 = 10 [V], the boosted voltage VRG becomes (20−2 Vf) [V] by controlling the power supply voltage Vo = 10 [V]. Further, in the region of V1 = 14 [V] and V2 = 16 [V], if the power supply voltage Vo is controlled to be (6 + 2Vf) [V], the boost voltage VRG becomes 16 + 6 = 22 [V].
As described above, according to the sixth embodiment, the variable voltage source 83 is used to variably control the power supply voltage Vo for the buffer 27 constituting the booster circuit 82, so that the charging current amount for the capacitor 28 is reduced. did. Therefore, the same effect as the fifth embodiment can be obtained.

(Seventh embodiment)
As shown in FIG. 22, in the drive circuit 91 according to the seventh embodiment, the variable voltage source 83 according to the sixth embodiment is replaced with a variable resistor 92 (resistor circuit) to form a booster circuit 93. As shown in FIG. 23, when the booster circuit is modeled similarly to FIG. 15 and the current source I is replaced with the resistor R, the terminal voltage of the capacitor C is expressed as
V = Va {1-exp (-T / RC)}
It is represented by As shown in FIG. 24, if the time T for charging the capacitor C through the resistor R is constant, the terminal voltage V varies depending on the resistance value of the resistor R. In the case of the resistance value (R2> R1), even if the power supply voltage Va is reached at V_R1, the voltage Vb rising at V_R2 is (<Va).

  Next, the operation of the seventh embodiment will be described. As shown in FIG. 25, in the region of V1 = V2 = 14 [V], the resistance value of the variable resistor 92 is set to R1, and the pumping voltage Va of the booster circuit 92 is set to 8V. Then, the boosted voltage VRG becomes (14 + 8 =) 22 [V]. When V1 = 10 [V] is lowered from this state, the resistance value of the variable resistor 92 is set to R2, and the pumping voltage Vb is set to 4V. Then, the boost voltage VRG becomes (14 + 4 =) 18 [V].

In the region of V1 = 14 [V] and V2 = 10 [V], if the resistance value of the variable resistor 92 is set to R1, the boosted voltage VRG becomes (10 + 8 =) 18 [V]. In the region of V1 = 14 [V] and V2 = 18 [V], if the resistance value of the variable resistor 92 is set to R2, the boosted voltage VRG becomes (18 + 4 =) 22 [V].
As described above, according to the seventh embodiment, the voltage adjustment circuit 74 includes the variable resistor 92 that supplies the charging current to the capacitor 28 from the DC power supply 16, and increases the resistance value to decrease the amount of charging current. I made it. Therefore, the same effect as in the sixth embodiment can be obtained.

(Eighth embodiment)
As shown in FIG. 26, in the drive circuit 101 of the eighth embodiment, the booster circuit 103 is configured by replacing the oscillation circuit 26 in the booster circuit 23 of the first embodiment with a variable oscillation circuit 102. Then, the variable oscillation circuit 102 is controlled by the voltage adjustment circuit 74. The variable oscillation circuit 102 is configured to be able to change the duty of the pumping clock output to the buffer 27. As shown in FIG. 27, when the period for charging the capacitor 28 is T1, when the voltage can be boosted to the pumping voltage Va, the voltage is boosted only to the voltage Vb (<Va) in the shorter period T2.

  Next, the operation of the eighth embodiment will be described. As shown in FIG. 28, in the region of V1 = V2 = 14 [V], the low level duty of the variable oscillation circuit 102 is set to a value corresponding to the period T1, and the pumping voltage Va of the booster circuit 102 is set to 8V. Then, the boosted voltage VRG becomes (14 + 8 =) 22 [V]. When V1 decreases to 10 [V] from this state, the duty is set to a value corresponding to the period T2, and the pumping voltage Vb is set to 4V. Then, the boost voltage VRG becomes (14 + 4 =) 18 [V].

  In the region of V1 = 14 [V] and V2 = 10 [V], the boosted voltage VRG becomes (10 + 8 =) 18 [V] if the duty is set to a value corresponding to the period T1. In the region where V1 = 14 [V] and V2 = 18 [V], if the duty is set to a value corresponding to the period T2, the boosted voltage VRG becomes (18 + 4 =) 22 [V].

  As described above, according to the eighth embodiment, the voltage adjustment circuit 74 decreases the duty of the pumping clock of the booster circuit 102 as the difference between the two voltages increases under the initial condition of (V1 ≦ V2). The amount of charging current was reduced. Therefore, the same effect as in the sixth or seventh embodiment can be obtained. Note that the frequency of the pumping clock may be reduced instead of the duty.

(Ninth embodiment)
As shown in FIG. 29, in the drive circuit 104 of the ninth embodiment, in the drive circuit 15 of the first embodiment, the power source for the gate drive unit 13 is passed through the variable voltage source 83 (constant voltage circuit, voltage changing means). The voltage control of the variable voltage source 83 is performed by the voltage adjustment circuit 74 as in the fifth embodiment.

  Next, the operation of the ninth embodiment will be described. As shown in FIG. 30, in this case, the boosted voltage VRG changes as the voltage V2 changes, and when V1 = V2 = 14 [V], it is (28-2Vf) [V]. At this time, the voltage adjustment circuit 74 controls the power supply voltage Vo of the gate driving unit 13 supplied via the variable voltage source 83, that is, the gate potential of the transistor T1 to be 22 [V].

  In the region where V1 = 10 [V] and V2 = 14 [V], the boosted voltage VRG remains (28-2Vf) [V], but the power supply voltage Vo is controlled to be 18 [V]. Thus, the gate-source voltage Vgs of the transistor T1 is set to 8V. In the region of V1 = 14 [V] and V2 = 10 [V], the boosted voltage VRG drops to (20−2Vf) [V]. At this time, the power supply voltage Vo becomes equal to the boosted voltage VRG. In the region where V1 = 14 [V] and V2 = 16 [V], the boosted voltage VRG rises to (32−2 Vf) [V], but the power supply voltage Vo maintains 22 [V].

  As described above, according to the ninth embodiment, the voltage adjustment circuit 74 controls the variable voltage source 83 in accordance with the changes in the voltages V1 and V2, thereby changing the power supply voltage Vo of the gate driving unit 13 to thereby change the transistor T1. The gate-source voltage Vgs is controlled so as not to exceed the upper limit. Therefore, the same effect as each embodiment is acquired.

(10th Embodiment)
In the drive circuit 111 of the tenth embodiment shown in FIG. 31, the booster circuit 112 is constituted by a DCDC converter. The diode 24 is omitted, and a coil 113 is connected between the positive terminal of the DC power supply 16 and the anode of the diode 25. A series circuit of resistance elements 114 and 115 is connected between the cathode of the diode 25 and the ground, and their common connection point is connected to the inverting input terminal of the error amplifier 116. The output voltage (reference voltage) of the variable voltage source 117 is given to the non-inverting input terminal of the error amplifier 116, and the variable voltage source 117 is controlled by the voltage adjustment circuit 74.

  The output terminal of the error amplifier 116 is connected to the inverting input terminal of the comparator 118, and the non-inverting input terminal of the comparator 118 is given a triangular wave carrier output from the oscillation circuit 119. A transistor (N-channel MOSFET) 120 is connected between the anode of the diode 25 and the ground, and an output terminal of the comparator 118 is connected to the gate of the transistor 120 via the buffer 121.

  Next, the operation of the tenth embodiment will be described. The voltage adjustment circuit 74 decreases the output voltage of the variable voltage source 117 and decreases the boosted voltage VRG generated by the booster circuit 112 as the potential difference between the voltages V1 and V2 increases. Therefore, even in this configuration, the same effects as those of the embodiments can be obtained.

(Eleventh embodiment)
The drive circuit 131 of the eleventh embodiment shown in FIG. 32 is obtained by replacing the configuration of the booster circuit 112 with a booster circuit 132 that is slightly changed. The booster circuit 132 is obtained by replacing the variable voltage source 117 with a constant voltage source 133 and the resistance element 115 with a variable resistance element 134, and the voltage adjustment circuit 74 controls the resistance value of the variable resistance element 134.

  Next, the operation of the eleventh embodiment will be described. The voltage adjustment circuit 74 increases the resistance value of the variable resistance element 134 as the potential difference between the voltages V1 and V2 increases. As a result, the amount of feedback to the error amplifier 116 increases (the feedback gain decreases), and the boosted voltage VRG generated by the booster circuit 132 decreases. Therefore, the same effect as the tenth embodiment can be obtained.

(Twelfth embodiment)
As shown in FIG. 33 corresponding to FIG. 5, the input voltage adjusting unit 21 (C) of the twelfth embodiment deletes the differential amplifier circuit 30 from the input voltage adjusting unit 21 (A), and a non-inverting amplifier circuit. In this configuration, the power supply voltage applied to the non-inverting input terminal of the AMP 3 constituting 32 is V1. That is,
(V7 = V5 + V6). And by setting to (R8 = R9), the effect similar to 1st Embodiment is acquired by the input voltage adjustment part 21 (C) comprised by a smaller circuit.

The present invention is not limited to the embodiments described above or shown in the drawings, and the following modifications or expansions are possible.
Each of the above embodiments is based on the premise that the relationship between the voltages V1 and V2 is (V1 ≦ V2). However, the present embodiment can be applied even when the relationship between the two is (V1 ≧ V2). For example, as the difference between both voltages increases,
Increase the voltage input to the booster circuit 23.
Increase the charge current amount of the capacitor 28 built in the booster circuit 23.
-Increase the frequency or duty of the pumping clock.
Increase the reference voltage of the error amplifier 116.
Reduce the amount of feedback to the error amplifier 116.
Increase the power supply voltage supplied to the buffer 27.
Increase the boosted voltage supplied to the gate driver 13.
For example, the boost voltage output from the booster circuit may be increased (see, for example, FIG. 34). Moreover, the structure corresponding to both the case of (V1 <= V2) and the case of (V1> = V2) may be provided, and you may switch and use according to a case.

  Also, by applying the configuration of the second or third embodiment to the fourth to ninth embodiments, the output voltage Vo is adjusted based on the voltage V1 side even in the region where (V1> V2) ( VRG = V1 + V8), and the transistor T1 can be driven.

  In the drawings, 2 is a battery (first power supply), 5 is a motor (load), 12 is a voltage adjustment circuit, 16 is a DC power supply (second power supply), 23 is a booster circuit, 28 capacitors, and T1 is a transistor (semiconductor switching element). ).

Claims (22)

Drives a voltage-driven semiconductor switching element (T1) connected between a first power supply (2) and a load (5).
A booster circuit (23, 52, 72, 82, 93, 103, 112) that generates a drive voltage to be applied to the conduction control terminal of the semiconductor switching element by boosting the voltage supplied from the second power source (16). 132) and
When at least one of the voltage V1 of the first power supply and the voltage V2 of the second power supply fluctuates, a voltage applied between the potential reference side conduction terminal and the conduction control terminal of the semiconductor switching element is: A drive circuit for a semiconductor switching element, comprising: a voltage adjustment circuit (12, 56, 74) for adjusting so as not to exceed a preset upper limit value. In response to an increase in the difference between the two voltages under the initial condition (V1 ≦ V2),
2. The semiconductor switching element drive circuit according to claim 1, wherein a voltage input to the booster circuit via the second power supply is lowered. The booster circuit (23, 52, 72, 82, 93, 103) is composed of a charge pump circuit,
The voltage adjustment circuit (56, 74) is configured such that the capacitor (28, C (1), C ( 3. The driving circuit for a semiconductor switching element according to claim 1, wherein the charging current amount of 2)) is reduced.   The voltage adjusting circuit includes a constant current circuit (73, I (1), I (2)) for supplying a charging current to the capacitor, and reduces a current value supplied by the constant current circuit. A drive circuit for a semiconductor switching element according to claim 3.   4. The drive circuit for a semiconductor switching element according to claim 3, wherein the voltage adjustment circuit includes a resistance circuit (92) for supplying a charging current to the capacitor, and increases a resistance value of the resistance circuit. The voltage adjusting circuit includes a buffer (27) for supplying a charging current to the capacitor;
4. The semiconductor switching element according to claim 3, further comprising: a variable voltage source (83) configured to supply operation power to the buffer and configured to change a power supply voltage, wherein the power supply voltage is lowered. Drive circuit. The booster circuit is composed of a charge pump circuit (103),
The voltage adjustment circuit (74) reduces the frequency or duty of the pumping clock of the charge pump circuit in accordance with an increase in the difference between both voltages under an initial condition of (V1 ≦ V2). Item 3. A driving circuit for a semiconductor switching element according to Item 1 or 2. The booster circuit (112) is composed of a DCDC converter,
The voltage adjustment circuit reduces a reference voltage of an error amplifier (116) constituting the DCDC converter in accordance with an increase in a difference between both voltages under an initial condition of (V1 ≦ V2). Item 8. A semiconductor switching element driving circuit according to Item 1. The booster circuit is composed of a DCDC converter (132),
The voltage adjustment circuit (74) changes a resistance value of a resistor that divides an output voltage of the DCDC converter in accordance with an increase in a difference between both voltages under an initial condition of (V1 ≦ V2), and the DCDC 2. The semiconductor switching element driving circuit according to claim 1, wherein the feedback amount to the error amplifier (116) constituting the converter is increased.   The voltage adjusting circuit includes voltage drop means (62) disposed between the voltage output terminal of the booster circuit and a reference potential point, and the difference between both voltages increases under the initial condition (V1 ≦ V2). 10. The drive circuit for a semiconductor switching element according to claim 1, wherein the voltage drop means is controlled in accordance with the voltage to reduce the drive voltage. The voltage drop means includes a series circuit of a resistance element (63) and a semiconductor switching element (64) connected between a voltage output terminal of the booster circuit and a reference potential point;
11. The semiconductor switching device according to claim 10, comprising a comparator (65) for comparing the voltage of the first power supply and the output voltage of the booster circuit to control the conduction state of the semiconductor switching element. Element drive circuit.   The power supply input terminal of the voltage adjustment circuit is connected to both the first power supply and the second power supply through two diodes (45, 46) having cathodes connected in common. The drive circuit of the semiconductor switching element as described in any one of Claims 1-11.   The voltage adjusting circuit includes voltage changing means (83) disposed in a path for supplying the driving voltage to a driving unit (13) for applying the driving voltage to a conduction control terminal of the semiconductor switching element, and reduces the power supply voltage. The drive circuit of the semiconductor switching element according to claim 1, wherein the drive circuit is a semiconductor switching element drive circuit.   The voltage adjustment circuit increases a voltage input to the booster circuit via the second power source in accordance with an increase in a difference between both voltages under an initial condition of (V1 ≧ V2). The drive circuit of the semiconductor switching element as described in any one of Claims 1-13. The booster circuit is composed of a charge pump circuit,
2. The voltage adjustment circuit increases a charging current amount of a capacitor constituting the charge pump circuit according to an increase in a difference between both voltages under an initial condition of (V1 ≧ V2). The drive circuit of the semiconductor switching element as described in any one of 1 to 14.   16. The drive circuit for a semiconductor switching element according to claim 15, wherein the voltage adjustment circuit includes a constant current circuit that supplies a charging current to the capacitor, and increases a current value supplied by the constant current circuit.   16. The drive circuit for a semiconductor switching element according to claim 15, wherein the voltage adjustment circuit includes a resistance circuit that supplies a charging current to the capacitor, and reduces a resistance value of the resistance circuit. The voltage adjusting circuit includes a buffer for supplying a charging current to the capacitor;
16. The drive circuit for a semiconductor switching element according to claim 15, further comprising: a variable voltage source configured to supply a power supply for operation to the buffer and configured to change a power supply voltage so as to raise the power supply voltage. . The booster circuit is composed of a charge pump circuit,
The voltage adjustment circuit increases the frequency or duty of the pumping clock of the charge pump circuit in accordance with an increase in the difference between the two voltages under an initial condition of (V1 ≧ V2). The drive circuit for the semiconductor switching element according to any one of claims 18 to 18. The booster circuit is composed of a DCDC converter,
The voltage adjustment circuit increases a reference voltage of an error amplifier constituting the DCDC converter according to an increase in a difference between both voltages under an initial condition of (V1 ≧ V2). 9. A drive circuit for a semiconductor switching element according to claim 8. The booster circuit is composed of a DCDC converter,
The voltage adjustment circuit configures the DCDC converter by changing a resistance value of a resistor that divides the output voltage of the DCDC converter in accordance with an increase in a difference between both voltages under an initial condition of (V1 ≧ V2). 10. The drive circuit for a semiconductor switching element according to claim 1, wherein a feedback amount to the error amplifier is reduced.   The voltage adjusting circuit includes voltage changing means disposed in a path for supplying the driving voltage to a driving unit that applies the driving voltage to a conduction control terminal of the semiconductor switching element, and reduces the power supply voltage. The drive circuit of the semiconductor switching element as described in any one of Claim 1 to 21.

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