CN113162377A - Silicon carbide power assembly, driving circuit and control method - Google Patents
Silicon carbide power assembly, driving circuit and control method Download PDFInfo
- Publication number
- CN113162377A CN113162377A CN202010075092.5A CN202010075092A CN113162377A CN 113162377 A CN113162377 A CN 113162377A CN 202010075092 A CN202010075092 A CN 202010075092A CN 113162377 A CN113162377 A CN 113162377A
- Authority
- CN
- China
- Prior art keywords
- source voltage
- driving signal
- gate
- bridge driving
- level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 42
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 42
- 238000000034 method Methods 0.000 title claims abstract description 13
- 230000008859 change Effects 0.000 claims abstract description 11
- 230000000630 rising effect Effects 0.000 claims description 10
- 230000007423 decrease Effects 0.000 claims description 9
- 230000002401 inhibitory effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 18
- 239000003990 capacitor Substances 0.000 description 17
- 101000885321 Homo sapiens Serine/threonine-protein kinase DCLK1 Proteins 0.000 description 4
- 102100039758 Serine/threonine-protein kinase DCLK1 Human genes 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 230000005669 field effect Effects 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- KZNMRPQBBZBTSW-UHFFFAOYSA-N [Au]=O Chemical compound [Au]=O KZNMRPQBBZBTSW-UHFFFAOYSA-N 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/157—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Power Conversion In General (AREA)
Abstract
The application relates to a silicon carbide power component, a driving circuit and a control method. A silicon carbide power component is controlled by a driver and has a grid electrode to source electrode voltage and a source electrode voltage, wherein the source electrode voltage is reduced according to the rise of the grid electrode to source electrode voltage, or the source electrode voltage is increased according to the fall of the grid electrode to source electrode voltage, so that a surge generated by the change of the grid electrode to source electrode voltage is inhibited, and the crosstalk phenomenon of the silicon carbide power component is inhibited.
Description
Technical Field
The present invention relates to a power device, a driving circuit and a control method, and more particularly, to a silicon carbide power device, a driving circuit and a control method.
Background
The silicon carbide power module has the advantages of high operating voltage, high operating temperature resistance, low on-resistance, high switching frequency and the like, and particularly, a silicon carbide gold oxygen semiconductor field effect transistor (SiC MOSFET) and a silicon carbide insulated gate bipolar transistor (SiC IGBT) are suitable for being used in the fields of electric vehicles and 5G communication which are in strong demand recently, and related technologies can be found in U.S. patent publication nos. US9,018,640B 1, US9,373,713B 2, US10,020,368B 2, US10,483,389B 2 and the like.
However, compared with the conventional silicon power device, the silicon carbide power device has a narrow voltage withstanding range of the gate and the source, and has a poor negative voltage withstanding capability, and the cross talk (Crosstalk) is likely to occur in the bridge arm circuit at a high switching frequency. This problem has been described in relation to A Magnetic Coupling Based Gate Driver for Cross Suppression of SiC MOSFETs by Binfeng Zhang et al, IEEE Transactions On Industrial Electronics, Vol.64, No.11, November 2017. At present, the crosstalk phenomenon of the silicon carbide power device cannot be effectively solved. In view of the above, there remains a need for improvement in conventional silicon carbide power devices.
Disclosure of Invention
The invention aims to solve the problem that the conventional silicon carbide power module is easy to generate crosstalk.
To achieve the above object, the present invention provides a method for controlling a silicon carbide power module, the method comprising the steps of: providing a silicon carbide power device controlled by a driver and having a gate-to-source voltage and a source voltage, the source voltage having at least a high level, a low level, and an intermediate level between the high level and the low level; and the driver alternately outputs an upper bridge driving signal and a lower bridge driving signal to a gate of the silicon carbide power device, wherein the source voltage is dropped from the middle level to the low level or dropped from the high level to the middle level when the gate-to-source voltage is raised according to the upper bridge driving signal or the lower bridge driving signal, and the source voltage is raised from the low level to the middle level or dropped from the middle level to the high level when the gate-to-source voltage is lowered according to the upper bridge driving signal or the lower bridge driving signal.
To achieve the above object, the present invention further provides a silicon carbide power device controlled by a driver and having a gate-to-source voltage and a source voltage, wherein the source voltage decreases according to the increase of the gate-to-source voltage, or the source voltage increases according to the decrease of the gate-to-source voltage, thereby suppressing a glitch generated by the change of the gate-to-source voltage.
To achieve the above object, the present invention further provides a driving circuit, including: a silicon carbide power device having a gate-to-source voltage and a source voltage; a driver for controlling the silicon carbide power device; and a compensation module for controlling the source voltage to fall according to the rise of the grid-source voltage or controlling the source voltage to rise according to the fall of the grid-source voltage, thereby suppressing a surge generated by the change of the grid-source voltage.
The invention controls the source voltage to inhibit the surge generated by the change of the voltage from the grid electrode to the source electrode, thereby solving the problem of the crosstalk phenomenon of the silicon carbide semiconductor power component.
Drawings
"fig. 1" is a schematic circuit diagram of a half-bridge circuit according to an embodiment of the present invention.
"figure 2" is a schematic voltage output diagram of a silicon carbide power device according to the present invention.
"fig. 3" is a logic schematic block diagram of an embodiment of the present invention.
"fig. 4" is a logic schematic block diagram of another embodiment of the present invention.
"fig. 5" is a schematic circuit diagram according to an embodiment of the present invention.
"fig. 6" is a logic schematic block diagram of another embodiment of the present invention.
"fig. 7" is a schematic circuit diagram of another embodiment of the present invention.
"fig. 8" is a logic schematic block diagram of "fig. 7".
"fig. 9" is a schematic diagram of voltage output according to the embodiment of "fig. 7".
"fig. 10" is a schematic operation flow chart of an embodiment of the present invention.
Detailed Description
The detailed description and technical contents of the present invention will now be described with reference to the drawings as follows:
the present invention shows a control method for a silicon carbide power device, which is applied to a driving circuit including a silicon carbide power device, and the silicon carbide power device may be an Insulated Gate Bipolar Transistor (IGBT), a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET), a Junction Field Effect Transistor (JFET), or other power devices. The silicon carbide power device is controlled by a driver and has a gate-to-source voltage (Vgs) and a source voltage (Vs).
Please refer to fig. 1, which is a schematic diagram of a half-bridge circuit to which the silicon carbide power component is applied according to an embodiment of the present invention, and the half-bridge circuit includes a controller 10, an upper bridge arm circuit 20 and a lower bridge arm circuit 30, where the upper bridge arm circuit 20 includes a first driver 21, a first silicon carbide power component 22, a first inductor 23, a first resistor 24 and a plurality of first capacitors 25, the first inductor 23 and the first resistor 24 are connected in series between the first driver 21 and the first silicon carbide power component 22, and the first capacitors 25 include a gate-drain capacitor 251, a gate-source capacitor 252 and a drain-source capacitor 253. The lower bridge arm circuit 30 includes a second driver 31, a second sic power device 32, a second inductor 33, a second resistor 34, and a plurality of second capacitors 35, where the second inductor 33 and the second resistor 34 are connected in series between the second driver 31 and the second sic power device 32, and the second capacitors 35 include a gate-drain capacitor 351, a gate-source capacitor 352, and a drain-source capacitor 353.
Please refer to fig. 2, which is a schematic diagram illustrating the voltage output of the sic power device according to an embodiment of the present invention, wherein the source voltage (Vs) has at least a high level (H), a low level (L), and a middle level (M) between the high level (H) and the low level (L). In the present invention, when the Gate-to-source voltages (Vgs) of the first and second sic power devices 22 and 32 rise according to the upper bridge driving signal (Gate signal 1) or the lower bridge driving signal (Gate signal 2), the source voltage (Vs) is controlled to fall from the middle level (M) to the low level (L) or from the high level (H) to the middle level (M); when the Gate-to-source voltages (Vgs) of the first and second silicon carbide power components 22 and 32 fall according to the upper bridge drive signal (Gate signal 1) or the lower bridge drive signal (Gate signal 2), the source voltage (Vs) is raised (L) from the low level to the middle level (M) or (H) from the middle level (M) to the high level (H).
As shown in "fig. 2", at time points (t1), (t5), the under-bridge driving signal (Gate signal 2) is decreased, so that the Gate-to-source voltage (Vgs) generates a negative peak, at which time the source voltage (Vs) is controlled to be increased from the middle level (M) to the high level (H) to suppress or reduce the spike (spike) of the Gate-to-source voltage (Vgs); at time points (t2), (t6), the upper bridge driving signal (Gate signal 1) rises, causing the Gate-to-source voltage (Vgs) to generate a positive peak, at which time the source voltage (Vs) is controlled to drop from the middle level (M) to the low level (L) to suppress or reduce the surge of the Gate-to-source voltage (Vgs); at a time point (t3), the upper bridge driving signal (Gate signal 1) is decreased to generate a negative peak of the Gate-to-source voltage (Vgs), and the source voltage (Vs) is controlled to increase from the middle level (M) to the high level (H) to suppress or reduce the surge of the Gate-to-source voltage (Vgs); at time (t4), the under-bridge driving signal (Gate signal 2) rises, causing a positive peak of the Gate-to-source voltage (Vgs), which controls the source voltage (Vs) to drop from the middle level (M) to the low level (L). "figure 2", Vgs is the voltage from gate to source without the method of the present invention, and the occurrence of the glitch is clearly observed; vgs' is the gate-to-source voltage using the method of the present invention, and it is evident that the glitch is suppressed and improved.
Please refer to fig. 3, which is a logic schematic block diagram of an embodiment of the present invention for explaining the determination and operation mechanism of the control method. In this embodiment, it is determined that the upper bridge driving signal (Gate signal 1) is rising or falling through the block 41 or 42, and that the lower bridge driving signal (Gate signal 2) is rising or falling through the block 43 or 44. The blocks 41 and 43 transmit a first result associated with the rise of the driving signal to the block 45 after the determination, and the blocks 42 and 44 transmit a second result associated with the fall of the driving signal to the block 46 after the determination, wherein the blocks 45 and 46 are an or gate in this embodiment. If any of the first results is valid, then the trigger block 47 controls the source voltage (Vs) to decrease; conversely, if the output of any of the second results is valid, the trigger block 48 controls the source voltage (Vs) to rise, thereby achieving the effect of suppressing or reducing the glitch of the gate-to-source voltage (Vgs).
Please refer to "fig. 4", which is a logic schematic block diagram of another embodiment of the present invention, compared to "fig. 3", this embodiment adds a block 491, a block 492, and a block 493, when the block 491 detects that the waveform of the upper bridge driving signal (Gate signal 1) or the lower bridge driving signal (Gate signal 2) changes, the output is changed (Edge trigger), and the rising or falling of the source voltage (Vs) is caused to have a delay τ through a block 492, the delay is the duration of the rising or falling of the source voltage (Vs), and finally the block 493 is triggered to make the rising or falling of the source voltage (Vs) continue for a period τ.
In the invention, the detection of the upper bridge driving signal (Gate signal 1) and the lower bridge driving signal (Gate signal 2) and the control of the Gate-to-source voltage (Vgs) may be performed by a compensation module, the compensation module includes a first compensation unit and a second compensation unit, the first compensation unit detects the upper bridge driving signal (Gate signal 1) and the lower bridge driving signal (Gate signal 2), the source voltage (Vs) is controlled to decrease when the Gate-to-source voltage (Vgs) increases based on the upper bridge driving signal (Gate signal 1) or the lower bridge driving signal (Gate signal 2), the second compensation unit detects the upper bridge driving signal (Gate signal 1) or the lower bridge driving signal (Gate signal 2), when the Gate-to-source voltage (Vgs) decreases based on the upper bridge driving signal (Gate signal 1) or the lower bridge driving signal (Gate signal 2), the source voltage is controlled to rise (Vs). Please refer to fig. 5, which is a schematic circuit structure diagram of an embodiment of the present invention, wherein a third-order gate driver (Three level gate driver) is taken as an example of the compensation module in the present embodiment, and the present embodiment includes a driver 21, a silicon carbide power device 22, a first inductor 23, a first resistor 24, a plurality of first capacitors 25, a first amplifier 26, and a second amplifier 27, where the first inductor 23 and the first resistor 24 are connected in series between the driver 21 and the silicon carbide power device 22, and the first capacitor 25 includes a gate-drain capacitor 251, a gate-source capacitor 252, and a drain-source capacitor 253. The driver 21 outputs a driving signal, which may be a positive voltage or a negative voltage, to the sic power device 22. The first amplifier 26 and the second amplifier 27 respectively receive a first input signal 261 and a second input signal 271, the first input signal 261 and the second input signal 271 are related to the driving signal, for example, when the driving signal is the positive voltage, the first input signal 261 and the second input signal 271 are both at a low level, and the source voltage decreases; when the driving signal is the negative voltage, the first input signal 261 and the second input signal 271 are both at a high level, and the source voltage rises (0 th level); when the driving signal is the positive voltage, the first input signal 261 and the second input signal 271 are both at a low level, and the source voltage decreases (level 1); when the driving signal changes to the negative voltage or to the positive voltage, the first input signal 261 and the second input signal 271 are at the high level and the low level, or at the low level and the high level, respectively, and the source voltage remains unchanged (2 nd level).
Please refer to "fig. 6", which is a logic schematic block diagram of another embodiment of the present invention, illustrated by a Cambridge Scanner one-shot circuit, wherein a block 61(G1 Rising Flag) and a block 62(G2 Rising Flag) respectively indicate that the upper bridge driving signal (Gate signal 1) and the lower bridge driving signal (Gate signal 2) are Rising, a nor Gate is used in a block 63, and a first one-shot flip-flop is used in a block 64. Block 65(G1 Dropping Flag) and block 66(G2 Dropping Flag) indicate that the upper bridge drive signal (Gate signal 1) and the lower bridge drive signal (Gate signal 2) are falling, respectively, block 67 is an or Gate, and block 68 is a second one-shot flip-flop. The first one-shot flip-flop of block 64 includes a nand gate 641, a capacitor 642, a resistor 643, and a not gate 644, and the second one-shot flip-flop of block 68 includes an or gate 681, a capacitor 682, a resistor 683, and a not gate 684.
Please refer to "fig. 7", which is a schematic circuit diagram of another embodiment of the present invention, compared to "fig. 5", in the present embodiment, a D-type flip-flop (D-latch flip-flop)28 is adopted, the D-type flip-flop (D-latch flip-flop)28 is coupled to a logic unit 70, wherein the D-type flip-flop 28 determines an output 283 according to a first input signal 281 and a second input signal 282 generated by the logic unit 70, a logic schematic block diagram of the logic unit 70 refers to "fig. 8", blocks 71 and 72 represent the upper bridge driving signal (Gate signal 1) and the lower bridge driving signal (Gate signal 2), respectively, block 73 is a delay, blocks 74 and 75 are an or Gate, and blocks 76 and 77 are inverters. After the upper bridge driving signal (Gate signal 1) and the lower bridge driving signal (Gate signal 2) are inputted into the logic unit 70, CLK signal,/DCLK signal and/DCLK signal are generated, wherein CLK signal and DCLK signal are the first input signal 281 and inputted into the D terminal of the D-type flip-flop 28, and/CLK signal,/DCLK signal are the second input signal 282 and inputted into the CLK terminal of the D-type flip-flop 28, and "" fig. 9 "is a voltage output diagram according to the embodiment of fig. 7.
Please refer to fig. 10, which is a flowchart illustrating an embodiment of the present invention. Considering the upper bridge drive signal (Gate signal 1) and the lower bridge drive signal as a pulse width modulation signal (PWM signal), when the state of the PWM signal changes (block 81), it is detected and adjusts the source voltage (Vs) to rise or fall (block 82), and will cause the Gate-to-source voltage (Vgs) to change (block 83), and the change of the Gate-to-source voltage (Vgs) will cause the drain-to-source voltage (Vds) to change (block 84) as well, and cause the Ringing phenomenon (block 85) of the Gate-to-source voltage (Vgs), wherein the change of the drain-to-source voltage (Vds) will generate Miller effect (block 86). Finally, the source voltage (Vs) is adjusted based on the change in the pwm signal to suppress or reduce the gate-to-source voltage (Vgs) glitch (block 87).
In summary, the present invention controls the source voltage to suppress the glitch caused by the variation of the gate-to-source voltage (Vgs), thereby solving the problem of crosstalk occurring in the sic semiconductor power device.
Claims (7)
1. A method of controlling a silicon carbide power module, the method comprising the steps of:
providing a silicon carbide power device controlled by a driver and having a gate-to-source voltage and a source voltage, the source voltage having at least a high level, a low level, and an intermediate level between the high level and the low level; and
the driver alternately outputs an upper bridge driving signal and a lower bridge driving signal to a gate of the silicon carbide power device, wherein the source voltage is lowered from the middle level to the low level or lowered from the high level to the middle level when the gate-to-source voltage is raised according to the upper bridge driving signal or the lower bridge driving signal, and the source voltage is raised from the low level to the middle level or raised from the middle level to the high level when the gate-to-source voltage is lowered according to the upper bridge driving signal or the lower bridge driving signal.
2. A silicon carbide power device controlled by a driver and having a gate-to-source voltage and a source voltage, wherein the source voltage falls in response to the gate-to-source voltage rising or the source voltage rises in response to the gate-to-source voltage falling, thereby suppressing a glitch caused by the change in the gate-to-source voltage.
3. The SiC power device of claim 2, wherein the source voltage has at least a high level, a low level, and an intermediate level between the high level and the low level, the driver alternately outputting an up-bridge driving signal and a down-bridge driving signal to a gate of the SiC power device, wherein the source voltage is lowered from the intermediate level to the low level or from the high level to the intermediate level when the gate-to-source voltage is raised according to the up-bridge driving signal or the down-bridge driving signal, and the source voltage is raised from the low level to the intermediate level or from the intermediate level to the high level when the gate-to-source voltage is lowered according to the up-bridge driving signal or the down-bridge driving signal.
4. A driver circuit, comprising:
a silicon carbide power device having a gate-to-source voltage and a source voltage;
a driver for controlling the silicon carbide power device; and
and the compensation module controls the source voltage to fall according to the rise of the grid-to-source voltage or controls the source voltage to rise according to the fall of the grid-to-source voltage, thereby inhibiting a surge generated by the change of the grid-to-source voltage.
5. The driving circuit of claim 4, wherein the compensation module receives an upper bridge driving signal and a lower bridge driving signal alternately output by the driver, and controls the source voltage to fall or rise according to the gate-to-source voltage rising or falling caused by the upper bridge driving signal and the lower bridge driving signal.
6. The driving circuit of claim 5, wherein the compensation module comprises a first compensation unit and a second compensation unit, the first compensation unit detects the upper bridge driving signal and the lower bridge driving signal to control the source voltage to decrease when the gate-to-source voltage increases based on the upper bridge driving signal or the lower bridge driving signal, the second compensation unit detects the upper bridge driving signal and the lower bridge driving signal to control the source voltage to increase when the gate-to-source voltage decreases based on the upper bridge driving signal or the lower bridge driving signal.
7. The driving circuit of claim 4, wherein the compensation module comprises a D-type flip-flop.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010075092.5A CN113162377A (en) | 2020-01-22 | 2020-01-22 | Silicon carbide power assembly, driving circuit and control method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010075092.5A CN113162377A (en) | 2020-01-22 | 2020-01-22 | Silicon carbide power assembly, driving circuit and control method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113162377A true CN113162377A (en) | 2021-07-23 |
Family
ID=76881866
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010075092.5A Pending CN113162377A (en) | 2020-01-22 | 2020-01-22 | Silicon carbide power assembly, driving circuit and control method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113162377A (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100156513A1 (en) * | 2008-12-23 | 2010-06-24 | Pratt & Whitney Rocketdyne, Inc. | Charge pump |
| CN103368362A (en) * | 2013-05-27 | 2013-10-23 | 苏州贝克微电子有限公司 | Driving circuit of dual-power field-effect tube under half-bridge configuration |
| CN104104369A (en) * | 2013-04-08 | 2014-10-15 | 富士通半导体股份有限公司 | Drive circuit, semiconductor integrated circuit, and control method of drive circuit |
| CN108809060A (en) * | 2017-05-01 | 2018-11-13 | 富士电机株式会社 | Driving device and switching device |
| CN110212740A (en) * | 2019-05-15 | 2019-09-06 | 中国矿业大学 | A kind of driving circuit inhibiting the crosstalk of SiC MOSFET gate pole and oscillation |
-
2020
- 2020-01-22 CN CN202010075092.5A patent/CN113162377A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100156513A1 (en) * | 2008-12-23 | 2010-06-24 | Pratt & Whitney Rocketdyne, Inc. | Charge pump |
| CN104104369A (en) * | 2013-04-08 | 2014-10-15 | 富士通半导体股份有限公司 | Drive circuit, semiconductor integrated circuit, and control method of drive circuit |
| CN103368362A (en) * | 2013-05-27 | 2013-10-23 | 苏州贝克微电子有限公司 | Driving circuit of dual-power field-effect tube under half-bridge configuration |
| CN108809060A (en) * | 2017-05-01 | 2018-11-13 | 富士电机株式会社 | Driving device and switching device |
| CN110212740A (en) * | 2019-05-15 | 2019-09-06 | 中国矿业大学 | A kind of driving circuit inhibiting the crosstalk of SiC MOSFET gate pole and oscillation |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN112821730B (en) | Novel driving topology, driving method thereof and crosstalk suppression method | |
| CN106301308B (en) | Active voltage drive control circuit for inhibiting turn-off overvoltage of SiC MOSFET (Metal oxide semiconductor field Effect transistor) and control method thereof | |
| CN110838787B (en) | SiC MOSFET active driving circuit for improving driving performance | |
| EP2801153B1 (en) | Apparatus and method for control of semiconductor switching devices | |
| JP2011239383A (en) | Switching gate driver | |
| KR20090014402A (en) | Switching circuit arrangement | |
| CN109842279B (en) | SiC MOSFET open-loop active driving circuit | |
| US20180191339A1 (en) | Gate Driver Controlling a Collector to Emitter Voltage Variation of an electronic Switch and Circuits Including the Gate Driver | |
| US11336277B2 (en) | Power MOSFET active gate drive based on negative feedback mechanism | |
| US10615779B1 (en) | Adaptive threshold control system for detecting and adjusting the duration of regions of operation during transistor turn on and turn off | |
| JP5480750B2 (en) | Semiconductor device driving apparatus and method | |
| US11843368B2 (en) | Method for reducing oscillation during turn on of a power transistor by regulating the gate switching speed control of its complementary power transistor | |
| CN112803727A (en) | Grid driving device and power conversion device | |
| JP5460520B2 (en) | Semiconductor device driving apparatus and method | |
| CN113541455A (en) | SiC MOSFET module continuously adjustable multi-level driving circuit | |
| CN216699815U (en) | Novel driving topology | |
| Frank | Simple slew-rate control technique cuts switching losses | |
| CN113067571A (en) | Silicon carbide MOSFET (Metal-oxide-semiconductor field Effect transistor) driving circuit with improved turn-off characteristic and control method | |
| CN113162377A (en) | Silicon carbide power assembly, driving circuit and control method | |
| US11184003B2 (en) | Silicon carbide power device, driving circuit and control method | |
| JP5462109B2 (en) | Semiconductor device driving apparatus | |
| TWI705664B (en) | Silicon carbide power element, drive circuit and control method | |
| CN114050712A (en) | Gate driving device and method | |
| CN112994417A (en) | Current change rate restraining device and converter system | |
| Choo et al. | A 3-level Active Gate Driver Network for SiC MOSFETs to Minimize Overshoot and Switching Losses |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |