CN113114185B - Gate drive circuit for inhibiting crosstalk, power device and drive method thereof - Google Patents
Gate drive circuit for inhibiting crosstalk, power device and drive method thereof Download PDFInfo
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- CN113114185B CN113114185B CN202110331013.7A CN202110331013A CN113114185B CN 113114185 B CN113114185 B CN 113114185B CN 202110331013 A CN202110331013 A CN 202110331013A CN 113114185 B CN113114185 B CN 113114185B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/082—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
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Abstract
The invention discloses a gate drive circuit, a power device and a driving method thereof for inhibiting crosstalk, which comprises the following steps: the power supply circuit, the driving resistor, the execution switch tube, the delay circuit and the power supply starting circuit; the power supply circuit is connected with the execution switch tube through the driving resistor; the execution switch tube is connected with the delay circuit to adjust the starting time of the execution switch tube; the execution switch tube is connected with the power supply starting circuit through the driving resistor so as to output the driving voltage of the execution switch tube. The power supply starting circuit controls the driving voltage of the output execution switch tube, and the delay circuit controls the on-time of the execution switch tube, so that the problem that the power module is damaged due to crosstalk in the switching process of the power module is solved.
Description
Technical Field
The invention relates to the technical field of power electronic devices, in particular to a gate drive circuit for inhibiting crosstalk, a power device and a drive method thereof.
Background
The statements in this section merely provide background information related to the present disclosure and may not necessarily constitute prior art.
Compared with a silicon device, the silicon carbide device has higher switching frequency, the higher switching frequency can aggravate the problem of grid crosstalk between an upper tube and a lower tube in the normal working process of the silicon carbide device due to the characteristic of high switching speed of the silicon carbide device, the severe grid crosstalk can cause two serious consequences, one is that a complementary tube is opened due to positive pressure overshoot in the opening process to cause a short circuit problem, and the other is that negative pressure overshoot of the complementary tube causes negative pressure breakdown in the closing process; secondly, the silicon carbide has lower conducting threshold voltage and poorer negative voltage breakdown resistance, so that the influence of the crosstalk problem on the power module under the high-frequency working condition is more serious, and the power module is more likely to be damaged due to the crosstalk problem.
Disclosure of Invention
In order to solve the problems, the invention provides a gate driving circuit, a power device and a driving method thereof for inhibiting crosstalk.
In order to achieve the purpose, the invention adopts the following technical scheme:
in a first aspect, the present invention provides a gate driving circuit for suppressing crosstalk, including: the power supply circuit, the driving resistor, the execution switch tube, the delay circuit and the power supply starting circuit; the power supply circuit is connected with the execution switch tube through the driving resistor, the execution switch tube is connected with the delay circuit to adjust the starting time of the execution switch tube, and the execution switch tube is connected with the power supply starting circuit through the driving resistor to output the driving voltage of the execution switch tube.
In a second aspect, the present invention provides a power device, where the gate driving circuit for suppressing crosstalk according to the first aspect is adopted.
In a third aspect, the present invention provides a gate driving method of a power device, including: and adjusting a driving resistance value in the power supply starting circuit according to a preset protection threshold value so as to enable the output voltage of the operational amplifier to be the grid electrode switching-on voltage of the execution switching tube, and adjusting the starting time through the delay circuit so as to drive the execution switching tube to act.
Compared with the prior art, the invention has the beneficial effects that:
the power supply starting circuit controls the driving voltage of the output switching tube, and does not need additional control signals to control the action of the switching tube, thereby effectively reducing the control difficulty of the driving circuit.
The invention can protect the power module from failure caused by crosstalk under the condition of fully exerting the advantage of high frequency of the silicon carbide.
The invention adopts the parallel time delay circuit, so that the turn-on time of each execution switch tube can be adjusted.
Advantages of additional aspects of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and together with the description serve to explain the invention and not to limit the invention.
Fig. 1 is a structural diagram of a gate driving circuit for suppressing crosstalk according to embodiment 1 of the present invention;
FIG. 2 is a timing diagram of waveforms of the switch tubes provided in embodiment 1 of the present invention;
fig. 3 is a graph showing an effect of a voltage waveform between gate and source electrodes of a complementary transistor before and after a protection circuit is added according to embodiment 1 of the present invention;
fig. 4 is a schematic diagram of a half-bridge circuit provided in embodiment 1 of the present invention.
The specific implementation mode is as follows:
the invention is further explained by the following embodiments in conjunction with the drawings.
It is to be understood that the following detailed description is exemplary and is intended to provide further explanation of the invention as claimed. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments according to the invention. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise, and it should be understood that the terms "comprises" and "comprising", and any variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The embodiments and features of the embodiments of the present invention may be combined with each other without conflict.
Example 1
As shown in fig. 1, the present embodiment provides a gate driving circuit for suppressing crosstalk, including: the power supply circuit, the driving resistor, the execution switch tube, the delay circuit and the power supply starting circuit; the power supply circuit is connected with the execution switch tube through the driving resistor, the execution switch tube is connected with the delay circuit to adjust the starting time of the execution switch tube, and the execution switch tube is connected with the power supply starting circuit through the driving resistor to output the driving voltage of the execution switch tube.
The crosstalk protection circuit provided by the embodiment can ensure that the power device is not damaged due to the crosstalk problem between the upper tube and the lower tube under the condition of fast switching, the high-frequency advantage of the silicon carbide device can be fully exerted while the device is protected, the switching time is reduced to reduce the switching loss, an extra control signal is not needed to control the execution switch tube in the protection process, the control difficulty can be reduced, and the advantage of the SIC power device is better exerted.
In the embodiment, the power supply circuit comprises a first power supply (DC), a first switching tube (Q1) and a second switching tube (Q2);
preferably, the collector of the first switching tube (Q1) is connected to the positive electrode of the first power supply (DC), the emitter of the first switching tube (Q1) is connected to the emitter of the second switching tube (Q2), and the collector of the second switching tube (Q2) is connected to the negative electrode of the first power supply (DC) and GND.
In the present embodiment, the driving resistors include a first driving resistor (R1) and a second driving resistor (R2);
preferably, one end of the first driving resistor (R1) is connected to an emitter of the first switching tube (Q1);
the other end of the first driving resistor (R1) is connected with one end of the second driving resistor (R2);
the other end of the first driving resistor (R1) is connected with the first power supply starting circuit through a second driving resistor (R2);
the other end of the first driving resistor (R1) is connected with the second power supply starting circuit;
the other end of the first driving resistor (R1) is connected with the grid of the power module (S1).
Preferably, the second driving resistor (R2) is a voltage detection resistor for obtaining a voltage across the gate and the source of the controlled power device;
the other end of the second driving resistor (R2) is connected with the source electrodes of the first power supply starting circuit, the delay circuit and the power module (S1); the first driving resistor (R1) and the second driving resistor (R2) are both connected with an execution switch tube.
In this embodiment, the power supply starting circuit includes a first power supply starting circuit and a second power supply starting circuit; the first power supply starting circuit comprises a sixth driving resistor (R6), a seventh driving resistor (R7), a first operational amplifier (OP 1) and a second power supply (VCC) which are connected in sequence; the second power supply starting circuit comprises a third driving resistor (R3), a fourth driving resistor (R4), a second operational amplifier (OP 2) and a second power supply (VCC) which are connected in sequence;
preferably, one end of the sixth driving resistor (R6) is connected to the seventh driving resistor (R7) and the input (-) of the first operational amplifier (OP 1); the other end of the sixth driving resistor (R6) is connected with the input end (+) of the second operational amplifier (OP 2);
preferably, the other end of the second driving resistor (R2) is connected to the first power supply starting circuit; specifically, the method comprises the following steps:
the other end of the second driving resistor (R2) is connected to the other end of the sixth driving resistor (R6) and an input end (+) of the second operational amplifier (OP 2).
Preferably, the other end of the seventh driving resistor (R7) is connected to the output end of the first operational amplifier (OP 1) and one end of the eighth driving resistor (R8-) of the complementary transistor.
Preferably, one end of the third driving resistor (R3) is connected to the fourth driving resistor (R4), the input end (-) of the second operational amplifier (OP 2); the other end of the third driving resistor (R3) is connected to one end of the second driving resistor (R2) and an input (+) of the first operational amplifier (OP 1).
Preferably, the other end of the fourth driving resistor (R4) is connected to the output end of the delay circuit and the second operational amplifier (OP 2).
Preferably, the other end of the first driving resistor (R1) is connected with the second power supply starting circuit; specifically, the method comprises the following steps: the other end of the first drive resistor (R1) is connected to the third drive resistor (R3) and an input (+) of the first operational amplifier (OP 1).
Preferably, the positive electrode and the negative electrode of the second power supply (VCC) are respectively connected with the power supply ends of the operational amplifiers of the first operational amplifier (OP 1) and the second operational amplifier (OP 2).
In this embodiment, the delay circuit includes a first delay circuit and a second delay circuit, where the first delay circuit includes an eighth driving resistor (R8) and a second driving capacitor (C2) connected in sequence; the second delay circuit comprises a fifth driving resistor (R5) and a first driving capacitor (C1) which are connected in sequence;
preferably, one end of the eighth driving resistor (R8) is connected with the second driving capacitor (C2), and the other end is connected with the output end of the first operational amplifier (OP 1-) of the complementary tube.
Preferably, the fifth driving resistor (R5) is connected with the base of the execution switch tube, the first driving capacitor (C1) and the output end of the complementary tube first operational amplifier (OP 1-).
Preferably, the first driving capacitor (C1) and the second driving capacitor (C2) are respectively connected to the second driving resistor (R2).
Preferably, the fourth drive resistor (R4) is connected to the fifth drive resistor (R5).
In the embodiment, the execution switch tube comprises a first execution switch tube and a second execution switch tube, the first execution switch tube is a fourth switch tube (Q4), and the second execution switch tube is a third switch tube (Q3);
preferably, the grid electrode of the fourth switching tube (Q4) is connected with the eighth driving resistor (R8) and the second driving capacitor (C2);
the drain electrode of the fourth switching tube (Q4) is connected with the other end of the first driving resistor (R1);
and the source electrode of the fourth switching tube (Q4) is connected with the other end of the second driving resistor (R2).
Preferably, the emitter of the third switching tube (Q3) is connected with the other end of the first driving resistor (R1);
the collector of the third switching tube (Q3) is connected with the other ends of the second driving resistor (R2) and the first driving capacitor (C1);
the base electrode of the third switching tube (Q3) is connected with a fifth driving resistor (R5).
In this embodiment, the device further includes components connected to the complementary transistor, that is, R8-, C2-, Q4-, OP1-, and G-, which are an eighth driving resistor of the complementary transistor, a second driving capacitor of the complementary transistor, a fourth switching transistor of the complementary transistor, a first operational amplifier of the complementary transistor, and a gate of the complementary transistor, respectively;
preferably, one end of an eighth driving resistor (R8-) of the complementary tube is connected with the output end of the first operational amplifier (OP 1), the other end of the eighth driving resistor is connected with one end of a second driving capacitor (C2-) of the complementary tube and a grid electrode of a fourth switching tube (Q4-) of the complementary tube, a source electrode of the fourth switching tube (Q4-) of the complementary tube is connected with the other end of the second driving capacitor (C2-), and a drain electrode of the fourth switching tube (Q4-) of the complementary tube is connected with the grid electrode of the complementary tube.
In the embodiment, taking the SIC MOSFET power device as an example, the third switching tube (Q3) controls a low-resistance state loop in the turn-off process of the complementary tube, and the fourth switching tube (Q4) controls a low-resistance state loop in the turn-on process of the complementary tube.
In the first power supply starting circuit, the output voltage value of the first operational amplifier (OP 1) is determined by a second driving resistor (R2), a sixth driving resistor (R6) and a seventh driving resistor (R7) on the voltage detection circuit, and the output voltage formula is as follows:
wherein Vout is an output voltage value of the operational amplifier, R6 and R7 are resistance values of the sixth driving resistor and the seventh driving resistor, respectively, and V2 is a voltage value at two ends of the second driving resistor R2.
In the second power supply starting circuit, the output voltage value of the second operational amplifier (OP 2) is determined by a second driving resistor (R2), a third driving resistor (R3) and a fourth driving resistor (R4) on the voltage detection circuit, and the output voltage formula is as follows:
wherein Vout is an output voltage value of the operational amplifier, R3 and R4 are resistance values of the third driving resistor and the fourth driving resistor, respectively, and V2 is a voltage value at two ends of the second driving resistor R2.
In the first delay circuit, the delay time is:
T 1 ＝R 8 C 2 ×ln[V out ×(V out -V th )]；
wherein, V out Representing the voltage value of the output end of the operational amplifier; v th The threshold voltage of the third switching tube is shown; r 8 Represents the resistance value of the eighth drive resistor; c 2 Representing the capacitance value of the second capacitor.
In the second delay circuit, the delay time is:
T 2 ＝R 5 C 1 ×ln[V out ×(V out -V th )]
wherein, V out Representing the voltage value of the output end of the operational amplifier; v th The threshold voltage of the third switching tube is represented; r 5 Represents the resistance value of the fifth drive resistor; c 1 Representing the capacitance value of the first capacitor.
The power supply starting circuit controls the driving voltage of the output execution switch tube, the delay circuit adjusts the starting time of the execution switch tube, and the execution switch tube provides a low-resistance state loop between the grid source electrodes to inhibit negative pressure overshoot, so that the power module is protected from being broken down by negative pressure; the timing diagram of the switching waveform of each execution switching tube is shown in fig. 2, and the voltage waveform between the gate and the source of the complementary tube before and after the protection circuit is added is shown in fig. 3.
It is appreciated that, based on the gate driving circuit for suppressing crosstalk described above, in further embodiments, there are further provided:
a power device adopts the gate drive circuit for inhibiting crosstalk.
A switching tube of a power conversion circuit of the power device adopts the gate drive circuit for inhibiting crosstalk to provide drive voltage.
A power converter adopts the grid drive circuit for restraining crosstalk, and is used for providing a drive voltage for a switch tube in the converter.
A gate driving method of a power device comprises the following steps: and adjusting a driving resistance value in the power supply starting circuit according to a preset protection threshold value so as to enable the output voltage of the operational amplifier to be the grid electrode switching-on voltage of the execution switching tube, and adjusting the starting time through the delay circuit so as to drive the execution switching tube to act.
Specifically, as shown in fig. 4, in the turn-on process of the half-bridge circuit, taking the upper tube as an example, the first switching tube (Q1 _ H) is turned on, after the second switching tube (Q2 _ H) is turned off, the upper tube (S1 _ H) starts to be turned on, and the gate turn-on voltage of the upper tube is DC _ H; during the turn-on process of the upper tube, the voltage between the drain and the source of the lower tube is rapidly increased to DC. Current flows through R1_ L rapidly in the change process of the voltage between the drain and the source of the lower tube, so that the voltage at two ends of the drain and the source of the lower tube is increased to V gs I.e. the voltage V across the voltage-sensing resistor R2 2 ＝V gs The positive input end of the first operational amplifier (OP 1) is V gs ；
Preset protection threshold, i.e. detection V 2 Voltage value at both ends, when V 2 And when the voltage values at the two ends reach the preset protection threshold value, the fourth switching tube (Q4 _ L) starts to work. Adjusting the resistance values of a sixth driving resistor (R6 _ L) and a seventh driving resistor (R7 _ L) according to a preset protection threshold value, so that the output voltage of the first operational amplifier (OP 1) can reach the grid electrode turn-on voltage of a fourth switching tube (Q4 _ L), and adjusting the delay time for starting the fourth switching tube (Q4 _ L) by adjusting the values of an eighth driving resistor (R8 _ L) and a second driving capacitor (C2 _ L);
when the voltage value of the upper tube grid source electrode reaches the set voltage threshold value, the first operational amplifier (OP 1) works, and the delay time T is passed 1 And then, the fourth switch tube (Q4 _ L) is opened, a low-resistance state loop between the grid and the source of the lower tube (S1 _ L) is provided, and current flows through the low-resistance state loop formed by the fourth switch tube (Q4 _ L) to achieve the purpose of inhibiting positive pressure overshoot, so that the effect of protecting the power module from short circuit due to crosstalk is achieved.
Taking the upper tube as an example, in the turn-off process, the first switch tube (Q1 _ H) is turned off, after the second switch tube (Q2 _ H) is turned on, the upper tube (S1 _ H) starts to be turned off, the gate turn-off voltage of the upper tube is 0V, the voltage between the drain and the source of the lower tube is rapidly reduced to 0V from DC in the turn-off process of the upper tube, and current rapidly flows through R1_ L, so that the voltage at two ends of the gate and the source of the lower tube is enabled to be rapidly reducedDown to V gs (V gs Less than 0), the voltage Vgs across the gate of the lower tube (S1 _ L) and the voltage V across the second drive resistor (R2 _ L) 2 The same;
preset protection threshold, i.e. detection V 2 Voltage value at both ends, when V 2 When the voltage values at the two ends reach the preset protection threshold value, the third switching tube (Q3 _ L) starts to work. Adjusting the resistance values of the third driving resistor (R3 _ L) and the fourth driving resistor (R4 _ L) according to a preset protection threshold value so that the output voltage of the second operational amplifier (OP 2) can reach the turn-on voltage of the third switching tube (Q3 _ L), and adjusting the delay time for starting the third switching tube (Q3 _ L) by adjusting the values of the fifth driving resistor (R5 _ L) and the first driving capacitor (C1 _ L);
when the voltage value V at the two ends of the second driving resistor (R2 _ L) 2 After reaching the set voltage value, the second operational amplifier (OP 2) starts to work and a delay time T is passed 2 And then the third switching tube (Q3 _ L) is opened, and a low-resistance state loop between the gate and the source of the lower tube (S1 _ L) is provided to inhibit negative voltage overshoot, so that the effect of protecting the power module from being broken down by negative voltage is achieved.
The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes will occur to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Although the embodiments of the present invention have been described with reference to the accompanying drawings, it is not intended to limit the scope of the invention, and it should be understood by those skilled in the art that various modifications and variations can be made without inventive changes in the technical solutions of the present invention.
Claims (9)
1. A gate drive circuit that suppresses crosstalk, comprising: the power supply circuit, the driving resistor, the execution switch tube, the delay circuit and the power supply starting circuit; the power supply circuit is connected with the execution switch tube through the driving resistor; the execution switch tube is connected with the delay circuit to adjust the starting time of the execution switch tube; the execution switch tube is connected with the power supply starting circuit through the driving resistor so as to output the driving voltage of the execution switch tube;
the delay circuit comprises a first delay circuit and a second delay circuit, and the first delay circuit comprises an eighth driving resistor and a second driving capacitor which are connected in sequence; the second delay circuit comprises a fifth driving resistor and a first driving capacitor which are connected in sequence.
2. The gate driving circuit for suppressing crosstalk according to claim 1, wherein the power supply circuit comprises a first power supply, a first switch tube, a second switch tube; the collector of the first switch tube is connected with the anode of the first power supply, the emitter of the first switch tube is connected with the emitter of the second switch tube, and the collector of the second switch tube is connected with the cathode of the first power supply.
3. The gate drive circuit for suppressing crosstalk of claim 2, wherein the driving resistors comprise a first driving resistor and a second driving resistor; one end of the first driving resistor is connected with an emitting electrode of the first switching tube; the other end of the first driving resistor is connected with one end of the second driving resistor; the first driving resistor and the second driving resistor are both connected with the execution switch tube.
4. The gate driving circuit for suppressing crosstalk according to claim 3, wherein the performing switching tube comprises a third switching tube and a fourth switching tube; the emitter of the third switching tube is connected with the first driving resistor; the collector of the third switch tube is connected with the second driving resistor, the source of the fourth switch tube is connected with the second driving resistor, and the drain of the fourth switch tube is connected with the first driving resistor.
5. The gate driving circuit for suppressing crosstalk according to claim 1, wherein the power supply starting circuit comprises a first power supply starting circuit and a second power supply starting circuit, and the first power supply starting circuit comprises a sixth driving resistor, a seventh driving resistor, a first operational amplifier and a second power supply which are connected in sequence; the second power supply starting circuit comprises a third driving resistor, a fourth driving resistor, a second operational amplifier and a second power supply which are connected in sequence.
6. The gate drive circuit for suppressing crosstalk of claim 5, wherein one end of the sixth driving resistor is connected to the input terminal of the second operational amplifier, and one end of the third driving resistor is connected to the input terminal of the first operational amplifier.
7. The gate driving circuit for suppressing crosstalk according to claim 1, wherein the performing switching transistors comprise a third switching transistor and a fourth switching transistor; the grid electrode of the fourth switching tube is connected with the eighth driving resistor and the second driving capacitor; the collector of the third switching tube is connected with the other end of the first driving capacitor; and the base electrode of the third switching tube is connected with the fifth driving resistor.
8. A power device employing a gate drive circuit for suppressing crosstalk according to any one of claims 1 to 7.
9. A gate driving method of the power device as claimed in claim 8, comprising: and adjusting a driving resistance value in the power supply starting circuit according to a preset protection threshold value so as to enable the output voltage of the operational amplifier to be the grid electrode switching-on voltage of the execution switching tube, and adjusting the starting time through the delay circuit so as to drive the execution switching tube to act.
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| JP5794246B2 (en) * | 2013-03-11 | 2015-10-14 | 株式会社デンソー | Gate drive circuit |
| CN108649777A (en) * | 2018-04-12 | 2018-10-12 | 南京航空航天大学 | A kind of eGaN HEMT bridge arm clutter reduction driving circuits and its control method |
| CN111404411B (en) * | 2020-02-26 | 2021-06-15 | 北京交通大学 | Three-level active driving circuit for inhibiting crosstalk |
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