CN116248094B

CN116248094B - Common mode transient suppression circuit and non-optical isolation direct current solid state relay

Info

Publication number: CN116248094B
Application number: CN202310059577.9A
Authority: CN
Inventors: 杨靖; 马春宇; 张峰; 张江风
Original assignee: Gl Microelectronics Inc
Current assignee: Gl Microelectronics Inc
Priority date: 2023-01-18
Filing date: 2023-01-18
Publication date: 2024-02-02
Anticipated expiration: 2043-01-18
Also published as: CN116248094A

Abstract

Provided herein are a common mode transient suppression circuit and a non-optically isolated DC solid state relay comprising: the current mirror module comprises a plurality of current mirror MOS (metal oxide semiconductor) tubes and a first comparison MOS tube; a signal control module; a shunt module; a second comparison MOS tube; through the signal control module and the shunt module which receive the first input signal and the second input signal, the current in the current mirror module can be distributed to the first comparison MOS tube and the second comparison MOS tube in proportion, one of the first comparison MOS tube and the second comparison MOS tube is in a linear region, so that the drain electrode of the second comparison MOS tube has the potential which changes along with the change of the first input signal and the second input signal, and the phenomenon that common mode interference causes a subsequent circuit to receive abnormal signals and further causes false triggering can be prevented.

Description

Common mode transient suppression circuit and non-optical isolation direct current solid state relay

Technical Field

The invention relates to the technical field of solid-state relays, in particular to a common-mode transient suppression circuit and a non-optical isolation direct-current solid-state relay.

Background

A non-optical isolation direct current Solid State Relay (SSR) widely used in the fields of numerical control devices, test instruments, computer terminals and the like is a four-port device, wherein two ports are input control ends and are connected with a microprocessor, a digital signal processor (DSP, digital Signal Processing) and the like for inputting signals; the other two ports are output controlled ends for controlling the power load. The input control end and the output load end are electrically isolated by using an isolator, and the purpose of directly driving a large current load is realized through a tiny input signal of the input end. The non-optical isolation direct current solid state relay not only can amplify driving signals, but also has an isolation function, so that the non-optical isolation direct current solid state relay is very suitable for driving a high-power switch tube. Compared with electromagnetic relay, the non-light isolated DC solid state relay has higher reliability, no contact, long service life, high speed and little interference to the outside.

However, the input port of the current non-optically isolated dc solid state relay is usually connected to a microprocessor (MCU, microcontroller Unit), logic device, etc., and when a common mode transient disturbance event occurs, the common mode signal disturbance may cause the power transistor on the high voltage side to be turned on by mistake.

Disclosure of Invention

In view of the foregoing problems in the prior art, an object of the present invention is to provide a common-mode transient suppression circuit and a non-optical isolation dc solid state relay, so as to solve the problem that when a common-mode transient interference event occurs in the non-optical isolation dc solid state relay in the prior art, common-mode signal interference may cause the false opening of a high-voltage side power tube.

In order to solve the technical problems, the specific technical scheme is as follows:

in one aspect, provided herein is a common mode transient suppression circuit comprising:

the current mirror module comprises a plurality of current mirror MOS (metal oxide semiconductor) tubes and a first comparison MOS tube; the signal control module comprises a plurality of control MOS tubes, and the drains of the control MOS tubes form two equivalent drain outputs; the shunt module comprises two shunt MOS tube groups, and each shunt MOS tube group is provided with a current receiving end; a second comparison MOS tube;

the current mirror MOS tube and the first comparison MOS tube are connected with an energy supply source and are coupled to generate mirror currents, and the mirror currents are respectively sent to the sources of the control MOS tubes through the current mirror MOS tube;

The grid electrodes of the control MOS tubes respectively receive a first input signal or a second input signal, and the output of the two equivalent drains are respectively connected with the current receiving end of each shunt MOS tube group;

the shunt MOS tube group distributes the mirror current according to the length-width ratio and then is coupled to the second comparison MOS tube;

the drain electrode of the second comparison MOS tube is connected with the drain electrode of the first comparison MOS tube, so that when the potential difference between the first input signal and the second input signal exceeds a threshold value range, the first comparison MOS tube works in a linear region and is opened, and the drain electrode of the second comparison MOS tube outputs a high level; when the potential difference between the first input signal and the second input signal is within the threshold range, the second comparison MOS tube is enabled to work in a linear region and is opened, and the drain electrode of the second comparison MOS tube outputs a low level.

As one embodiment herein, the current mirror module further comprises a first resistor; the current mirror MOS tube comprises a first PMOS tube, a third PMOS tube and a fourth PMOS tube;

the sources of the first PMOS tube, the third PMOS tube, the fourth PMOS tube and the first comparison MOS tube are connected with the energy supply power supply;

The grid electrode of the first PMOS tube is connected with the drain electrode, the grid electrode of the first PMOS tube is also connected with the grid electrode of the third PMOS tube, the grid electrode of the fourth PMOS tube and the grid electrode of the first comparison MOS tube, the drain electrode of the first PMOS tube is connected with one end of the first resistor, and the other end of the first resistor is grounded;

and the drains of the third PMOS tube and the fourth PMOS tube are connected with the source electrode of the control MOS tube.

As an embodiment herein, the plurality of control MOS transistors includes a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, and a tenth PMOS transistor;

the sources of the seventh PMOS tube and the ninth PMOS tube are connected with the drain electrode of the third PMOS tube;

the gates of the seventh PMOS tube and the tenth PMOS tube are connected with the first input signal;

the sources of the eighth PMOS tube and the tenth PMOS tube are connected with the drain electrode of the fourth PMOS tube;

the grid electrodes of the eighth PMOS tube and the ninth PMOS tube are connected with the second input signal;

the drains of the seventh PMOS tube and the eighth PMOS tube form the equivalent drain output, and the equivalent drain output is connected with a current receiving end of a shunt MOS tube group;

The drains of the ninth PMOS tube and the tenth PMOS tube form the equivalent drain output, and the equivalent drain output is connected with a current receiving end of a shunt MOS tube group.

As one embodiment herein, the shunt module includes a first shunt MOS stack and a second shunt MOS stack;

the first shunt MOS tube group comprises a fourth NMOS tube, and the drain electrode of the fourth NMOS tube is the current receiving end; the second shunt MOS tube group comprises a sixth NMOS tube and a seventh NMOS tube, and the drains of the sixth NMOS tube and the seventh NMOS tube jointly form the current receiving end;

the drain electrode of the fourth NMOS tube is connected with the drain electrode of the seventh PMOS tube and the drain electrode of the eighth PMOS tube, the grid electrode of the fourth NMOS tube is connected with the drain electrode, the grid electrode of the fourth NMOS tube is also connected with the grid electrode of the sixth NMOS tube, and the source electrode of the fourth NMOS tube is grounded;

the drain electrode of the sixth NMOS tube is connected with the drain electrode of the seventh NMOS tube, and the source electrode of the sixth NMOS tube is grounded;

the drain electrode of the seventh NMOS tube is respectively connected with the drain electrode of the ninth PMOS tube and the drain electrode of the tenth PMOS tube, the grid electrode of the seventh NMOS tube is connected with the drain electrode, the source electrode of the seventh NMOS tube is grounded, the grid electrode of the seventh NMOS tube is connected with the grid electrode of the second comparison MOS tube, and the source electrode of the second comparison MOS tube is grounded.

As an embodiment herein, further comprising:

the protection module is used for protecting the MOS tube with the grid connected with the first input signal and the second input signal;

the protection module comprises a second resistor and a third resistor;

the second resistor is arranged between the first input signal and the grid electrode of the seventh PMOS tube, and the first input signal is respectively connected with the grid electrode of the seventh PMOS tube and the grid electrode of the tenth PMOS tube through the second resistor;

the third resistor is arranged between the second input signal and the grid electrode of the eighth PMOS tube, and the second input signal is respectively connected with the grid electrode of the eighth PMOS tube and the grid electrode of the ninth PMOS tube through the third resistor.

As an embodiment herein, further comprising:

the voltage stabilizing module is used for stabilizing the voltage of the first input signal and the voltage of the second input signal;

the voltage stabilizing module comprises a second NMOS tube and a third NMOS tube;

the drain electrode of the second NMOS tube is connected with the grid electrode of the seventh PMOS tube, and the grid electrode and the source electrode of the second NMOS tube are grounded;

and the drain electrode of the third NMOS tube is connected with the grid electrode of the eighth PMOS tube, and the grid electrode and the source electrode of the third NMOS tube are grounded.

As an embodiment herein, further comprising:

the enabling module is used for enabling the common mode transient suppression circuit to be turned on/off through an enabling signal;

the enabling module comprises a first NMOS tube, a second PMOS tube, a fifth NMOS tube, an eighth NMOS tube and a sixth PMOS tube;

the drain electrode of the first NMOS tube is connected with the other end of the first resistor, the source electrode of the first NMOS tube is grounded, and the grid electrode of the first NMOS tube is connected with a third enabling signal;

the source electrode of the second PMOS tube is connected with the energy supply source, the drain electrode of the second PMOS tube is connected with the grid electrode of the third PMOS tube, and the grid electrode of the second PMOS tube is connected with the third enabling signal;

the drain electrode of the fifth NMOS tube is connected with the grid electrode of the fourth NMOS tube, the source electrode of the fifth NMOS tube is grounded, and the grid electrode of the fifth NMOS tube is connected with a second enabling signal;

the drain electrode of the eighth NMOS tube is connected with the grid electrode of the second comparison MOS tube, the source electrode of the eighth NMOS tube is grounded, and the grid electrode of the eighth NMOS tube is connected with the second enabling signal;

the source electrode of the sixth PMOS tube is connected with the energy supply source, the drain electrode of the sixth PMOS tube is connected with the drain electrode of the second comparison MOS tube, and the grid electrode of the sixth PMOS tube is connected with the third enabling signal.

As an embodiment herein, further comprising:

an enable signal generation module for receiving a first enable signal and generating the second enable signal and the third enable signal, respectively;

the enabling signal generation module comprises a fifth inverter and a sixth inverter, and the output end of the fifth inverter is connected with the input end of the sixth inverter;

the input end of the fifth inverter receives the first enabling signal, and the output end of the fifth inverter generates the second enabling signal;

the input end of the sixth inverter receives the second enabling signal, and the output end of the sixth inverter generates the third enabling signal.

As an embodiment herein, further comprising: the analog-to-digital conversion module is used for converting the high or low level output by the drain electrode of the second comparison MOS tube into a first output signal and a second output signal;

the analog-to-digital conversion module comprises a first schmitt trigger, a first inverter, a second inverter, a third inverter and a fourth inverter;

the input end of the first Schmitt trigger is connected with the drain electrode of the second comparison MOS tube, and the output end of the first Schmitt trigger is connected with the input end of the first reverser;

The output end of the first inverter is respectively connected with the input end of the second inverter and the input end of the fourth inverter;

the output end of the fourth inverter outputs the first output signal, the output end of the second inverter is connected with the input end of the third inverter, and the output end of the third inverter outputs the second output signal.

In another aspect, the disclosure also includes a non-optically isolated dc solid state relay provided with any one of the common mode transient suppression circuits.

As one embodiment herein, comprises: the low-voltage side, the coupling transmission module, the high-voltage side and the power tube;

the low-voltage side is provided with a first common mode transient suppression circuit;

the low-voltage side is used for receiving a first input signal and a second input signal, the first common mode transient suppression circuit detects whether the potential difference between the first input signal and the second input signal is within a threshold range, if so, the first common mode transient suppression circuit enables the low-voltage side to be cut off, and if the potential difference exceeds the threshold range, the low-voltage side converts the first input signal and the second input signal into coded signals and transmits the coded signals to the coupling transmission module;

The coupling transmission module is used for isolating and transmitting the coded signals to the high-voltage side;

the high-voltage side is used for receiving the coded signal and converting the coded signal into a decoded signal, and outputting a conducting signal to the power tube according to the decoded signal when the coded signal is at a high level;

the power tube is connected with the high-voltage signal and is conducted when receiving the conducting signal.

the high-voltage side is provided with a second common mode transient suppression circuit;

the low-voltage side is used for receiving a first input signal and a second input signal, converting the first input signal and the second input signal into coded signals when the first input signal is at a high level, and transmitting the coded signals to the coupling transmission module;

the high-voltage side is used for receiving the coded signal and converting the coded signal into a decoded signal, the second common mode transient suppression circuit detects whether the two ends of the coded signal are within a threshold range, if yes, the second common mode transient suppression circuit enables the high-voltage side to be cut off, and if exceeding, the high-voltage side outputs a conducting signal to the power tube according to the decoded signal;

the low-voltage side is provided with a first common mode transient suppression circuit, and the high-voltage side is provided with a second common mode transient suppression circuit;

the high-voltage side is used for receiving the coded signal and converting the coded signal into a decoded signal, the second common mode transient suppression circuit detects whether two ends of the coded signal are in a threshold range, if yes, the second common mode transient suppression circuit enables the high-voltage side to be cut off, and if exceeding, the high-voltage side outputs a conducting signal to the power tube according to the coded signal;

As one embodiment herein, the low voltage side further includes an ESD protection circuit, a bi-directional rectification circuit, a current limiting circuit, a rectification capacitor, an oscillator, and a first under-voltage latch-up circuit;

the energy supply power source comprises a first energy supply power source;

one end of the ESD protection circuit is connected with the input end of the first input signal, and the other end of the ESD protection circuit is connected with the input end of the second input signal, so as to prevent the input end of the first input signal and the input end of the second input signal at the low voltage side from being invalid caused by ESD phenomena;

the bidirectional rectifying circuit is used for receiving the first input signal and the second input signal processed by the ESD protection circuit, preventing abnormal current from flowing backward to the input end of the first input signal, and taking out signals with higher potentials of the first input signal and the second input signal and outputting the signals to the oscillator;

the current limiting circuit is connected with the bidirectional rectifying circuit and used for clamping the working current of the low-voltage side;

the rectifying capacitor is connected with the current limiting circuit;

the oscillator is used for receiving a first input signal, a second input signal and a second output signal, and converting the first input signal and the second input signal into the coding signal when the second output signal is at a low level;

The first under-voltage locking circuit is used for detecting the first energy supply power supply and turning off the low-voltage side when the first energy supply power supply is lower than a first voltage threshold.

As one embodiment herein, the oscillator includes a twenty-sixth PMOS transistor, a twenty-seventh PMOS transistor, a twenty-eighth PMOS transistor, a twenty-ninth PMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a third capacitor, a second capacitor, and an inductance;

the source electrode of the twenty-sixth PMOS tube is connected with the source electrode of the twenty-seventh PMOS tube, the grid electrode of the twenty-sixth PMOS tube is connected with the grid electrode of the twenty-seventh PMOS tube, and the drain electrode of the twenty-sixth PMOS tube is connected with the drain electrode of the twenty-seventh PMOS tube;

the source electrode of the twenty-seventh PMOS tube is connected with the first input signal or the second input signal, and the grid electrode of the twenty-seventh PMOS tube is connected with the second output signal;

the source electrode of the twenty-eighth PMOS tube is connected with the drain electrode of the twenty-sixth PMOS tube, the grid electrode of the twenty-eighth PMOS tube is connected with the drain electrode of the twenty-ninth PMOS tube, the drain electrode of the twenty-eighth PMOS tube is connected with the grid electrode of the twenty-ninth PMOS tube, and the source electrode of the twenty-ninth PMOS tube is connected with the drain electrode of the twenty-seventh PMOS tube;

The drain electrode of the twenty-eighth PMOS tube is connected with one end of the inductor, and the drain electrode of the twenty-ninth PMOS tube is connected with the other end of the inductor;

the drain electrode of the ninth NMOS tube is respectively connected with one end of the third capacitor, one end of the inductor, the grid electrode of the tenth NMOS tube and the drain electrode of the eleventh NMOS tube, the grid electrode of the ninth NMOS tube is connected with one end of the second capacitor, the drain electrode of the tenth NMOS tube is connected, and the source electrode of the tenth NMOS tube is connected with the source electrode of the ninth NMOS tube; the source electrode of the ninth NMOS tube is grounded;

the drain electrode of the tenth NMOS tube is respectively connected with the other end of the third capacitor, the other end of the inductor, the grid electrode of the ninth NMOS tube and the drain electrode of the twelfth NMOS tube; the two ends of the inductor output the coding signals;

the other end of the second capacitor is grounded;

the grid electrode of the eleventh NMOS tube is connected with the grid electrode of the twelfth NMOS tube, and the grid electrode of the eleventh NMOS tube is connected with the second output signal; the source electrode of the eleventh NMOS tube and the source electrode of the twelfth NMOS tube are grounded.

As one embodiment herein, the power supply includes a second power supply;

The high pressure side further comprises:

the rectification filter circuit is used for decoding the coded signal to obtain the decoded signal;

the grid control module is used for receiving the high level or the low level generated by the second common mode transient suppression circuit, and when the high level is received, the decoding signal is coupled and the conducting signal is output;

and the second undervoltage locking circuit is used for detecting the second energy supply power supply and switching off the high-voltage side when the second energy supply power supply is lower than a second voltage threshold value.

As one embodiment herein, the gate control module includes a sixteenth resistor, a seventeenth resistor, an eighteenth PMOS transistor, a nineteenth PMOS transistor, a twenty-second NMOS transistor, a twenty-third NMOS transistor, a twenty-fourth NMOS transistor, and a twenty-fifth NMOS transistor;

one end of the sixteenth resistor and the source electrode of the eighteenth PMOS tube are connected with the decoding signal, the other end of the sixteenth resistor is respectively connected with the grid electrode of the eighteenth PMOS tube and the grid electrode of the twenty-second NMOS tube, and the drain electrode of the eighteenth PMOS tube is connected with the drain electrode of the twenty-second NMOS tube;

the source electrode of the twenty-second NMOS tube is connected with the high-voltage side reference ground; the grid electrode of the twenty-second NMOS tube receives a first output signal;

The source electrode of the nineteenth PMOS tube is connected with the drain electrode of the eighteenth PMOS tube, the grid electrode of the nineteenth PMOS tube is connected with the second under-voltage locking circuit, and the drain electrode of the nineteenth PMOS tube is connected with the high-voltage side reference ground;

one end of the seventeenth resistor is connected with the source electrode of the nineteenth PMOS tube, and the other end of the seventeenth resistor is connected with the drain electrode of the nineteenth PMOS tube;

the drain electrode of the twenty-third NMOS tube is connected with the grid electrode, and the source electrode of the twenty-third NMOS tube is connected with the drain electrode of the twenty-fourth NMOS tube; the drain electrode of the twenty-third NMOS tube outputs a driving signal, and the driving signal is used for driving the power tube to be turned on or turned off;

the drain electrode of the twenty-fourth NMOS tube is connected with the grid electrode, and the source electrode of the twenty-fourth NMOS tube is connected with the drain electrode of the twenty-fifth NMOS tube;

and the drain electrode of the twenty-fifth NMOS tube is connected with the grid electrode, and the source electrode of the twenty-fifth NMOS tube is connected with the other end of the seventeenth resistor.

As one embodiment herein, the power tube includes a first power tube and a second power tube;

the grid electrode of the first power tube and the grid electrode of the second power tube are connected with the grid electrode control module and receive the driving signals, the source electrode of the first power tube is connected with the source electrode of the second power tube, and the source electrode of the second power tube is connected with the analog ground of the high voltage side.

As an embodiment herein, the power tube is disposed outside or inside the package of the high-voltage side corresponding chip.

By adopting the technical scheme, through the signal control module and the shunt module which receive the first input signal and the second input signal, the current in the current mirror module can be distributed to the first comparison MOS tube and the second comparison MOS tube in proportion, so that one linear region exists in the first comparison MOS tube and the second comparison MOS tube, the potential of the drain electrode of the second comparison MOS tube is pulled to the ground or an energy supply source, and the potential which changes along with the change of the first input signal and the second input signal appears in the drain electrode of the second comparison MOS tube, therefore, common mode interference can be prevented from causing a subsequent circuit to receive abnormal signals, and false triggering is prevented.

The foregoing and other objects, features and advantages will be apparent from the following more particular description of preferred embodiments, as illustrated in the accompanying drawings.

Drawings

In order to more clearly illustrate the embodiments herein or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments herein and that other drawings may be obtained according to these drawings without inventive effort to a person skilled in the art.

FIG. 1 illustrates a common mode transient suppression circuit schematic of an embodiment herein;

FIG. 2 shows a first type of schematic diagram of embodiments herein;

FIG. 3 shows a second type of schematic diagram of embodiments herein;

FIG. 4 shows a third type of schematic diagram of embodiments herein;

FIG. 5 illustrates a schematic diagram of a bi-directional rectifying circuit of an embodiment herein;

FIG. 6 shows a schematic diagram of an oscillator of an embodiment herein;

FIG. 7 illustrates a second under-voltage lockout circuit and gate control module schematic of an embodiment herein;

FIG. 8 illustrates a schematic diagram of a relay with bi-directional rectification for a single power tube of embodiments herein;

FIG. 9 shows a schematic diagram of a relay with bi-directional rectification for a dual power tube of embodiments herein;

FIG. 10 illustrates a schematic diagram of a relay with bi-directional rectification for a power tube containing package of embodiments herein;

FIG. 11 illustrates a schematic diagram of a relay without bidirectional rectification for a single power tube of embodiments herein;

fig. 12 shows a schematic of a relay without bidirectional rectification for the dual power tube of the embodiments herein. Description of the drawings:

11. a current mirror module;

12. a signal control module;

13. a shunt module;

14. a second comparison MOS tube;

15. a protection module;

16. a voltage stabilizing module;

17. An enabling module;

18. an enable signal generation module;

101. a first PMOS tube;

102. a second PMOS tube;

103. a third PMOS tube;

104. a fourth PMOS tube;

105. a first comparison MOS tube;

106. a sixth PMOS tube;

107. a seventh PMOS transistor;

108. an eighth PMOS tube;

109. a ninth PMOS transistor;

110. a tenth PMOS tube;

117. seventeenth PMOS transistor;

118. an eighteenth PMOS tube;

119. nineteenth PMOS transistor;

125. a twenty-fifth PMOS tube;

126. a twenty-sixth PMOS tube;

127. a twenty-seventh PMOS tube;

128. a twenty eighth PMOS tube;

129. a twenty-ninth PMOS tube;

201. a first NMOS tube;

202. a second NMOS tube;

203. a third NMOS tube;

204. a fourth NMOS tube;

205. a fifth NMOS tube;

206. a sixth NMOS tube;

207. a seventh NMOS tube;

208. an eighth NMOS tube;

209. a ninth NMOS transistor;

210. a tenth NMOS tube;

211. an eleventh NMOS transistor;

212. a twelfth NMOS transistor;

221. a twenty-first NMOS tube;

222. a twenty-second NMOS tube;

223. a twenty-third NMOS transistor;

224. a twenty-fourth NMOS transistor;

225. a twenty-fifth NMOS transistor;

301. a first resistor;

302. a second resistor;

303. a third resistor;

312. a twelfth resistor;

313. A thirteenth resistor;

314. a fourteenth resistor;

315. a fifteenth resistor;

316. a sixteenth resistor;

317. seventeenth resistance;

401. a first inverter;

402. a second inverter;

403. a third inverter;

404. a fourth inverter;

405. a fifth inverter;

406. a sixth inverter;

501. a first schmitt trigger;

601. a first diode;

602. a second diode;

603. a third diode;

604. a fourth diode;

609. a ninth diode;

610. a twelfth pole tube;

701. a first capacitor;

702. a second capacitor;

704. a fourth capacitor;

801. an inductance;

21. a low pressure side;

22. an ESD protection circuit;

23. a rectifying capacitor;

24. a bidirectional rectifying circuit;

25. a current limiting circuit;

26. a first under-voltage latch circuit;

27. a first common mode transient suppression circuit;

28. an oscillator;

32. a coupling transmission module;

33. a rectifying and filtering circuit;

41. a high pressure side;

42. a second under-voltage latch circuit;

43. a second common mode transient suppression circuit;

44. a gate control module;

51. a power tube.

Detailed Description

The following description of the embodiments of the present disclosure will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the disclosure. All other embodiments, based on the embodiments herein, which a person of ordinary skill in the art would obtain without undue burden, are within the scope of protection herein.

It should be noted that the terms "first," "second," and the like in the description and claims herein and in the foregoing figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments described herein may be capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, apparatus, article, or device that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed or inherent to such process, method, article, or device.

A common mode transient suppression circuit schematic as shown in fig. 1, comprising:

the current mirror module 11 comprises a plurality of current mirror MOS tubes and a first comparison MOS tube 105; the signal control module 12 comprises a plurality of control MOS tubes, and the drains of the control MOS tubes form two equivalent drain outputs; the shunt module 13 comprises two shunt MOS tube groups, and each shunt MOS tube group is provided with a current receiving end; a second comparison MOS transistor 14;

The current mirror MOS tube and the first comparison MOS tube 105 are both connected with an energy supply source and coupled to generate mirror currents, and the mirror currents are respectively sent to the sources of the control MOS tubes through the current mirror MOS tube;

the shunt MOS tube group distributes the mirror current according to the length-width ratio and then is coupled to the second comparison MOS tube 14;

the drain electrode of the second comparison MOS transistor 14 is connected to the drain electrode of the first comparison MOS transistor 105, so that when the potential difference between the first input signal and the second input signal exceeds the threshold range, the first comparison MOS transistor 105 is operated in the linear region and is turned on, and the drain electrode of the second comparison MOS transistor 14 outputs a high level; when the potential difference between the first input signal and the second input signal is within the threshold range, the second comparison MOS transistor 14 is operated in a linear region and is turned on, and the drain electrode of the second comparison MOS transistor 14 outputs a low level.

By adopting the technical scheme, through the signal control module 12 and the shunt module 13 which receive the first input signal and the second input signal, the current in the current mirror module 11 can be distributed to the first comparison MOS tube 105 and the second comparison MOS tube 14 in proportion, so that one linear region exists in the first comparison MOS tube 105 and the second comparison MOS tube 14, the potential of the drain electrode of the second comparison MOS tube 14 is pulled to the ground or the energy supply source, the potential which changes along with the change of the first input signal and the second input signal appears in the drain electrode of the second comparison MOS tube 14, and the occurrence of common mode interference can be prevented, so that the subsequent circuit receives abnormal signals and is triggered by mistake.

In this context, the current mirror module 11 in particular also comprises a first resistor 301; the current mirror MOS tube comprises a first PMOS tube 101, a third PMOS tube 103 and a fourth PMOS tube 104;

the sources of the first PMOS transistor 101, the third PMOS transistor 103, the fourth PMOS transistor 104, and the first comparison MOS transistor 105 are all connected to the power supply;

the gate of the first PMOS transistor 101 is connected to the drain, the gate of the first PMOS transistor 101 is further connected to the gate of the third PMOS transistor 103, the gate of the fourth PMOS transistor 104, and the gate of the first comparison MOS transistor 105, the drain of the first PMOS transistor 101 is connected to one end of the first resistor 301, and the other end of the first resistor 301 is grounded;

the drains of the third PMOS transistor 103 and the fourth PMOS transistor 104 are connected to the source of the control MOS transistor.

The plurality of control MOS transistors comprise a seventh PMOS transistor 107, an eighth PMOS transistor 108, a ninth PMOS transistor 109 and a tenth PMOS transistor 110;

the sources of the seventh PMOS transistor 107 and the ninth PMOS transistor 109 are connected to the drain of the third PMOS transistor 103;

the gates of the seventh PMOS transistor 107 and the tenth PMOS transistor 110 are connected to the first input signal;

The sources of the eighth PMOS transistor 108 and the tenth PMOS transistor 110 are connected to the drain of the fourth PMOS transistor 104;

the gates of the eighth PMOS transistor 108 and the ninth PMOS transistor 109 are connected to the second input signal;

the drains of the seventh PMOS transistor 107 and the eighth PMOS transistor 108 form the equivalent drain output, and the equivalent drain output is connected to a current receiving end of one of the shunt MOS transistor groups;

the drains of the ninth PMOS transistor 109 and the tenth PMOS transistor 110 form the equivalent drain output, and the equivalent drain output is connected to a current receiving end of one of the shunt MOS transistor sets.

The shunt module 13 comprises a first shunt MOS tube group and a second shunt MOS tube group;

the first shunt MOS tube group comprises a fourth NMOS tube 204, and the drain electrode of the fourth NMOS tube 204 is the current receiving end; the second shunt MOS tube group includes a sixth NMOS tube 206 and a seventh NMOS tube 207, and drains of the sixth NMOS tube 206 and the seventh NMOS tube 207 together form the current receiving end;

the drain electrode of the fourth NMOS transistor 204 is connected to the drain electrode of the seventh PMOS transistor 107 and the drain electrode of the eighth PMOS transistor 108, the gate electrode of the fourth NMOS transistor 204 is connected to the drain electrode, the gate electrode of the fourth NMOS transistor 204 is also connected to the gate electrode of the sixth NMOS transistor 206, and the source electrode of the fourth NMOS transistor 204 is grounded;

The drain electrode of the sixth NMOS transistor 206 is connected to the drain electrode of the seventh NMOS transistor 207, and the source electrode of the sixth NMOS transistor 206 is grounded;

the drain electrode of the seventh NMOS transistor 207 is connected to the drain electrode of the ninth PMOS transistor 109 and the drain electrode of the tenth PMOS transistor 110, the gate electrode of the seventh NMOS transistor 207 is connected to the drain electrode, the source electrode of the seventh NMOS transistor 207 is grounded, the gate electrode of the seventh NMOS transistor 207 is connected to the gate electrode of the second comparison MOS transistor 14, and the source electrode of the second comparison MOS transistor 14 is grounded.

In order to protect the MOS transistors with gates connected to the first input signal and the second input signal, a protection module 15 is also provided herein,

the protection module 15 includes a second resistor 302 and a third resistor 303;

the second resistor 302 is disposed between the first input signal and the gate of the seventh PMOS transistor 107, and the first input signal is connected to the gate of the seventh PMOS transistor 107 and the gate of the tenth PMOS transistor 110 through the second resistor 302 respectively;

the third resistor 303 is disposed between the second input signal and the gate of the eighth PMOS transistor 108, and the second input signal is connected to the gate of the eighth PMOS transistor 108 and the gate of the ninth PMOS transistor 109 through the third resistor 303, respectively.

In order to ensure signal stability after the first and second input signals are connected, a voltage stabilizing module 16 is provided herein for stabilizing the voltages of the first and second input signals;

the voltage stabilizing module 16 comprises a second NMOS tube 202 and a third NMOS tube 203;

the drain electrode of the second NMOS transistor 202 is connected to the gate electrode of the seventh PMOS transistor 107, and both the gate electrode and the source electrode of the second NMOS transistor 202 are grounded;

the drain electrode of the third NMOS transistor 203 is connected to the gate electrode of the eighth PMOS transistor 108, and both the gate electrode and the source electrode of the third NMOS transistor 203 are grounded.

To ensure that the transient suppression circuit can be turned off or on when in use, an enabling module 17 is also provided herein for enabling the common mode transient suppression circuit to be turned on/off by an enabling signal;

the enabling module 17 includes a first NMOS transistor 201, a second PMOS transistor 102, a fifth NMOS transistor 205, an eighth NMOS transistor 208, and a sixth PMOS transistor 106;

the drain electrode of the first NMOS tube 201 is connected to the other end of the first resistor 301, the source electrode of the first NMOS tube 201 is grounded, and the gate electrode of the first NMOS tube 201 is connected to a third input signal;

the source electrode of the second PMOS transistor 102 is connected to the power supply, the drain electrode of the second PMOS transistor 102 is connected to the gate electrode of the third PMOS transistor 103, and the gate electrode of the second PMOS transistor 102 is connected to the third input signal;

The drain electrode of the fifth NMOS tube 205 is connected to the gate electrode of the fourth NMOS tube 204, the source electrode of the fifth NMOS tube 205 is grounded, and the gate electrode of the fifth NMOS tube 205 is connected to the second input signal;

the drain electrode of the eighth NMOS transistor 208 is connected to the gate electrode of the second comparison MOS transistor 14, the source electrode of the eighth NMOS transistor 208 is grounded, and the gate electrode of the eighth NMOS transistor 208 is connected to the second input signal;

the source electrode of the sixth PMOS transistor 106 is connected to the power supply, the drain electrode of the sixth PMOS transistor 106 is connected to the drain electrode of the second comparison MOS transistor 14, and the gate electrode of the sixth PMOS transistor 106 is connected to the third input signal.

Herein, the enable signal is generated by a specific module, which may be an enable signal generating module 18 for receiving a first enable signal and generating the second enable signal and the third enable signal, respectively;

the enabling signal generating module 18 comprises a fifth inverter and a sixth inverter, wherein the output end of the fifth inverter is connected with the input end of the sixth inverter;

In order to ensure that the transient suppression circuit can stabilize the output signal, an analog-to-digital conversion module is provided herein, and the analog-to-digital conversion module is used for converting the high or low level output by the drain electrode of the second comparison MOS tube 14 into a first output signal and a second output signal;

the analog-to-digital conversion module comprises a first schmitt trigger 501, a first inverter 401, a second inverter 402, a third inverter 403 and a fourth inverter 404;

the input end of the first schmitt trigger 501 is connected with the drain electrode of the second comparison MOS tube 14, and the output end of the first schmitt trigger 501 is connected with the input end of the first inverter 401;

the output end of the first inverter 401 is respectively connected with the input end of the second inverter 402 and the input end of the fourth inverter 404;

the output end of the fourth inverter 404 outputs the first output signal, the output end of the second inverter 402 is connected to the input end of the third inverter 403, and the output end of the third inverter 403 outputs the second output signal.

The power supply may include a first power supply and a second power supply, the power supply being the first power supply when the common mode transient suppression circuit is disposed on the low voltage side, and the power supply being the second power supply when the common mode transient suppression circuit is disposed on the high voltage side.

In another aspect, a non-optical isolation dc solid state relay is provided with the common mode transient suppression circuit.

The non-optically isolated dc solid state relay herein includes three types, the first type having a common mode transient suppression circuit on the low voltage side 21 and the high voltage side 41 having no common mode transient suppression circuit. The second type is a common mode-free transient suppression circuit, the high voltage side 41 is provided with a common mode transient suppression circuit, the third type is that the low voltage side 21 is provided with a common mode transient suppression circuit, and the high voltage side 41 is also provided with a common mode transient suppression circuit.

In this context, the high voltage signal may be 5V or 15V or higher, which independently powers the power tube.

The first type of schematic shown in fig. 2 includes: low side 21, coupled transmission module 32, high side 41, and power tube 51;

the low voltage side 21 is provided with a first common mode transient suppression circuit 27;

the low voltage side 21 is configured to receive a first input signal and a second input signal, and the first common mode transient suppression circuit 27 detects whether a potential difference between the first input signal and the second input signal is within a threshold range, if so, the first common mode transient suppression circuit 27 turns off the low voltage side 21, and if so, the low voltage side 21 converts the first input signal and the second input signal into encoded signals and transmits the encoded signals to the coupling transmission module 32;

The coupling transmission module 32 is configured to transmit the encoded signal to the high voltage side 41 in isolation;

the high voltage side 41 is configured to receive the encoded signal and convert the encoded signal into a decoded signal, and output a turn-on signal to the power tube 51 according to the decoded signal when the decoded signal is at a high level;

the power tube 51 is connected to a high voltage signal and is turned on when receiving the on signal.

A second type of schematic diagram, shown in fig. 3, includes a low voltage side 21, a coupled transmission module 32, a high voltage side 41, and a power tube 51;

the high voltage side 41 is provided with a second common mode transient suppression circuit 43;

the low-voltage side 21 is configured to receive a first input signal and a second input signal, and convert the first input signal and the second input signal into encoded signals and transmit the encoded signals to the coupling transmission module 32 when the first input signal is at a high level;

the high voltage side 41 is configured to receive the encoded signal and convert the encoded signal into a decoded signal, and the second common mode transient suppression circuit 43 detects whether a threshold value is within a range between two ends of the encoded signal, if yes, the second common mode transient suppression circuit 43 turns off the high voltage side, and if exceeded, the high voltage side 41 outputs a turn-on signal to the power tube 51 according to the decoded signal;

A third type of schematic, as shown in fig. 4, includes: low side 21, coupled transmission module 32, high side 41, and power tube 51;

the low voltage side 21 is provided with a first common mode transient suppression circuit 27 and the high voltage side 41 is provided with a second common mode transient suppression circuit 43;

the low voltage side 21 is configured to receive a first input signal, a second input signal, and a low voltage power supply, and the first common mode transient suppression circuit 27 detects whether a potential difference between the first input signal and the second input signal is within a threshold range, if so, the first common mode transient suppression circuit 27 turns off the low voltage side 21, and if exceeded, the low voltage side 21 converts the first input signal and the second input signal into encoded signals and transmits the encoded signals to the coupling transmission module 32;

The low voltage side 21 herein further comprises an ESD protection circuit 22, a bi-directional rectification circuit 24, a current limiting circuit 25, a rectification capacitor 23 and an oscillator 28;

the ESD protection circuit 22 has one end connected to the input terminal of the first input signal and the other end connected to the input terminal of the second input signal, and is configured to prevent the input terminal of the first input signal of the low voltage side 21 from being disabled due to an ESD event;

the bidirectional rectifying circuit 24 is configured to receive the first input signal and the second input signal processed by the ESD protection circuit 22, and further configured to prevent an abnormal current from flowing backward to an input terminal of the first input signal, and to invert a potential lower than ground to a high potential;

the current limiting circuit 25 is connected with the bidirectional rectifying circuit 24 and is used for clamping the working current of the low-voltage side 21;

the rectifying capacitor 23 is connected with the current limiting circuit 25;

the oscillator 28 is configured to receive the first input signal, the second input signal, and the second output signal, and to convert the first input signal and the second input signal into the encoded signal when the second output signal is low.

All the circuits are described in detail below, and the bidirectional rectifying circuit shown in fig. 5 includes a first diode 601, a second diode 602, a third diode 603, and a fourth diode 604;

an anode of the first diode 601 is connected to the first input signal, and a cathode of the first diode 601 is connected to a cathode of the third diode 603;

the anode of the third diode 603 is connected to the second input signal and the cathode of the fourth diode 604, respectively;

an anode of the fourth diode 604 is connected to an anode of the second diode 602;

the cathode of the second diode 602 is connected to the anode of the first diode 601.

As shown in the schematic diagram of the oscillator in fig. 6, the oscillator 28 includes a twenty-sixth PMOS transistor 126, a twenty-seventh PMOS transistor 127, a twenty-eighth PMOS transistor 128, a twenty-ninth PMOS transistor 129, a ninth NMOS transistor 209, a tenth NMOS transistor 210, an eleventh NMOS transistor 211, a twelfth NMOS transistor 212, a third capacitor 703, a second capacitor 702, and an inductor 801;

the source electrode of the twenty-sixth PMOS transistor 126 is connected to the source electrode of the twenty-seventh PMOS transistor 127, the gate electrode of the twenty-sixth PMOS transistor 126 is connected to the gate electrode of the twenty-seventh PMOS transistor 127, and the drain electrode of the twenty-sixth PMOS transistor 126 is connected to the drain electrode of the twenty-seventh PMOS transistor 127;

The grid electrode of the twenty-seventh PMOS tube 127 is connected with the second output signal;

the source electrode of the twenty-eighth PMOS transistor 128 is connected to the drain electrode of the twenty-sixth PMOS transistor 126, the gate electrode of the twenty-eighth PMOS transistor 128 is connected to the drain electrode of the twenty-ninth PMOS transistor 129, the drain electrode of the twenty-eighth PMOS transistor 128 is connected to the gate electrode of the twenty-ninth PMOS transistor 129, and the source electrode of the twenty-ninth PMOS transistor 129 is connected to the drain electrode of the twenty-seventh PMOS transistor 127;

the drain electrode of the twenty-eighth PMOS transistor 128 is connected to one end of the inductor 801, and the drain electrode of the twenty-ninth PMOS transistor 129 is connected to the other end of the inductor 801;

the drain electrode of the ninth NMOS transistor 209 is connected to one end of the third capacitor 703, one end of the inductor 801, the gate electrode of the tenth NMOS transistor 210, and the drain electrode of the eleventh NMOS transistor 211, the gate electrode of the ninth NMOS transistor 209 is connected to one end of the second capacitor 702, the drain electrode of the tenth NMOS transistor 210 is connected, and the source electrode of the ninth NMOS transistor 209 is connected to the source electrode of the tenth NMOS transistor 210; the source electrode of the tenth NMOS transistor 210 is grounded;

the drain electrode of the tenth NMOS transistor 210 is connected to the other end of the third capacitor 703, the other end of the inductor 801, the gate electrode of the ninth NMOS transistor 209, and the drain electrode of the twelfth NMOS transistor 212, respectively; the two ends of the inductor 801 output the coded signal;

The other end of the second capacitor 702 is connected to ground;

the gate of the eleventh NMOS transistor 211 is connected to the gate of the twelfth NMOS transistor 212, and the gate of the eleventh NMOS transistor 211 is connected to the second output signal; the source of the eleventh NMOS transistor 211 and the source of the twelfth NMOS transistor 212 are both grounded.

The low pressure side 21 further comprises: a first under-voltage latch circuit 26 for detecting the low-voltage power supply and switching off the low-voltage side 21 when the low-voltage power supply is below a first voltage threshold.

Herein, the coupling transmission module 32 includes a coupling transmission module 32;

the coupling transmission module 32 is used for isolating and transmitting the encoded signal to the high voltage side 41.

The high pressure side 41 further comprises:

a rectifying and filtering circuit 33, configured to rectify the encoded signal to obtain the decoded signal;

a gate control module 44 for receiving the decoded signal, and outputting the on signal when a potential difference between the decoded signal and the high-voltage side 41 analog ground is greater than a threshold range;

a second under-voltage latch circuit 42 for detecting the high-voltage power supply and turning off the high-voltage side 41 when the high-voltage power supply is lower than a second voltage threshold.

The second under-voltage latch-up circuit and the gate control module schematic shown in fig. 7, the second under-voltage latch-up circuit 42 includes: a twelfth resistor 312, a thirteenth resistor 313, a fourteenth resistor 314, a fifteenth resistor 315, a ninth diode 609, a tenth diode 610, a twenty-first NMOS transistor 221, a seventeenth PMOS transistor 117, and a fourth capacitor 704;

an anode of the ninth diode 609 is connected to an anode of the twelfth diode 610, the anode of the tenth diode 610 receives the second power supply, and a cathode of the twelfth diode 610 is connected to one end of the fifteenth resistor 315;

the other end of the fifteenth resistor 315 is connected to the drain of the twenty-first NMOS transistor 221, and the drain of the twenty-first NMOS transistor 221 outputs a second feedback signal, where the second feedback signal is used to instruct the high-voltage side 41 to turn off/on, and the second feedback signal may be used herein as an enable signal of the high-voltage side;

the gate of the twenty-first NMOS 221 is connected to one end of the fourteenth resistor 314 and one end of the fourth capacitor 704, and the other end of the fourth capacitor 704 is connected to the source of the twenty-first NMOS 221;

the other end of the fourteenth resistor 314 is connected to the drain of the seventeenth PMOS transistor 117 and one end of the thirteenth resistor 313, and the other end of the thirteenth resistor 313 is connected to the other end of the fourth capacitor 704;

The gate of the seventeenth PMOS transistor 117 is connected to the other end of the thirteenth resistor 313 and one end of the twelfth resistor 312, respectively;

the other end of the twelfth resistor 312 is connected to the cathode of the ninth diode 609;

the gate control module 44 includes a sixteenth resistor 316, a seventeenth resistor 317, an eighteenth PMOS transistor 118, a nineteenth PMOS transistor 119, a twenty-second NMOS transistor 222, a twenty-third NMOS transistor 223, a twenty-fourth NMOS transistor 224, and a twenty-fifth NMOS transistor 225;

one end of the sixteenth resistor 316 and the source of the eighteenth PMOS transistor 118 are connected to the decoded signal after rectification and filtration, the other end of the sixteenth resistor 316 is connected to the gate of the eighteenth PMOS transistor 118 and the gate of the twenty-second NMOS transistor 222, and the drain of the eighteenth PMOS transistor 118 is connected to the drain of the twenty-second NMOS transistor 222;

the source of the twenty-second NMOS transistor 222 is connected to the high voltage side 41 with reference to ground; the gate of the twenty-second NMOS transistor 222 receives the first output signal;

a source electrode of the nineteenth PMOS transistor 119 is connected to a drain electrode of the eighteenth PMOS transistor 118, a gate electrode of the nineteenth PMOS transistor 119 is connected to a source electrode of the seventeenth PMOS transistor 117, and a drain electrode of the nineteenth PMOS transistor 119 is connected to the high-voltage side 41 with reference to ground;

One end of the seventeenth resistor 317 is connected to the source of the nineteenth PMOS transistor 119, and the other end of the seventeenth resistor 317 is connected to the drain of the nineteenth PMOS transistor 119;

the drain electrode of the twenty-third NMOS tube 223 is connected to the gate electrode, and the source electrode of the twenty-third NMOS tube 223 is connected to the drain electrode of the twenty-fourth NMOS tube 224; the drain electrode of the twenty-third NMOS transistor 223 outputs a driving signal, where the driving signal is used to drive the power transistor 51 to be turned on or turned off;

the drain electrode of the twenty-fourth NMOS transistor 224 is connected to the gate electrode, and the source electrode of the twenty-fourth NMOS transistor 224 is connected to the drain electrode of the twenty-fifth NMOS transistor 225;

the drain electrode of the twenty-fifth NMOS transistor 225 is connected to the gate electrode, and the source electrode of the twenty-fifth NMOS transistor 225 is connected to the other end of the seventeenth resistor 317.

In the above, in some cases, the power tube 51 is encapsulated inside the high-voltage side 41, and of course, in some cases, the power tube 51 may be removed from the high-voltage side 41 as a peripheral circuit of the high-voltage side 41, so that the relay schematic diagram with bidirectional rectification of the single power tube shown in fig. 8 may be obtained.

Likewise, the number of the power tubes 51 may be increased to two, and the power tubes 51 include a first power tube and a second power tube;

The gate of the first power tube and the gate of the second power tube are both connected with the gate control module 44 and receive the driving signal, the source of the first power tube is connected with the source of the second power tube, and the source of the second power tube is connected with the analog ground of the high voltage side 41. Thus, a relay schematic diagram with bi-directional rectification for a dual power tube as shown in fig. 9 can be obtained.

In addition, in some cases, to reduce the volume of the product, the bidirectional rectifying circuit 24 may be replaced by a diode, so as to obtain a relay schematic diagram with bidirectional rectification of the power tube package shown in fig. 10, a relay schematic diagram with no bidirectional rectification of the single power tube shown in fig. 11, and a relay schematic diagram with no bidirectional rectification of the dual power tube shown in fig. 12.

It should be understood that, in the various embodiments herein, the sequence number of each process described above does not mean the sequence of execution, and the execution sequence of each process should be determined by its functions and internal logic, and should not constitute any limitation on the implementation process of the embodiments herein.

It should also be understood that in embodiments herein, the term "and/or" is merely one relationship that describes an associated object, meaning that three relationships may exist. For example, a and/or B may represent: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.

Those of ordinary skill in the art will appreciate that the elements and algorithm steps described in connection with the embodiments disclosed herein may be embodied in electronic hardware, in computer software, or in a combination of the two, and that the elements and steps of the examples have been generally described in terms of function in the foregoing description to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, and are not repeated herein.

In the several embodiments provided herein, it should be understood that the disclosed systems, devices, and methods may be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. In addition, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices, or elements, or may be an electrical, mechanical, or other form of connection.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the elements may be selected according to actual needs to achieve the objectives of the embodiments herein.

In addition, each functional unit in the embodiments herein may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.

The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the technical solutions herein are essentially or portions contributing to the prior art, or all or portions of the technical solutions may be embodied in the form of a software product stored in a storage medium, including several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the embodiments herein. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

Specific examples are set forth herein to illustrate the principles and embodiments herein and are merely illustrative of the methods herein and their core ideas; also, as will be apparent to those of ordinary skill in the art in light of the teachings herein, many variations are possible in the specific embodiments and in the scope of use, and nothing in this specification should be construed as a limitation on the invention.

Claims

1. A common mode transient suppression circuit, comprising:

the current mirror module further comprises a first resistor; the current mirror MOS tube comprises a first PMOS tube, a third PMOS tube and a fourth PMOS tube;

the sources of the first PMOS tube, the third PMOS tube, the fourth PMOS tube and the first comparison MOS tube are all connected with an energy supply source;

the drains of the third PMOS tube and the fourth PMOS tube are connected with the source electrode of the control MOS tube; the signal control module comprises a plurality of control MOS tubes, and the drains of the control MOS tubes form two equivalent drain outputs; the shunt module comprises two shunt MOS tube groups, and each shunt MOS tube group is provided with a current receiving end; a second comparison MOS tube;

2. The common mode transient suppression circuit of claim 1, wherein the plurality of control MOS transistors comprises a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, and a tenth PMOS transistor;

3. The common mode transient suppression circuit of claim 2, wherein the shunt module comprises a first shunt MOS tube bank and a second shunt MOS tube bank;

4. The common mode transient suppression circuit of claim 2, further comprising:

the protection module comprises a second resistor and a third resistor;

5. The common mode transient suppression circuit of claim 2, further comprising:

6. A common mode transient suppression circuit according to claim 3, further comprising:

7. The common mode transient suppression circuit of claim 6, further comprising:

8. The common mode transient suppression circuit of claim 1, further comprising: the analog-to-digital conversion module is used for converting the high or low level output by the drain electrode of the second comparison MOS tube into a first output signal and a second output signal;

9. A non-optically isolated dc solid state relay provided with a common mode transient suppression circuit as claimed in any one of claims 1 to 8.

10. The non-optically isolated dc solid state relay of claim 9, comprising: the low-voltage side, the coupling transmission module, the high-voltage side and the power tube;

11. The non-optically isolated dc solid state relay of claim 9, comprising: the low-voltage side, the coupling transmission module, the high-voltage side and the power tube;

12. The non-optically isolated dc solid state relay of claim 9, comprising: the low-voltage side, the coupling transmission module, the high-voltage side and the power tube;

13. The non-optically isolated dc solid state relay of any one of claims 10-12, wherein the low side further comprises an ESD protection circuit, a bi-directional rectifier circuit, a current limiting circuit, a rectifier capacitor, an oscillator, and a first under-voltage latch-up circuit;

the energy supply power source comprises a first energy supply power source;

the bidirectional rectifying circuit is used for receiving the first input signal and the second input signal processed by the ESD protection circuit, preventing abnormal current from flowing backward to the input end of the first input signal, and outputting signals with higher potentials of the first input signal and the second input signal to the oscillator;

the rectifying capacitor is connected with the current limiting circuit;

14. The non-optically isolated dc solid state relay of claim 13, wherein the oscillator comprises a twenty-sixth PMOS transistor, a twenty-seventh PMOS transistor, a twenty-eighth PMOS transistor, a twenty-ninth PMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a third capacitor, a second capacitor, and an inductance;

the source electrode of the twenty-seventh PMOS tube is connected with the high level in the first input signal or the second input signal;

The grid electrode of the twenty-seventh PMOS tube is connected with a second output signal;

The other end of the second capacitor is grounded;

15. The non-optically isolated dc solid state relay of any one of claims 10 to 12, wherein the power supply comprises a second power supply;

the high pressure side further comprises:

16. The non-optically isolated dc solid state relay of claim 15, wherein the gate control module comprises a sixteenth resistor, a seventeenth resistor, an eighteenth PMOS transistor, a nineteenth PMOS transistor, a twenty-second NMOS transistor, a twenty-third NMOS transistor, a twenty-fourth NMOS transistor, and a twenty-fifth NMOS transistor;

17. The non-optically isolated dc solid state relay of claim 16, wherein the power tube comprises a first power tube and a second power tube;

18. The non-optically isolated dc solid state relay of claim 17, wherein the power tube is disposed outside or inside a package of the high side corresponding chip.