JPH11163632A - Oscillator circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an oscillator circuit which drastically reduces oscillation rise time and gets an oscillation output just after oscillation start. SOLUTION: A short-circuiting means 7 is placed side by side as an input terminal voltage biasing means of an inverting amplifier 1 between its input and output terminals, also, an output buffer circuit which receives an output of the amplifier 1 and performs an oscillation output always amplifies a minute amplitude output of the amplifier 1, the amplifier 1 is activated at the time of oscillation start, also, a vibrator 5 is excited by giving potential difference to both ends of the vibrator 5 and the intra-input-output terminal of the amplifier 1 is short-circuited by thereafter operating the means 7 in a prescribed period. Thus, because resonance current peak in the vibrator 5 is increased and minute vibrations of the vibrator 5 are promoted, it is possible to perform oscillation start at an early stage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillation circuit using a crystal oscillator or a ceramic oscillator, and more particularly to an oscillation circuit suitable for being incorporated in a semiconductor integrated circuit such as a microprocessor.

[0002]

2. Description of the Related Art A general oscillation circuit using a CMOS gate is shown in FIG.

In FIG. 11, a crystal oscillator or a ceramic oscillator (hereinafter, referred to as an oscillator) 5 and a feedback resistor 4 are connected in parallel between a terminal T1 and a terminal T2, and a terminal T1 and a ground (hereinafter, GND) are connected. Terminal T2 and GN
Capacitors 61 and 62 are connected between the capacitors D and D, respectively. A two-input NOR gate G1 forms an inverting amplifier 1. One input is connected to a terminal T1, the other is connected to a control terminal C1, and the output is connected via a resistor 3 to a terminal T1.
2 and an oscillation output terminal OUT via an output buffer circuit 2 composed of inverters G2, G3 and the like.

FIG. 11 shows an example in which a NOR gate is used as an inverting amplifier. In addition, an inverter, a NAND gate, a clocked inverter and the like are generally used. The control terminal C1 is provided for controlling the stop and start of the oscillation circuit. The control terminal C1 controls the stop and start of the oscillation circuit incorporated in a microprocessor or the like according to the operation mode, thereby reducing power consumption. It is used when aiming. The resistor 3 is provided for the purpose of preventing abnormal oscillation such as spurious oscillation, but may be omitted.

When the oscillation circuit shown in FIG. 11 is formed on a semiconductor integrated circuit, a normal NOR gate G1, an inverter G2,
A CMOS gate such as G3 and a resistor 3 are formed on the semiconductor integrated circuit, and other components are externally attached. The feedback resistor 4 may be formed on a semiconductor integrated circuit.

The operation of the oscillation circuit shown in FIG. 11 will be described below.

First, when the control terminal C1 is biased to the high level, the output of the NOR gate G1 is fixed to the GND level, and therefore the NOR gate G1 does not function as an inverting amplifier and the oscillation circuit is in a stopped state. At this time, the terminal T
2 is at the GND level, but the terminal T1 is also biased to the GND level by the feedback resistor 4.

Next, when the control terminal C1 is biased to the low level, the NOR gate G1 is activated and becomes capable of functioning as an inverting amplifier. However, since the terminal T1 is biased to the GND level, the output of the NOR gate G1, that is, the terminal The T2 side temporarily rises to the VCC level. As the potential of the terminal T2 rises, the capacitance 61 and the like on the terminal T1 side are charged by the feedback resistor 4, and the potential gradually rises. As the potential on the terminal T1 side rises, the output of the NOR gate G1, that is, the potential on the terminal T2, on the contrary, falls. And terminal T
1. The potential becomes stable when the potentials of both terminals T2 become about the logical threshold voltage of the NOR gate G1 (hereinafter referred to as VLT1). At this time, the gain of the NOR gate G1 as an inverting amplifier becomes maximum, and a positive feedback loop is formed between the NOR gate G1, ie, the inverting amplifier 1 and the oscillator 5, and oscillation starts. At the beginning of the oscillation, the oscillation is small with the VLT1 level as the center voltage. However, the oscillation amplitude is gradually expanded by the above-mentioned positive feedback loop, and eventually grows to the power supply VCC amplitude. The output amplitude of the inverting amplifier 1 is equal to the logical threshold voltage (hereinafter, VLT) of the inverter G2 in the output buffer 2.
2), the oscillation amplitude is amplified and the waveform is shaped by the inverters G2, G3, etc., and an oscillation output having a VCC amplitude appears at the oscillation output terminal OUT.

FIG. 11 shows the schematic operation waveforms described above.
The waveform of the output terminal OUT is shown by a solid line and a dotted line, and which one to take depends on the number of inverter stages in the output buffer 2.

[0010]

In the oscillation circuit shown in FIG. 11, even when the control terminal C1 goes low and the oscillation circuit is started, the inverting amplifier 1 has a sufficient gain until the potential of the terminal T1 is biased near VLT1. It is not possible to form a positive feedback loop necessary for starting oscillation. V at terminal T2
Since the amplitude gradually decreases from the CC level, even if amplification of the minute vibration by the inverting amplifier 1 is performed during that time, unless the output amplitude crosses the VLT 2, the inverter G
2, no oscillation output is obtained. Further, even if the terminals T1 and T2 are biased to VLT1 and the oscillation by the positive feedback loop of the inverting amplifier 1 and the oscillator 5 is started, VL
If the oscillation amplitude is not amplified to an amplitude corresponding to the voltage difference between T1 and VLT2, the amplification is not performed by the inverter G2 and the oscillation output cannot be taken out.

The time constant until the potential of the terminal T1 is biased near VLT1 depends on the feedback resistor 4.
Is usually about 1 MΩ, and the above time constant is relatively large. Further, taking into account the amplification delay of the positive feedback loop, the oscillation rise time in the waveform of FIG. 11 usually requires several hundred μs to several tens ms.

In the case where the oscillation circuit is incorporated in a microprocessor or the like and the oscillation output is used as a system clock source, no clock pulse is obtained during the oscillation rise time, and the process becomes impossible. is there. Therefore, the conventional example shown in FIG. 11 cannot cope with an application in which it is desired to execute some processing using the oscillation output immediately after the oscillation is started. In addition, during the oscillation rise time, the potential of the terminals T1 and T2 is at the intermediate potential, so that a through current flows in the CMOS gates such as the NOR gate G1 and the inverter G2. This means that the oscillation circuit consumes the current even though the oscillation output is not obtained, which results in completely invalid current consumption.

An object of the present invention is to provide an oscillation circuit in which the above-mentioned oscillation rise time is greatly shortened and an oscillation output is obtained immediately after the oscillation is started, and an oscillation circuit in which invalid current consumption is reduced. It is in. It is still another object of the present invention to provide an oscillation circuit that can realize them even at a low voltage operation.

[0014]

The object of the present invention is to provide a circuit for biasing the input terminal potential of an inverting amplifier near an operating voltage (eg, a logical threshold voltage) of the inverting amplifier and a small amplitude output of the inverting amplifier. An output buffer circuit that can always amplify and shape the waveform and send it to the oscillation output terminal is provided, activates the inverting amplifier when oscillation starts, and applies a potential difference between the terminals (that is, between both terminals of the oscillator) to connect the oscillator. This is achieved by energizing, and then operating the circuit means for a predetermined period so that an exciting current sufficient for the operation of the oscillator flows, thereby biasing the input terminal potential of the inverting amplifier to its operating voltage. You. The specific means corresponding to the low-voltage operation and the specific configuration of the output buffer circuit will be clarified in the embodiments.

When the oscillation is activated, the inverting amplifier is activated and a potential difference is applied between the terminals, so that an exciting current flows through the oscillator, and the oscillator starts micro-vibration. The vibration frequency is a resonance frequency determined by the equivalent inductance and capacitance of the oscillator. Immediately after excitation of this oscillator,
The potential difference between the terminals is still open, and the potential of both terminals gradually starts to shift toward the operating voltage of the inverting amplifier due to the feedback resistance. Thereafter, the circuit means is operated for a predetermined period to forcibly bias the input terminal potential of the inverting amplifier to a predetermined potential (for example, near VLT1) at which the inverting amplifier operates, thereby starting the function as the inverting amplifier. Therefore, the positive feedback loop between the inverting amplifier and the oscillator can be formed at an early stage. Further, by providing an output buffer circuit capable of always amplifying the output of the inverting amplifier, it is possible to extract the oscillation output of the power supply amplitude at an early stage even if the amplitude of the oscillator itself is still minute.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to FIG.

In FIG. 1, an oscillator 5 and a feedback resistor 4 are connected in parallel between terminals T1 and T2, and capacitors 61 and 62 are connected between terminals T1 and T2 and GND, respectively. . The oscillator 5 shows an equivalent circuit based on equivalent inductance and capacitance. The inverting amplifier 1 is constituted by a two-input NOR gate G1, one input of which is connected to a terminal T1.
The other is connected to the control terminal C1, and the output is connected to the terminal T2 via the resistor 3. And its terminal T1
Short-circuit means 7 is connected in parallel between the input and the output on the side. The short-circuit means 7 includes an NMOS transistor N1 having a gate connected to the control terminal C2, and a source and a drain connected to the input and the output of the inverting amplifier 1 on the terminal T1 side. An oscillation detection gate 21 is connected to the output of the inverting amplifier 1, and the output is connected to an oscillation output terminal OUT via a buffer circuit 22. The oscillation detection gate 21 and the buffer circuit 22 connect the output buffer shown in FIG. The circuit 2 is configured. The oscillation detection gate 21 is a two-input NOR constituting the inverting amplifier 1.
A two-input NOR gate G4 having the same configuration as the gate G1 is formed, and one input is biased to GND.
The buffer circuit 22 is composed of inverters G5, G6, etc., which are provided for further amplifying and waveform shaping the output of the oscillation detection gate 21 to obtain an oscillation output. What is necessary is just to set suitably as needed.

The operation of this embodiment will be described below.

First, when the control terminal C1 is biased to the high level, the output of the NOR gate G1 is fixed to the GND level, and the NOR gate G1 does not function as an inverting amplifier, and the oscillation circuit is in a stopped state. At this time, the terminal T
2 and the terminal T1 are both biased to the GND level by the feedback resistor 4. Since the output of the NOR gate G1, ie, the output of the inverting amplifier 1, is at the GND level, the output of the NOR gate G4, ie, the oscillation detection gate 21, is at the high level (power supply VCC).
Level) is fixed, and the oscillation output OUT is
High level or GND depending on the number of inverter stages of 2
Fixed to one of the levels.

At the start of oscillation, the NOR gate G1 is activated by first biasing the control terminal C1 to a low level (or a GND level). At this time, the terminal T1 side
NOR gate G1 because it was biased to GND level
The output, that is, the terminal T2 side temporarily rises to the VCC level. An exciting current is supplied to the oscillator 5 by the potential difference generated between the terminal T2 and the terminal T1 at this time, and the oscillator starts micro-vibration at a natural frequency, that is, a resonance frequency determined by an equivalent inductance, a capacitance, and the like. On the terminal T1 side, the capacitance 61 and the like are charged by the feedback resistor 4, and the potential starts to gradually rise. However, immediately after the NOR gate G1 is activated, it is still near the GND level, and the NOR gate G1 may still function as an inverting amplifier. In a state where it cannot be performed.

Thereafter, as shown by the waveform in FIG. 1, a one-shot pulse is applied to the control terminal C2 to turn on the NMOS transistor N1, that is, the short-circuit means 7 only for a predetermined period. When the NMOS transistor N1 is turned on, NOR
The input and output of the gate G1 are short-circuited, and both of the terminals T1 and T2 are biased to the VLT1 level. At this time, the capacity 6
The oscillator 5 flowing in a closed loop of the oscillators 1 and 62 and the oscillator 5
Can be bypassed to the short-circuit means 7 side, the impedance of the resonance current path decreases, and the resonance current peak increases. This also increases the voltage amplitude at the equivalent inductance Ls of the oscillator 5 and the like, which is advantageous for starting oscillation output.

When the one-shot pulse at the control terminal C2 ends and the level returns to the original level, the NMOS transistor N1 turns off the NMOS transistor N1.
At this time, the potentials of the terminal T1 and the terminal T2 are almost VL.
Since it is at the T1 level, the gain of the NOR gate G1, that is, the inverting amplifier 1, becomes maximum, a positive feedback loop is formed between the inverting amplifier 1 and the oscillator 5, and oscillation starts immediately. At the beginning of the oscillation, the output of the inverting amplifier 1 is a minute oscillation with the VLT1 level as the center voltage, and the oscillation detecting gate 21 receiving the oscillation causes the NOR gate G1 constituting the inverting amplifier 1 to receive the oscillation.
Since the NOR gate G4 has the same configuration as those described above, their logical threshold voltages are equal, so that the minute oscillation of the output of the inverting amplifier 1 centered at the VLT1 level can be immediately amplified. Inverter G in buffer circuit 22
Even if the logical threshold voltages of 5, G6 and the like deviate from VLT1, the output amplitude of the inverting amplifier 1 is once amplified by the oscillation detection gate 21, so that the amplification of the oscillation amplitude and the waveform shaping by the buffer circuit 22 also start immediately. can do.

The one-shot pulse width of the control terminal C2 may be a pulse width that is necessary and sufficient to bias the terminals T1 and T2 to the level VLT1, and may be, for example, about several μs or less. Therefore, compared to the conventional example in FIG.
An oscillation output can be obtained early from the start of activation of the oscillation circuit by the control terminal C1.

As described above, according to the present embodiment, a positive feedback loop between the inverting amplifier 1 and the oscillator 5 can be formed at an early stage from the start of oscillation, and the output of the inverting amplifier 1 is immediately amplified to output the output terminal OUT. Therefore, it is possible to obtain an oscillation circuit in which the time from the start of oscillation to the start of oscillation output, that is, the oscillation rise time is greatly reduced. Therefore, it is possible to obtain an oscillation circuit with reduced ineffective current consumption until the start of oscillation.

In FIG. 1, the inverting amplifier 1 and the oscillation detection gate 21 are constituted by NOR gates. However, the present invention is not limited to this. Low voltage operation such as an inverter, a NAND gate, a clocked inverter, or a load MOS type inverter is possible. Similar effects can be obtained by other gate configurations such as a gate corresponding to the above. Short-circuit means 7
The same operation can be realized by using, for example, a PMOS transistor or a transfer gate in which a PMOS transistor and an NMOS transistor are connected in parallel, other than the configuration using the NMOS transistor N1.
The resistor 3 should be set as required for stabilizing the oscillation, and can be omitted. These are the same in the following embodiments.

FIG. 2 shows a second embodiment of the present invention.

This embodiment is different from the first embodiment shown in FIG. 1 in that a gate is connected to the control terminal C3, and a source and a drain are connected to the power supply VCC and the output of the inverting amplifier 1, respectively.
The configuration is such that excitation current supply means 18 composed of a PMOS transistor P1 is added. FIG. 2 shows the control terminals C1 and C
2, and an example of the timing of an applied signal to C3 is also shown.

In the oscillation stop state, the control terminals C1,
By biasing C3 to the high level, the output of the inverting amplifier 1 is fixed to the GND level as in the first embodiment.
The PMOS transistor P1, that is, the exciting current supply means 18 is kept OFF.

Next, when the oscillation is started, the control terminal C1 is set to the low level to activate the NOR gate G1, and a low-level one-shot pulse is applied to the control terminal C3. While the control terminal C3 is at the low level, the PMOS transistor P1 is also turned on, thereby rapidly charging the terminal T2 and supplying an exciting current to the oscillator 5.

The control terminal C3 returns to the high level and the PMO
After the S transistor P1 is turned off, a one-shot pulse is applied to the control terminal C2 and NO
Short between the input and output of the R gate G1 and connect the terminals T1 and T2 to V
By biasing LT1, a positive feedback loop between the inverting amplifier 1 and the oscillator 5 is formed at an early stage.

According to the present embodiment, in addition to the effect of the first embodiment, the provision of the exciting current supply means 18 makes it necessary to supply the oscillator exciting current at the time of startup from the gate constituting the inverting amplifier 1. Since it has disappeared, the current driving capability of the gate constituting the inverting amplifier 1 can be set to such an extent that the oscillation state can be maintained, and an oscillation circuit with reduced current consumption can be obtained.

In this embodiment, the exciting current supply means 18 is provided on the terminal T2 side, but the same effect can be obtained by providing this on the terminal T1 side. In this case, the terminal T1 is biased to the VCC level by the exciting current supply means 18 simultaneously with the activation of the NOR gate G1, and the NOR gate G1 is turned on while the exciting current supply means 18 is ON.
The output goes to the GND level and a potential difference is applied between the terminals T1 and T2 to excite the oscillator 5.

When a NAND gate is used as the inverting amplifier 1, the oscillation stop state is such that the control terminal connected to the NAND gate input is set to Lo, contrary to the case of the NOR gate G1.
By setting the level to the w level, the potentials of the terminals T1 and T2 are both fixed to the High level side. In this case, the exciting current supply means 18 is connected to the terminal T1 or the terminal T2.
Provided between this pin and GND.
It will be pulled out to the ND side.

The exciting current supply means 18 shown in FIG.
Is constituted by the PMOS transistor P1, but the present invention is not limited to this. For example, an NMOS transistor or the like may be used.

In the following embodiments, the description of the exciting current supply means 18 is omitted unless it is particularly necessary. However, in any of the embodiments, it is possible to provide the exciting current supply means 18 together and to enjoy the effects of this embodiment. Needless to say.

FIG. 3 shows a third embodiment of the present invention.

In FIG. 3, the connection configuration of the inverting amplifier 1, the short-circuit means 7, the feedback resistor 4, the oscillator 5, and the capacitors 61 and 62 is the same as that of the first embodiment of FIG. The output is connected to the oscillation detection gate 21 via the coupling capacitor 8, and a feedback resistor 9 and a short circuit 10 are connected in parallel between the input and output of the oscillation detection gate 21. The short-circuit means 10 has a gate connected to the control terminal C4, and a source and a drain connected to the input and output of the oscillation detection gate 21, respectively.
It is constituted by a MOS transistor N2. The oscillation detection gate 21 includes a NOR gate G7, one input of which is connected to the coupling capacitor 8, and the other input of which is connected to the control terminal C1. The buffer circuit 22 receiving the output is the same as in the first embodiment of FIG.

The operation of this embodiment will be described below.

In the oscillation stop state, the control terminal C1 is
By biasing to the high level, the NOR gate G1
The output of the inverting amplifier 1 consisting of: and the output of the oscillation detection gate 21 consisting of the NOR gate G7 are fixed to the GND level,
The control terminals C2 and C4 are biased to the low level to
Short-circuit means 7, 1 composed of MOS transistors N1, N2
0 is set to the OFF state.

At the time of starting the oscillation, the control terminal C1 is set to the low level as in the first embodiment of FIG.
1 is activated to excite the oscillator 5, and then a one-shot pulse is applied to the control terminal C2 to short-circuit the terminals T1 and T2 by the short-circuit means 7 for a predetermined period. At this time, the NOR gate G7 for connecting the input to the control terminal C1 is also activated at the same time as the NOR gate G1. Thereafter, a one-shot pulse is also applied to the control terminal C4, and the NOR gate G7 is turned on by the short-circuit means 10 comprising the NMOS transistor N2. The output operating point is rapidly biased to its logic threshold voltage. When the one-shot pulse of the control terminal C4 returns, N
Since the input potential of the OR gate G7 has reached its logical threshold voltage, it immediately starts functioning as an oscillation detection gate.

The oscillation detecting gate 21 causes the inverting amplifier 1
When the output amplitude center voltage of the inverting amplifier 1 fluctuates due to a leak current or the like on the terminal T1 side while the small output amplitude is amplified, in the embodiment shown in FIGS. The input voltage level fluctuates from the logical threshold voltage, and the oscillation detection gate 21 may become insensitive and may not be able to output oscillation. However, according to this embodiment, the input impedance of the oscillation detection gate 21 is reduced by providing the feedback resistor 9 in the oscillation detection gate 21, and the output of the inverting amplifier 1 is received via the coupling capacitor 8. Oscillation detection gate 2 due to output voltage level fluctuation of inverting amplifier 1 as described above
1 has almost no effect on the input voltage level, and the oscillation detection gate 21 can always perform stable amplification at the operating point with its logical threshold voltage as the center voltage. Further, the operating point of the oscillation detection gate 21 can be quickly determined by the short-circuit means 10 at the time of starting the oscillation, and the oscillation detection gate 21 can be stabilized without extending the oscillation rise time.

The short-circuit means 10 and the control terminal C4 can be omitted by setting the feedback resistor 9 to a lower resistance than the feedback resistor 4 and the like so that the operating point of the oscillation detection gate 21 can be determined quickly. Is also possible.

The falling timing of the one-shot pulse at the control terminal C4, that is, the OFF timing of the short-circuit means 10, is
By delaying the fall of the control terminal C2, that is, the OFF timing of the short-circuiting means 7, as shown in the timing in FIG. It is also possible to prevent a decrease or the like.

According to this embodiment, in addition to the effects of the first embodiment, it is possible to obtain an oscillation circuit capable of stably generating an oscillation output even when the terminal voltage of the oscillator fluctuates.

In this embodiment, the control of the oscillation detection gate 21 is performed by the control terminal C1. However, the present invention is not limited to this. The activation of the oscillation detection gate 21 may not be performed simultaneously with the inverting amplifier 1. .

FIG. 4 shows a fourth embodiment of the present invention.

In FIG. 4, instead of the buffer circuit 22 in the third embodiment of FIG. 3, the gates of the PMOS transistor P2 and the PMOS transistor P3 are connected to each other, and the gate and drain of the PMOS transistor P2 are short-circuited. A current mirror circuit, a coupling capacitor 11 connected between the drain of the PMOS transistor P2 and the output of the oscillation detection gate 21, a bias means 12 connected between the drain of the PMOS transistor P2 and GND, and a PMOS. Bias means 13 connected between the drain of the transistor P3 and GND is provided, and an oscillation output is taken out using a connection point between the PMOS transistor P3 and the bias means 13 as an output OUT. The bias means 12 and 13 each have a resistance R
B1 and RB2.

The oscillation stop and start control in this embodiment is the same as in the third embodiment shown in FIG. Looking at the state immediately after the oscillation is started, in any of the embodiments, the oscillation detection gate 21 amplifies the small output amplitude of the inverting amplifier 1, but the amplitude is small and the output voltage amplitude level is still the logic threshold of the oscillation detection gate 21. It is near the value voltage. In order to increase the output amplitude of the oscillation detection gate 21, it is necessary to increase the minute output amplitude of the inverting amplifier 1 itself, and it takes a considerable time to expand the amplitude to the power supply VCC amplitude. In the third embodiment and the like in FIG. 3, the oscillation detection gate 2
When viewed from the inverter G5 in the buffer circuit 22 receiving one output, an intermediate level input voltage is applied, and if the inverter G5 or the like has a CMOS configuration, a through current will flow. Inverter G5 output amplitude is power supply V
If the current is not amplified to the CC amplitude, a through current will flow in the inverter G6.

In the third embodiment shown in FIG. 3 and the like, if the difference between the logic threshold voltages of the oscillation detection gate 21 and the inverter G5 in the buffer circuit 22 increases due to device variation or the like, the inverter G5 A time is required for the output amplitude of the oscillation detection gate 21 to increase to a voltage level at which the oscillation output is sensitive, which delays the start of the oscillation output. That is, the logical threshold voltage of the inverter G5 needs to be always near the center voltage level of the oscillation output of the oscillation detection gate 21.

This embodiment is to solve the above problem.

In FIG. 4, the bias means 12 is set so as to apply a current bias of, for example, about several μA to the PMOS transistor P2 to such an extent that current consumption does not matter so much, and keeps the PMOS transistor P2 active. As a result, the operating point of the PMOS transistor P2, that is, its drain voltage is changed from the power supply VCC to the PMOS transistor P2.
Is biased to a level reduced by the gate-drain voltage VGS. On the other hand, the output of the oscillation detection gate 21 starts to oscillate with the logic threshold voltage as the center voltage after the oscillation is started. The output voltage fluctuation of the oscillation detection gate 21 is caused by the displacement current of the coupling capacitor 11. PMO
This is converted into a change in drain current of the S transistor P2. That is, when the output voltage of the oscillation detection gate 21 fluctuates in a rising direction, the displacement current of the coupling capacitor 11 flows from the output side of the oscillation detection gate 21 to the drain side of the PMOS transistor P2, and the drain current of the PMOS transistor P2 Attenuate. Conversely, when the output voltage of the oscillation detection gate 21 fluctuates in the downward direction, the displacement current of the coupling capacitor 11 becomes PM
It flows in the direction from the drain side of the OS transistor P2 to the output side of the oscillation detection gate 21, and increases the drain current of the PMOS transistor P2. The change in the drain current of the PMOS transistor P2 is transmitted to the current mirror-connected PMOS transistor P3 side, multiplied by the mirror ratio, and appears as a change in the output current of the PMOS transistor P3. On the PMOS transistor P3 side, a drain current corresponding to a mirror ratio multiple of the bias current of the PMOS transistor P2 by the bias means 12 flows, but the above-mentioned fluctuation is superimposed thereon.
The drain current of the PMOS transistor P3 is equal to the resistance R
It flows to the bias means 13 composed of B2, is converted into a voltage amplitude, and is taken out from the output terminal OUT. As described above, according to the present embodiment, the output voltage fluctuation of the oscillation detection gate 21 is converted into the output current fluctuation of the PMOS transistor P2, and the output current fluctuation is amplified.
The oscillation amplitude can be amplified without depending on the center voltage level of the oscillation output of No. 1.

In the embodiment shown in FIG. 4, the DC bias current component of the bias means 12 also flows to the bias means 13 composed of the resistor RB2, causing a potential drop. Further, even at the peak point of the drain current of the PMOS transistor P3, the output terminal OUT potential becomes the divided potential of the on-resistance component of the PMOS transistor P3 and the resistor RB2. Therefore, the oscillation output voltage amplitude of the output terminal OUT in FIG. The amplitude becomes smaller than the amplitude between GND. However, if a CMOS inverter or the like is added to the output terminal OUT, the waveform can be easily shaped, and a voltage amplitude that is sufficiently larger than the output amplitude of the oscillation detection gate 21 can be obtained. The through current in the gate portion is much smaller than that in the inverter G5 in FIG.

In the configuration shown in FIG. 4, the resistors RB1 and RB2 are connected to suppress the DC bias current flowing through the bias means 12 and 13 and to obtain a large voltage amplitude from the output current amplitude of the PMOS transistor P3. Although it is necessary to have a relatively high resistance, this is disadvantageous in terms of integration. Therefore, as shown in FIG. 5, a configuration in which the resistors RB1 and RB2 are replaced with constant current circuits using MOS transistors can be adopted. Hereinafter, the configuration shown in FIG. 5 will be described.

In FIG. 5, the bias means 12 and 13 in FIG.
N5. The drain of the NMOS transistor N4 is connected to the drain of the PMOS transistor P2 and GND,
The source is also the PMOS transistor P3 drain and G
The drain and source of the NMOS transistor N5 are connected to ND, respectively. The gates and drains of the gates of the NMOS transistors N4 and N5 are short-circuited and the source is GN.
Commonly connected to the gate of NMOS transistor N3 connected to D. A current source 14 is provided between the drain of the NMOS transistor N3 and the power supply VCC.

Since the NMOS transistor N3, the NMOS transistor N4, and the NMOS transistor N5 are in a current mirror connection, the drain current of the NMOS transistor N4 and the NMOS transistor N5, that is, the bias current of the PMOS transistor P2 and the PMOS transistor P3 is a current source. 14 and their mirror ratios. Now the NMOS transistor N4
The mirror ratio of the NMOS transistor N5 to the PMOS transistor
If the mirror ratio is set to be the same as the transistor P2 and the PMOS transistor P3, the NMOS transistors N4 and P4
Since the drain currents of the MOS transistors P2 have the same value, the NMOS transistors N are respectively multiplied by the mirror ratio.
5 and the respective drain currents of the PMOS transistor P3 are also equal. According to such a bias setting, the current oscillation superimposed on the drain current of the PMOS transistor P3 during oscillation can be converted into a voltage amplitude without excess or deficiency, which will be described in detail below. In addition, this bias setting is performed by the PMOS transistors P2 and P3 for amplifying the oscillation current and the NMOS transistors N4 and N5 as the bias current sources.
This is realized by the mirror ratio setting based on the transistor dimensions and does not depend on the absolute value of the current source 14 or the like, so that it is very suitable for integration. The amplification operation according to this configuration will be described below.

Assuming that the output of the oscillation detection gate 21 has not yet started oscillating, at this time the PMOS
The drain current driving capabilities of the transistor P3 and the NMOS transistor N5 are in a state of being exactly balanced as described above. Oscillation starts from that state and oscillation detection gate 2
If the oscillation output voltage oscillation of No. 1 oscillates in the voltage decreasing direction and the drain current of the PMOS transistor P3 oscillates in the increasing direction, the drain current driving capability of the PMOS transistor P3 exceeds that of the NMOS transistor N5. The operating point rapidly rises toward the power supply VCC. Then, the potential rises from the power supply VCC to the potential lowered by the voltage VDS between the drain and source of the PMOS transistor P3 which can supply the drain current of the NMOS transistor N5, and is stabilized. Conversely, when the oscillation output voltage oscillation of the oscillation detection gate 21 swings in the voltage increasing direction and the drain current of the PMOS transistor P3 swings in the decreasing direction, the drain current driving capability of the PMOS transistor P3 falls below that of the NMOS transistor N5. The operating point of the output terminal OUT rapidly drops toward the GND potential. Then, the potential is stabilized at the potential floating from GND by the drain-source voltage VDS of the NMOS transistor N5 which can flow the drain current of the PMOS transistor P3. Since the VDS voltages of the PMOS transistor P3 and the NMOS transistor N5 are both in the non-saturation region, their values are relatively small, so that the voltage amplitude of the output terminal OUT can be close to the power supply VCC voltage. it can.

As described above, according to the fourth embodiment shown in FIG. 4 or 5, in addition to the effects of the third embodiment, a CMOS
By amplifying the small oscillation voltage amplitude by using a current mirror circuit instead of the gate, it is possible to avoid a problem of a through current in the case of using a CMOS gate, and to obtain an oscillation circuit effective for reducing current consumption. In addition, since the oscillation voltage oscillation is converted to current oscillation via the coupling capacitor and amplified, it is possible to extract and amplify only the voltage variation without depending on the center voltage level of the oscillation voltage oscillation,
It is possible to obtain an oscillation circuit capable of stably obtaining an oscillation output even when the oscillation operating point level fluctuates due to device variation.

In the third embodiment shown in FIG. 3 and the like, when a gate of a load MOS type inverter or the like is used for the inverting amplifier 1 and the oscillation detection gate 21 to perform an oscillation operation at a low voltage of about 2 V or less, for example. If the buffer circuit 22 is formed of a CMOS gate, the CMOS gate will not respond unless the output amplitude of the oscillation detection gate 21 is sufficiently enlarged, and the start of oscillation output will be delayed. Also, if the sensitivity of the buffer circuit 22 at a low voltage is increased by using a gate of a load MOS inverter or the like, the current consumption increases accordingly.

According to the present embodiment, the current mirror circuit can be operated if there is a voltage equal to or higher than the threshold voltage Vth of the MOS transistor constituting the current mirror circuit. There is also an effect that a suitable oscillation circuit can be obtained.

In FIGS. 4 and 5, the configuration of the coupling capacitor 8 and the oscillation detection gate 21 shown in FIG. 3 is used as the output buffer of the inverting amplifier 1.
If there is no problem in the amplification by the current mirror circuit of the S transistors P2 and P3, this need not be used. That is, the coupling capacitance 8 and the oscillation detection gate 21 are eliminated,
The coupling capacitance 11 may be directly connected to the output of the inverting amplifier 1. This should be determined as appropriate in design. In FIGS. 4 and 5, the output of the current mirror circuit is used as the oscillation output terminal OUT. However, as described above, especially during the period in which the oscillation voltage amplitude is very small immediately after the start of oscillation, the oscillation output is generated due to the bias current. The operating point amplitude of the terminal OUT is at the intermediate level and does not become the power supply VCC amplitude.
Therefore, a CMOS gate or the like may be provided at the terminal OUT in FIGS. 4 and 5, and an output of the gate may be used as an oscillation output terminal to obtain an oscillation output having a power supply VCC amplitude. However, in any of the embodiments, when the oscillation circuit is used by being integrated on a semiconductor substrate, a CMOS gate or the like which always receives the oscillation output terminal OUT exists, and the CMO
Waveform shaping is performed in the S gate and the like. In the embodiments of the present invention shown in FIG. 4 and subsequent figures, the description of those waveform shaping buffer gates is omitted, and only the constituent elements that characterize the present invention are described.

FIG. 6 shows a fifth embodiment of the present invention.

In FIG. 6, the configuration from the periphery of the oscillator 5 to the oscillation detection gate 21 is the same as that of the third embodiment shown in FIG. The first transistor is formed by connecting the gates of the PMOS transistor P2 and the PMOS transistor P3 to each other and short-circuiting the gate and the drain of the PMOS transistor P2.
Current mirror circuit, and a bias current source 16 connected between the drain of the PMOS transistor P2 and GND.
And an NMOS transistor N6 connecting the gates of the NMOS transistor N6 and the NMOS transistor N7 to each other.
A second current mirror circuit formed by short-circuiting the gate and the drain on the side, a bias current source 17 connected between the drain of the NMOS transistor N6 and the power supply VCC,
A coupling capacitor 11 connected between the drain of the PMOS transistor P2 and the output of the oscillation detection gate 21;
MOS transistor N6 drain and oscillation detection gate 2
A coupling capacitor 15 connected between the output terminal and one output is provided, and the drain of the PMOS transistor P3 and the drain of the NMOS transistor N7 are connected to form an oscillation output terminal OUT.

The operation of this embodiment will be described below. Note that the control of the oscillation stop, start, and the like is the same as in the third and fourth embodiments, and thus the description is omitted.

The dimensions of each MOS transistor are set so that the mirror ratios of the first current mirror circuit and the second current mirror circuit are the same.
Assuming that the current values of the transistors 17 are set to the same level, the outputs of the current mirror circuits, that is, the drain currents of the PMOS transistor P3 and the NMOS transistor N7 are substantially equal. The operation when the oscillation detection gate 21 starts oscillating output in this state will be described below. Here, the bias current sources 16 and 17 are PMO
It supplies a bias current for keeping the S transistor P2 and the NMOS transistor N6 in an active state, and is provided for the same purpose as the bias means 12 in FIGS.

First, when the oscillation output voltage oscillation of the oscillation detection gate 21 swings in the rising direction, the coupling capacitors 11 and 15
Generates displacement currents from the output of the oscillation detection gate 21 to the drain of the PMOS transistor P2 and from the output of the oscillation detection gate 21 to the drain of the NMOS transistor N6. As a result, the drain current on the PMOS transistor P2 side fluctuates in the attenuating direction, and the drain current on the NMOS transistor N6 side fluctuates in the increasing direction.
The drain current of the S transistor P3 and the NMOS transistor N7 fluctuates. As a result, the drain current drivability of the NMOS transistor N7 exceeds the drain current drivability of the PMOS transistor P3, and the operating point of the oscillation output terminal OUT rapidly drops toward the GND potential.

Next, when the oscillation output voltage oscillation of the oscillation detection gate 21 swings in the downward direction, the coupling capacitances 11, 1
5, displacement currents from the drain of the PMOS transistor P2 to the output of the oscillation detection gate 21 and the displacement current from the drain of the NMOS transistor N6 to the output of the oscillation detection gate 21 are generated. As a result, the drain current of the PMOS transistor P2 increases, and the drain current of the NMOS transistor N6 increases.
The drain current on the side fluctuates in the decay direction, and the current fluctuation is again multiplied by the mirror ratio, and becomes the drain current fluctuation of the PMOS transistor P3 and the NMOS transistor N7 which are current mirror-connected to them. As a result, this time PMO
The drain current drive capability of the S transistor P3 is NMOS
The operating point of the oscillation output terminal OUT rapidly exceeds the power supply VCC because the drain current driving capability of the transistor N7 is exceeded.
It rises toward the potential.

In the present embodiment, since the PMOS transistor P3 and the NMOS transistor N7 operate exclusively, the load driving capability of the oscillation output terminal OUT can be improved, and the fourth embodiment is more effective than the fourth embodiment. An enlarged oscillation output amplitude can be obtained. This is because, for example, when the current driving capability of the PMOS transistor P3 is increased to increase the potential of the oscillation output terminal OUT,
Since the drain current on the NMOS transistor N7 side is attenuated, the load current for the PMOS transistor P3 is attenuated, and the load driving capability of the PMOS transistor P3 is relatively improved, thereby rapidly raising the potential of the oscillation output terminal OUT. At this time, the PMOS transistor P3
Attenuates the load current, the potential drop between the source and the drain of the PMOS transistor P3 decreases, and the potential reached by the oscillation output terminal OUT becomes closer to the power supply VCC. The same applies to the case where the current driving capability of the NMOS transistor N7 increases.
Since the voltage approaches the potential, the amplitude of the oscillation output voltage can be increased as compared with the fourth embodiment.

The displacement current of the coupling capacitors 11 and 15 due to the oscillation output voltage amplitude of the oscillation detection gate 21 is:
When the oscillation voltage amplitude increases to a level exceeding the current values of the current sources 16 and 17, the PMOS transistor P2 or N
Since one of the MOS transistors N6 is turned off, the PMOS transistor P3 and the NMOS transistor N
7 is a completely exclusive operation, and an oscillation output of the power supply VCC voltage amplitude is obtained at the oscillation output terminal OUT.

According to this embodiment, it is possible to obtain an oscillation circuit in which the oscillation output characteristics are further improved in addition to the effects of the fourth embodiment.

FIG. 7 shows a sixth embodiment of the present invention.

In FIG. 7, in addition to the configuration of FIG.
A third current mirror circuit in which the gates of the MOS transistor P4 and the PMOS transistor P5 are connected to each other and the gate and drain of the PMOS transistor P4 are short-circuited, and the gates of the NMOS transistor N8 and the NMOS transistor N9 are connected. A fourth current mirror circuit in which the gate and the drain of the NMOS transistor N8 are short-circuited, and the drain of the PMOS transistor P3 is connected to the drain of the NMOS transistor N8, and the drain of the NMOS transistor N7 is connected to the drain of the PMOS transistor P4. Separately connect each, PM
The drain of the OS transistor P5 and the NMOS transistor N
9 is connected to the oscillation output terminal OUT.

The operation until the oscillation voltage oscillation from the oscillation detection gate 21 is converted and amplified into the drain current fluctuation of the PMOS transistor P3 and the NMOS transistor N7 is the same as that of the fifth embodiment shown in FIG. In FIG. 7, the drain currents are further added to the NMOS transistors N8 and PM
The current is supplied as a drain current of the OS transistor P4, and the NMOS transistor N8, N9 and the PMOS transistor P4, P5 are provided with NM
The signal is amplified and transmitted to the OS transistor N9 and the PMOS transistor P5. PMOS transistor P3 and NMOS
Since the transistor N7 operates exclusively as described in the fifth embodiment, the PMOS transistor P5 and the NMOS transistor N9 which amplify their respective drain currents also operate exclusively, and the oscillation output terminal The voltage amplitude is output to OUT.

In the fifth embodiment shown in FIG.
It is necessary that the amplification factors of the current mirror circuits of the OS transistors P2 and P3 and the NMOS transistors N6 and N7 are almost the same. If the amplification factors are different, the output side PMOS transistor P3 or NMO
A larger current bias is applied to one of the S-transistors N7, and as a result, the output voltage amplitude is biased toward the power supply VCC side or the GND side, and in an extreme case, the amplitude is collapsed and an oscillation output cannot be obtained. Therefore, the mirror ratios, that is, the amplification factors are set to be the same by making the size ratios of the respective MOS transistors of the PMOS transistors P2 and P3 and the NMOS transistors N6 and N7 equal. Since the type of the transistor is different from that of the PMOS and the NMOS, a difference may occur in the amplification factor due to a device characteristic variation or the like. For example, looking at the PMOS transistors P2 and P3 and the NMOS transistors N6 and N7 in FIG. 6, the drain-source voltage of each MOS transistor is different.
Therefore, if there is a difference in the drain current change rate (or Early voltage) with respect to the drain-source voltage in the characteristics of the PMOS transistor and the NMOS transistor, PM
Even if the mirror ratios of the OS transistors P2 and P3 and the NMOS transistors N6 and N7 are set to the same value, a difference occurs in the amplification factor of each current mirror circuit.

On the other hand, in FIG. 7, the output of the current mirror circuit of the PMOS transistors P2 and P3 is NM
With the configuration in which the output of the current mirror circuit of the NMOS transistors N6 and N7 is output via the current mirror circuit of the PMOS transistors P4 and P5 via the current mirror circuit of the OS transistors N8 and N9, the PMOS transistors P2 and Even if the amplification factors of the first stage current mirror circuits of P3 and the NMOS transistors N6 and N7 differ, the next stage current mirror circuit for amplifying the output is constituted by MOS transistors of opposite polarity, so that the first stage current mirror circuit has the opposite polarity. It is possible to compensate for a difference in amplification factor in the current mirror circuit. That is, P
A first current mirror circuit formed by MOS transistors P2 and P3 and a fourth current mirror circuit formed by NMOS transistors N8 and N9.
Current mirror circuit and NMOS transistors N6, N
7, the oscillation current amplifying path formed by each current mirror circuit combination of the second current mirror circuit formed by the PMOS transistor 7 and the third current mirror circuit formed by the PMOS transistors P4 and P5 is constituted by a combination of a PMOS transistor and an NMOS transistor. / NMOS
It is possible to compensate for variations in device characteristics between the two.

According to the present embodiment, it is possible to obtain an oscillation circuit that suppresses fluctuations in oscillation output characteristics due to device characteristics fluctuations in addition to the effects of the fifth embodiment.

The fourth, fifth, and sixth aspects of the present invention described above
The amplifier circuit of the oscillation voltage amplitude by the coupling capacitance and the current mirror circuit in the embodiment of FIG. Since the oscillation can be immediately amplified and output when the oscillation starts, it is needless to say that it has an effect of shortening the oscillation rising time as compared with the related art.

FIG. 8 shows a seventh embodiment of the present invention.

This embodiment relates to an oscillation circuit that can operate even at a low voltage of, for example, about 2 V or less. The difference from the other embodiments of the present invention is that the boosting means 30,
An NMO comprising a level shifter 31 and constituting the short-circuit means 7
That is, the gate of the S transistor N1 is driven by a boosted voltage equal to or higher than the power supply voltage VCC, and the inverting amplifier 1 and the oscillation detection gate 21 are constituted by load MOS type inverters.

In order for the NMOS transistor N1 constituting the short-circuit means 7 to exhibit a sufficient short-circuiting performance, a sufficient potential difference between the drain and source terminal potentials and the gate terminal potential exceeding the threshold voltage Vth is required. . However, under a low voltage, the potential difference is reduced, and in some cases, may fall below the threshold voltage Vth. In such a state, the NMOS transistor N
1 has a high impedance between the drain and the source, thereby greatly increasing the time required for the input / output of the inverting amplifier 1 to be biased to its logical threshold voltage VLT1 during a short-circuit operation. This has a significant effect on shortening the rise time.

On the other hand, as in this embodiment, the boosting means 30
The gate of the NMOS transistor N1 is driven by the boosted output voltage of the NMOS transistor N1.
, A potential difference between the drain and source terminal potentials and the gate terminal potential can be secured.
The short-circuit operation between the input and the output of the inverting amplifier 1 can be performed in a state where the impedance between the drain and the source of the MOS transistor N1 is kept low.

Also, an inverting amplifier 1 and an oscillation detection gate 2
1 is a PMOS transistor P6 and an NMOS transistor N10, respectively, and a PMOS transistor P7 and an NM
The load MOS type inverter is composed of the OS transistor N11. Since the load MOS type inverter has a gain in a voltage range whose input voltage level is equal to or higher than the threshold voltage Vth of the NMOS transistor,
The function as an inverting amplifier can be ensured even under a low voltage of about 2 V or less. In FIG. 8, these load MOS type inverters are connected to a PMOS transistor P6.
And the control terminal C1 commonly connected to each gate of the PMOS transistor P7 is activated by setting it to a low level.

In FIG. 8, the input of the oscillation detection gate 21 is connected to the output of the inverting amplifier 1 via the coupling capacitor 8 as in the other embodiments, and the feedback resistor 9 is provided between the input and output. However, the input / output short circuit means 10 is omitted. This is because, as described in the description of the third embodiment of the present invention, by setting the feedback resistor 9 to a relatively low resistance value, the input / output short-circuit means 10 on the oscillation detection gate 21 side is not necessarily required. Not limited. Of course, the short-circuit means 10 may be provided.
Similarly, in order to secure short-circuit performance during low-voltage operation, booster 30
Control drive by the boosted output voltage is required.

In FIG. 8, an output circuit 20 provided between the oscillation detection gate 21 and the oscillation output terminal OUT amplifies or waveform-shapes the output amplitude of the oscillation detection gate 21 and sends out the oscillation circuit output. This is constituted by the inverters G5 and G6 in FIG. 1 or the like, or the amplification stage configuration by the coupling capacitance and the current mirror circuit in FIG. 4 and thereafter. Further, in FIG. 8, the oscillation detection gate 21 is provided, but this is not an essential component, and a configuration in which the output circuit 20 is directly connected to the output of the inverting amplifier 1 is also possible. These may be appropriately designed according to the target oscillation circuit specification.

According to the present embodiment, the short circuit performance of the short circuit means 7 and the function of the inverting amplifier 1 can be ensured even at a low voltage, so that an oscillating circuit having a reduced oscillation rise time even at a low voltage can be obtained. .

FIG. 9 shows an eighth embodiment of the present invention.

FIG. 9 shows a configuration in which the inverting amplifier 1 and the oscillation detection gate 21 in the seventh embodiment of FIG. 8 are configured as a constant current load type inverter. That is, in FIG.
The inverting amplifier 1 and the oscillation detection gate 21 are connected to the PM as in FIG.
OS transistor P6 and NMOS transistor N10, and PMOS transistor P7 and NMOS transistor N1
1 but the PMOS transistor P
6 and the gate of the PMOS transistor P7 are commonly connected to the gate of the PMOS transistor P8 whose gate and drain are short-circuited.
The S transistors P6 and P7 form a current mirror circuit. The drain of the PMOS transistor P8 is
Gate to reference voltage source Vref, source to GND
The drain of a PMOS transistor P9 whose gate is connected to the control terminal C1 is connected to the drain of an NMOS transistor N12 connected to the control terminal C1. Where PMOS
The transistor P9 is turned on when the control terminal C1 is at the low level.
N is provided to bias the gates of the PMOS transistors P6, P7, and P8 to the power supply VCC voltage and stop the operations of the inverting amplifier 1 and the oscillation detection gate 21. At this time, for example, the reference voltage source Vref is also low.
(GND) level, the PMOS transistor P
Although a through current between the transistor 9 and the NMOS transistor N12 can be prevented, a detailed description is omitted because it does not constitute a feature of the present embodiment.

In FIG. 9, the NMOS transistor N
12 is a reference current source, and the NMOS transistor N12
The mirror ratio times the current flowing between the inverter transistor 1 and the PMOS transistor P8 is the bias current of the inverting amplifier 1 and the oscillation detection gate 21. That is, the NMOS transistors N10 and N11 forming the inverting amplifier 1 and the oscillation detection gate 21
Is defined by the NMOS transistor N12.

On the other hand, in the embodiment shown in FIG. 8, the load currents of the NMOS transistors N10 and N11 are defined by the PMOS transistors P6 and P7, respectively. There is a possibility that the gain as a result will vary greatly.

In this embodiment shown in FIG. 9, the active device on the signal receiving side as described above, that is, the NMOS shown in FIG.
Since the load current is defined by the same type of devices as the transistors N10 and N11, that is, the NMOS transistor N12, the effect of device characteristics variation between the PMOS transistor and the NMOS transistor can be suppressed, and the gain can be stabilized. That is, even if the device characteristics of the PMOS transistors P6, P7, and P8 forming the current mirror in FIG. 9 vary, the mirror ratio does not change as long as there is no relative variation between the PMOS transistors. Since there is no change in current, there is no change in gain.

Keeping the gain of the inverting amplifier 1 stable is important for forming a positive feedback loop with the oscillator 5 at the time of starting the oscillation and for enlarging the oscillation amplitude thereafter, leading to stabilization of the oscillation rising characteristic.

According to the present embodiment, since the gain of the inverting amplifier can be stabilized with respect to device characteristic variations, in addition to the effects of the seventh embodiment, there is a stable oscillation rising characteristic with respect to device variations. An oscillation circuit that has been obtained can be obtained.

FIG. 10 shows a ninth embodiment of the present invention.

In the other embodiments described above, the input / output terminal potential of the inverting amplifier 1 is biased to its logical threshold voltage VLT1 by the short-circuit means 7 at the time of starting the oscillation. A positive feedback loop with the element 5 is formed at an early stage to accelerate the start of oscillation. However, when the power supply VCC is in a low voltage range, there is a problem that the impedance of the short-circuit means 7 increases as described in the seventh embodiment, and the boosting means 30 and the like are required to prevent this. In order to generate a boosted output voltage from the boosting means 30, a clock pulse source for operating the boosting means 30 is usually required. In a semiconductor integrated circuit such as a microprocessor incorporating the oscillation circuit, a boosted output voltage is required at the time of starting the oscillation circuit serving as a system clock source. For example, a self-propelled oscillation circuit such as a ring oscillator, Alternatively, a pulse source such as an external clock for operating the booster 30 in advance must be separately provided.

The present embodiment relates to an oscillation circuit capable of avoiding an increase in circuit elements as described above. Hereinafter, this embodiment will be described.

In FIG. 10, the oscillator 5 and the feedback resistor 4 are connected in parallel between the terminal T1 and the terminal T2 as in the other embodiments, and the capacitor 6 is connected between the terminal T1 and the terminal T2 and GND.
1, 62 are connected. The inverting amplifier 1 is composed of a load MOS type inverter including a PMOS transistor P6 and an NMOS transistor N10, as in the seventh embodiment of FIG. 8, and the gate of the NMOS transistor N10 is controlled at the terminal T1 and the gate of the PMOS transistor P6 is controlled. An output, that is, a PMOS transistor P6 and N
The drain of the MOS transistor N10 is connected to the terminal T2 via the resistor 3. The oscillation detection gate 21 is also constituted by a load MOS type inverter comprising a PMOS transistor P7 and an NMOS transistor N11 as in the seventh embodiment of FIG. 8, and the gate of the NMOS transistor N11 is connected to the inverting amplifier 1 via the coupling capacitor 8. To the output, the gate of the PMOS transistor P7 is connected to the control terminal C1. The output, that is, the drain of the PMOS transistor P7 and the drain of the NMOS transistor N11 are connected to the oscillation output terminal OUT via the output circuit 20, and the feedback resistor 9 is connected between the input, that is, the gate and the output of the NMOS transistor N11. ing. The configuration of the output circuit 20 is as described in the description of the seventh embodiment. Further, a switching element 19 composed of a PMOS transistor P10 having a drain connected to the input of the inverting amplifier 1, ie, the gate of the NMOS transistor N10, and a detection circuit 32 for detecting the output potential of the inverting amplifier 1 and controlling the switching element 19, An exciting current supply means 18 comprising a PMOS transistor P1 having a gate connected to the control terminal C3, a gate to the control terminal C5, a drain to the output of the inverting amplifier 1,
And an NMOS transistor N13 whose source is connected to GND. The detection circuit 32 has its output connected to the gate of the PMOS transistor P10 in the switching element 19, and has one input connected to the NAND gate G10 having one input connected to the control terminal C6 and the output connected to the other input of the NAND gate G10. A NAND gate G8 having one input connected to the control terminal C6, an output connected to the other input of the NAND gate G8, one input connected to the output of the NAND gate G8, and the other input connected to an inverting amplifier. 1 connected to the output of each NAND
And a gate G9.

Hereinafter, the operation of this embodiment will be described.

First, when the oscillation circuit is stopped, the control terminals C1, C3, and C5 are biased to a high level, and C6 is biased to a low level. At this time, since the PMOS transistors P6 and P7 are in the OFF state, the inverting amplifier 1 and the oscillation detection gate 21 do not function. Also PMO
S transistor P1 is OFF, NMOS transistor N
Since the terminal 13 is in the ON state, the terminal T2 side potential is at the GND level. Further, since the output of the NAND gate G10 becomes High, the PMOS transistor P10 is in the OFF state, so that the potential on the terminal T1 side is also at the GND level due to the feedback resistor 4.

Next, when the oscillation circuit is started, the control terminal C5 is set to low and the NMOS transistor N13 is turned off.
At the same time, a low-level one-shot pulse is applied to the control terminal C3, and the PMOS transistor P1 is turned ON only for a predetermined period to supply an exciting current to the oscillator 5.
As a result, the potential at the terminal T2 rises sharply toward the power supply VCC potential, but the potential at the terminal T1 begins to rise slowly because the feedback resistor 4 has a high resistance. After that, the control terminal C1 is set to Low to activate the inverting amplifier 1 and the oscillation detection gate 21, but at this time, the potential on the terminal T1 side is near the GND level, and the inverting amplifier 1 cannot yet function.

At this time, that is, when the control terminal C6 is set to High immediately after activating the inverting amplifier 1, the output of the NAND gate G10 becomes Low and the PMOS transistor P10
Turns on to accelerate the potential rise on the terminal T1 side. Where N
The reason that the output of the AND gate G10 is inverted to Low is that the output of the NAND gate G8 becomes Hi immediately before the control terminal C6 is set to High.
gh, the potential of the terminal T2 is high, and the output of the NAND gate G9 is low.
gh, NA becomes low by the low output of the NAND gate G9.
The output of the ND gate G8 keeps High, so that both inputs of the NAND gate G10 become High and the output of the NAND gate G10 is inverted to Low. If the bias of the control terminal C6 is maintained at the high level as it is,
This state is maintained unless the potential of the terminal T2 is inverted to Low.

When the potential at the terminal T1 rises and reaches the logical threshold voltage VLT1 of the inverting amplifier 1 by turning on the PMOS transistor P10, ie, the switching element 19, the output of the inverting amplifier 1, that is, the potential at the terminal T2, becomes High. Start flipping from level to low. In response to the inversion of the potential at the terminal T2 side to Low, the output of the NAND gate G9 becomes High, whereby both inputs of the NAND gate G8 become High, and the output of the NAND gate G8 becomes Low.
Therefore, the output of the NAND gate G10 returns to High and PM
The OS transistor P10 turns off. At this point, the potential rise on the terminal T1 side stops, and as a result, the potential on the terminal T1 side is biased near the logical threshold voltage VLT1 of the inverting amplifier 1. On the terminal T2 side, the potential can temporarily fluctuate to or near the GND level, but since the input potential of the terminal T1, ie, the inverting amplifier 1, is near VLT1, the output of the inverting amplifier 1, ie, the potential on the terminal T2 side, will soon. It is stabilized near VLT1. Since the input potential of the inverting amplifier 1 is near VLT1 from the time when the switching element 19 is turned off, the gain of the inverting amplifier 1 is ensured regardless of the potential fluctuation on the terminal T2 side, and oscillation can be started. When the output of the inverting amplifier 1 is received via the coupling capacitor 8 as shown in FIG. 10, a minute oscillation oscillation component of the inverting amplifier 1 is extracted regardless of the potential fluctuation of the output, and this is output to the oscillation detection gate 21 and the output. Circuit 20
Amplification and waveform shaping can be performed by, for example, transmission to the output terminal OUT.

Even if the potential at the terminal T2, which has been once inverted to the low level due to the turning on of the switching element 19, becomes high again due to the expansion of the oscillation amplitude or the like, the control terminal C6 remains high during the operation of the oscillation circuit. By setting the level, the output of the NAND gates G9 and G10 is fixed to High because the NAND gate G8 maintains the Low output, and the OFF state of the switching element 19 is maintained.

Since the detection circuit 32 only needs to be able to detect the output inversion of the inverting amplifier 1, a normal CMOS gate configuration can be applied to a low-voltage operation.

In FIG. 10, the inverting amplifier 1 and the oscillation detection gate 21 are configured as the load MOS type inverter in the same manner as in the seventh embodiment in consideration of the low voltage operation. However, the invention is not limited to this. No, for example, the third in FIG.
The same operation can be obtained by the gate having the CMOS configuration as shown in the embodiment. However, regarding the power supply VCC voltage, the operation lower limit value differs. Excitation current supply means 1
8 and the NMOS transistor N13 are omitted as long as they have a sufficient excitation current supply capacity when the inverting amplifier 1 is activated, and have a gate configuration capable of fixing the potentials of the terminals T1 and T2 in the stopped state. Is also good. Also, the configuration of the oscillation detection gate 21 and the output circuit 20 may be appropriately designed as described in the seventh embodiment.

In FIG. 10, when the oscillation is stopped, the terminals T1 and T2 are both fixed to the GND level when the inverting amplifier 1 and the oscillation detection gate 21 are of the PMOS load type.
Although a function of pulling up one potential is provided, the present invention is not limited to this. For example, the inverting amplifier 1 and the oscillation detection gate 21 may be of an NMOS load type (in this case, the terminal T1 is connected to the gate of the PMOS transistor). If the terminals T1 and T2 are both fixed to the power supply VCC potential side when the oscillation is stopped, the exciting current supply means 18 is also provided between the terminal T2 and GND, and the terminal T2 side is biased to the GND level. Excitation of the oscillator 5 will be performed. In this case, since the potential of the terminal T1 changes from the High level side, the switching element 19 has a function of pulling down the potential of the terminal T1. Specifically, instead of the PMOS transistor P10 in FIG.
If an NMOS transistor is provided between the switching element D and the switching element 19, the switching element 19 having a pull-down function can be easily configured. Further, in this case, since the switching element 19 is turned off by detecting the output inversion of the inverting amplifier 1 to the high level side, it is necessary that the detection circuit 32 has a configuration corresponding thereto. One example is a NAND gate G
8, G9 and G10 may all be replaced with NOR gates, and conversely to FIG. 10, the control terminal C6 may be set to Low to start up.

According to the present embodiment, the input potential of the inverting amplifier 1 can be biased to the vicinity of its logical threshold voltage VLT1 at the start of oscillation without using the input / output short circuit means 7 of the inverting amplifier 1. As in the case of the seventh embodiment, an oscillation circuit having a reduced oscillation rise time can be obtained, and low-voltage operation can be dealt with without adding circuit elements such as the booster 30 as in the seventh and eighth embodiments. In addition, an oscillation circuit advantageous for integration can be obtained with a relatively small circuit scale.

[0106]

According to the present invention, a positive feedback loop between the inverting amplifier 1 and the oscillator 5 is formed at an early stage to accelerate the start of oscillation.
Further, it is possible to obtain an oscillation circuit in which the minute oscillation output from the inverting amplifier 1 is amplified and waveform-shaped, and the oscillation rise time from the start of oscillation until an available oscillation output is obtained is greatly reduced.

Further, according to the present invention, it is possible to obtain an oscillation circuit in which the current consumption of the output buffer circuit for amplifying and shaping the minute oscillation output from the inverting amplifier 1 is reduced.

Further, according to the present invention, by using a current mirror circuit for amplifying the oscillation amplitude, it is possible to obtain an oscillation circuit capable of shortening the oscillation rise time even under a low voltage and maintaining good oscillation output characteristics. Can be.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration of a third embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration of a fourth embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of a fourth embodiment of the present invention.

FIG. 6 is a circuit diagram showing a configuration of a fifth embodiment of the present invention.

FIG. 7 is a circuit diagram showing a configuration of a sixth embodiment of the present invention.

FIG. 8 is a circuit diagram showing a configuration of a seventh embodiment of the present invention.

FIG. 9 is a circuit diagram showing a configuration of an eighth embodiment of the present invention.

FIG. 10 is a circuit diagram showing a configuration of a ninth embodiment of the present invention.

FIG. 11 is a circuit diagram showing a conventional configuration.

[Description of Signs] 1 ... inverting amplifier, 2 ... output buffer circuit, 3 ... resistor,
4, 9 feedback resistor, 5 oscillator, 7, 10 short circuit means,
8, 11, 15 coupling capacity, 12, 13 bias means, 14, 16, 17 current source, 18 exciting current supply means, 19 switching element, 20 output circuit,
Reference numeral 21: oscillation detection gate, 22: buffer circuit, 30: boosting means, 31: level shifter, 32: detection circuit, 61,
62: capacity, C1, C2, C3, C4, C5, C6: control terminals, P1, P2, P3, P4, P5, P6, P7,
P8, P9, P10 ... PMOS transistors, N1, N
2, N3, N4, N5, N6, N7, N8, N9, N1
0, N11, N12, N13 ... NMOS transistors,
OUT: oscillation output terminal, VCC: power supply.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Tadashi Sanbe 3-1-1, Sachimachi, Hitachi-shi, Ibaraki Pref. Hitachi, Ltd. Hitachi Plant (72) Inventor Katsunori Koike 3-2-2, Sachimachi, Hitachi-shi, Ibaraki No. 1 Hitachi Engineering Co., Ltd. (72) Inventor Masahiko Numata 3-10-2 Bentencho, Hitachi City, Ibaraki Prefecture Within Hitachi Haramachi Electronics Co., Ltd. (72) Inventor Satoshi Sugai Sachimachi, Hitachi City, Ibaraki Prefecture Hitachi 1-1, Hitachi Works, Ltd. (72) Inventor Hiroyuki Kida 3-1-1, Sakaimachi, Hitachi, Ibaraki Prefecture, Hitachi Works, Hitachi Works

Claims (14)

[Claims] 1. An oscillation circuit for oscillating by forming a positive feedback loop of an inverting amplifier and an oscillator connected in parallel between input and output terminals of the inverting amplifier, wherein voltage bias means is provided at an input terminal of the inverting amplifier. When the oscillation is started, a potential difference is generated between the input and output terminals of the inverting amplifier to excite the oscillator, and then the voltage bias means is operated to apply a predetermined potential to the input terminal of the inverting amplifier to start the oscillation. Oscillation circuit. 2. An oscillating circuit for performing an oscillating operation by forming a positive feedback loop of an inverting amplifier and an oscillator connected in parallel between input and output terminals of the inverting amplifier, wherein a voltage bias means connected to an input terminal of the inverting amplifier. And an exciting current supply means connected to at least one of the input terminal and the output terminal of the inverting amplifier, and when the oscillation is started, the exciting current supply means is operated for a predetermined period to supply the exciting current to the oscillator. An oscillation circuit which stops the operation of the exciting current supply means, activates the voltage bias means, applies a predetermined potential to the input terminal of the inverting amplifier, and starts oscillation. 3. An oscillation circuit which forms a positive feedback loop of an inverting amplifier and an oscillator connected in parallel between input and output terminals of the inverting amplifier to perform an oscillating operation, wherein a voltage bias means connected to an input terminal of the inverting amplifier. And an oscillation detection gate connected to the output terminal of the inverting amplifier and having the same gate configuration as that of the inverting amplifier. An oscillating circuit for operating the means to apply a predetermined potential to an input terminal of the inverting amplifier, start oscillation, and extract an oscillation output via an oscillation detection gate. 4. An oscillation circuit for performing an oscillation operation by forming a positive feedback loop of an inverting amplifier and an oscillator connected in parallel between input and output terminals of the inverting amplifier, wherein a voltage bias means connected to an input terminal of the inverting amplifier. A coupling capacitance; and an oscillation detection gate having an input terminal connected to the output terminal of the inverting amplifier via the coupling capacitance, and a feedback resistor connected in parallel between the input and output terminals. After a potential difference is generated between the output terminals to excite the oscillator, the voltage bias means is operated to apply a predetermined potential to the input terminal of the inverting amplifier, to start oscillation, and to take out the oscillation output through the oscillation detection gate. An oscillation circuit characterized by the above. 5. The voltage bias means is constituted by short-circuit means connected in parallel between the input and output terminals of the inverting amplifier and short-circuiting between the input and output terminals of the inverting amplifier only for a predetermined period by a one-shot control pulse. The oscillation circuit according to claim 1, 2, 3, or 4. 6. The oscillation circuit according to claim 5, wherein the short-circuiting means is driven by a boosting voltage at least equal to a power supply voltage of the inverting amplifier at the time of short-circuit operation using the boosting means. 7. A switching element connected to an input terminal of the inverting amplifier, for switching the input terminal potential immediately after the excitation of the oscillator in a direction of a predetermined potential, and an inverting amplifier by the operation of the switching element. 5. The oscillation circuit according to claim 1, further comprising: a detection circuit that controls the switching element to be turned off in response to the output potential fluctuation. . 8. A first control terminal, a second control terminal, a third control terminal, an inverting amplifier activated by an input signal to the first control terminal, and a second control terminal. First short-circuit means which is on / off controlled by an input signal of the inverting amplifier and connected in parallel between the input and output terminals of the inverting amplifier, a first feedback resistor and an oscillator respectively connected in parallel between the input and output terminals of the inverting amplifier, A first and a second capacitor connected between both ends of the inverter and a reference potential, an oscillation detection gate connected to the output terminal of the inverting amplifier via a coupling capacitor, and a parallel connection between the input and output terminals of the oscillation detection gate A second feedback resistor, and second short-circuiting means which is on / off controlled by an input signal to a third control terminal and is connected between the input and output terminals of the oscillation detection gate;
A one-shot pulse signal is input to the second control terminal with a predetermined delay with respect to the signal input of the first control terminal, and the off-timing of the second short-circuiting means is the off-timing of the first short-circuiting means. Thereafter, a one-shot pulse signal having a pulse width not less than the one-shot pulse width of the second control terminal is input to the third control terminal to start oscillation, and the oscillation output is output via the oscillation detection gate. An oscillation circuit characterized by taking out. 9. The oscillation circuit according to claim 8, wherein the first short-circuiting means and the second short-circuiting means are turned on by using a boosting means with a boosted voltage at least equal to a power supply voltage of the inverting amplifier. . 10. An oscillating circuit for performing an oscillating operation by forming a positive feedback loop of an inverting amplifier and an oscillator connected in parallel between input and output terminals of the inverting amplifier, wherein the source is connected to a first reference potential. The first transistor of one conductivity type and the gate of the second transistor of the first conductivity type whose source is connected to the first reference potential are connected to each other, and the gate and drain of the first transistor are short-circuited. A current mirror circuit having an input terminal and a drain of a second transistor as an output terminal; a first current bias means connected between an input terminal of the current mirror circuit and a second reference potential; A second current bias means connected between an output terminal of the mirror circuit and a second reference potential; and a coupling capacitor, for coupling the oscillation voltage oscillation originating from the output of the inverting amplifier. An oscillation circuit which inputs an input terminal of the current mirror circuit via a capacitor and takes out an oscillation output from an output terminal of the current mirror circuit. 11. An oscillating circuit which performs a oscillating operation by forming a positive feedback loop of an inverting amplifier and an oscillator connected in parallel between input and output terminals of the inverting amplifier, wherein the source is connected to a first reference potential. The first transistor of one conductivity type and the gate of the second transistor of the first conductivity type whose source is connected to the first reference potential are connected to each other, and the gate and drain of the first transistor are short-circuited. A first current mirror circuit having a drain as an input terminal and a second transistor of a second conductivity type having a source connected to a second reference potential; The fourth transistor of the second conductivity type connected to the reference potential of the second transistor is connected to each other, and the gate and drain of the third transistor are short-circuited to form an input terminal; A second current mirror circuit having a drain as an output terminal; first current bias means connected between an input terminal of the first current mirror circuit and a second reference potential; A second current bias means connected between the input terminal and the first reference potential; and a second current bias means connected in series between the input terminal of the first current mirror circuit and the input terminal of the second current mirror circuit. And a common connection point of the first and second coupling capacitors as an input terminal, and an output terminal of each of the first and second current mirror circuits connected in common. An oscillation circuit, comprising: an amplification circuit serving as an output terminal; inputting an oscillation voltage oscillation from the output of the inverting amplifier to an input terminal of the amplification circuit, and extracting an oscillation output from an output terminal of the amplification circuit. 12. An oscillating circuit which performs a oscillating operation by forming a positive feedback loop of an inverting amplifier and an oscillator connected in parallel between input and output terminals of the inverting amplifier, wherein the source is connected to a first reference potential. The first transistor of one conductivity type and the gate of the second transistor of the first conductivity type whose source is connected to the first reference potential are connected to each other, and the gate and drain of the first transistor are short-circuited. A first current mirror circuit having a drain as an input terminal and a second transistor of a second conductivity type having a source connected to a second reference potential; The fourth transistor of the second conductivity type connected to the reference potential of the second transistor is connected to each other, and the gate and drain of the third transistor are short-circuited to form an input terminal; A second current mirror circuit having a drain as an output terminal; a fifth transistor of a first conductivity type having a source connected to a first reference potential; and a first conductivity type having a source connected to the first reference potential. A third current mirror circuit in which the gates of the sixth transistor are connected to each other, the gate and drain of the fifth transistor are short-circuited and used as an input terminal, and the drain of the sixth transistor is used as an output terminal; Are connected to the gate of a seventh transistor of the second conductivity type, the source of which is connected to the second reference potential, and the eighth transistor of the second conductivity type, the source of which is also connected to the second reference potential; A fourth current mirror circuit in which the gate and the drain of the transistor are short-circuited and used as an input terminal, and the drain of the eighth transistor is an output terminal; and a first current mirror circuit. Current bias means connected between the input terminal of the second current mirror circuit and the second reference potential, and second current bias means connected between the input terminal of the second current mirror circuit and the first reference potential And first and second coupling capacitors provided in series between an input terminal of the first current mirror circuit and an input terminal of the second current mirror circuit. , The output terminal of the first current mirror circuit is connected to the input terminal of the fourth current mirror circuit, and the output terminal of the second current mirror circuit is connected to the third current mirror circuit. And an output circuit connected to the output terminals of the third and fourth current mirror circuits in common, and an amplifier circuit serving as an output terminal is provided. Circuit input terminal An oscillation output from the output terminal of the amplifier circuit. 13. The inverting amplifier further comprises voltage bias means for biasing an input terminal of the inverting amplifier to a predetermined potential after exciting the oscillator at the time of starting oscillation. 13. The oscillation circuit according to claim 12. 14. An inverting amplifier, comprising: a first MOS transistor of a first conductivity type; a second MOS transistor of a second conductivity type having a drain connected to the drain of the first MOS transistor; And the gate is connected to the second M
A third of the second conductivity type which is connected to the gate of the OS transistor to form a current mirror with the second MOS transistor.
A fourth MOS transistor of a first conductivity type, the first MOS transistor being connected to a gate of a reference voltage source and the drain being connected to the drain of a third MOS transistor, respectively.
The gate of the transistor is used as an input terminal and the drain is used as an output terminal, according to claim 1, claim 2, claim 3, claim 4, claim 8, claim 10, claim 11, or claim 12. The oscillation circuit according to claim 1.