JP5048355B2 - Oscillator circuit - Google Patents

Description

  The present invention relates to a Colpitts type oscillation circuit including an LC resonance circuit.

  The Colpitts type oscillation circuit is configured as shown in FIG. INV1 and INV2 are CMOS inverters connected to the power supply VDD and the ground GND, X1 is a crystal resonator, Rf is a feedback resistor, and Cg and Cd are resonance capacitors.

In this oscillation circuit, the input side and the output side of the CMOS inverter INV1 are initially at the same voltage by the feedback resistor Rf. Thereafter, when the signal on the input side of the CMOS inverter INV1 is inverted and amplified and appears at the node N1, The voltage fluctuation at the node N1 charges or discharges the capacitor Cd, and this operation causes the inductance component at the natural frequency of the crystal resonator X1 and the parallel resonance circuit of the capacitors Cg and Cd to resonate. Oscillation occurs at the natural frequency of X1. A crystal oscillation circuit having such a configuration is described in Patent Document 1.
Japanese Utility Model Publication No. 03-098513

  In the oscillation circuit as described above, the feedback bias voltage of the CMOS inverter INV1 is set to a voltage of VDD / 2 in order to make the output symmetry (duty ratio) 50%. Further, the threshold voltage of the CMOS inverter INV2 as a buffer in the next stage is also set to a voltage of VDD / 2 in order to make the output symmetry 50%. In this case, when the power supply voltage VDD is turned on, self-excited oscillation occurs according to the following procedures (a) to (c). FIG. 6 shows a waveform diagram.

(a) Due to power supply noise when the power supply voltage VDD is turned on, noise enters the power supply voltage VDD of the CMOS inverter INV1, and the voltage (output voltage) of the node N1 is fluctuated.
(b) When the voltage at the node N1 fluctuates, the output of the CMOS inverter INV2 is inverted. At this time, a large through current flows during the operation of the CMOS inverter INV2, resulting in further noise on the power supply voltage VDD.
(c) By repeating the operations (a) and (b) above, self-excited oscillation is caused.

  As described above, self-excited oscillation having a frequency different from the natural frequency of the crystal unit X1 is caused, and thus there is a problem of causing malfunction in a device using the oscillation circuit.

  Therefore, the feedback bias voltage of the CMOS inverter INV1 is set to VDD / 2 by adjusting the size ratio of the two MOS transistors constituting the CMOS inverter INV1 or adjusting the threshold voltage of the CMOS inverter INV2 in the next stage. The voltage is made higher (or lower) than the noise level and a large voltage difference is made between the feedback bias voltage and the threshold voltage of the CMOS inverter INV2.

  Thus, even when the feedback bias potential (output voltage) of the CMOS inverter INV1 is fluctuated by power supply noise when the power supply voltage VDD is turned on, the output voltage (voltage of the node N1) and the threshold voltage of the next-stage CMOS inverter INV2 A sufficient voltage difference is ensured between the two and the output of the CMOS inverter INV2 does not change (invert), and self-excited oscillation is not caused. At this time, when the threshold voltage is VDD / 2, the output of the CMOS inverter INV2 is set to “L” (= GND) and low if the feedback bias voltage of the CMOS inverter INV1 is set higher than VDD / 2. If it is, it becomes “H” (= VDD).

  However, the above method has a problem in that the output symmetry is deteriorated due to the deviation of the feedback bias voltage of the CMOS inverter INV1.

  In order to solve the above problems, an object of the present invention is to provide an oscillation circuit in which self-excited oscillation does not occur and output symmetry can be secured.

In order to achieve the above object, an invention according to claim 1 is directed to an inverter to which a first power source and a second power source are connected, and a second power source connected between the input side of the inverter and the second power source. 1 capacitor, a second capacitor connected between the output side of the inverter and the second power supply, a feedback resistor and a vibrator connected in parallel between the input and output of the inverter, and An oscillation circuit body in which a feedback bias voltage on the output side of the inverter is set to an intermediate voltage between the voltage of the first power supply and the voltage of the second power supply, and an oscillation output signal oscillated in the oscillation circuit body is detected. An oscillation detection circuit, and when the oscillation detection circuit does not detect the oscillation output signal, pulls up the output voltage of the inverter to a voltage higher than the intermediate voltage, and the oscillation detection circuit Upon detection of a serial oscillating output signal, in the oscillation circuit provided with a voltage application circuit for releasing the pull-up, the oscillation detection circuit, the integral of the first time constant for integrating the oscillation signal outputted from the oscillation circuit body A discharge circuit having a second time constant for discharging the electric charge integrated in the integration circuit, wherein the second time constant is set larger than the first time constant and reaches a predetermined value. The integration voltage of the integration circuit is a signal obtained by detecting the oscillation output signal .
According to a second aspect of the present invention, there is provided an inverter connected to the first power source and the second power source, a first capacitor connected between the input side of the inverter and the second power source, and an output of the inverter A feedback capacitor and a feedback resistor and a vibrator connected in parallel between the input and output of the inverter, and a feedback bias voltage on the output side of the inverter Comprises an oscillation circuit body that is set to an intermediate voltage between the voltage of the first power supply and the voltage of the second power supply, and an oscillation detection circuit that detects an oscillation output signal oscillated by the oscillation circuit body, In the oscillation circuit body, when the oscillation detection circuit does not detect the oscillation output signal, the output voltage of the inverter is pulled down to a voltage lower than the intermediate voltage, and the oscillation detection circuit detects the oscillation output signal. Can, in the oscillation circuit provided with a voltage application circuit for releasing the pull, the oscillation detection circuit includes an integration circuit of the first time constant for integrating the oscillation signal outputted from the oscillation circuit body, integral to the integrating circuit A discharge circuit having a second time constant for discharging the generated charge, wherein the second time constant is set to be larger than the first time constant, and the integration voltage of the integration circuit that has reached a predetermined value The oscillation output signal is a detected signal .
According to a third aspect of the present invention, in the oscillation circuit according to the first or second aspect, the voltage application circuit is a switch element that is turned on when the oscillation detection circuit does not detect the oscillation output signal and is turned off when the oscillation output signal is detected. Oh, wherein the Rukoto.
The invention according to claim 4 is the oscillation circuit according to any one of claims 1 to 3,
When the oscillation detecting circuit does not detect the oscillation output signal, characterized by Rukoto an output control circuit for prohibiting the output of the output signal of the oscillating circuit body.
According to a fifth aspect of the present invention, in the oscillation circuit according to the fourth aspect, when the oscillation detection circuit detects the oscillation output signal, the output control circuit outputs an output signal of the oscillation circuit body after a predetermined time delay. and features that you release the output prohibition.

  According to the present invention, by pulling up or pulling down the feedback bias voltage of the inverter at the time of power-on when the oscillation output signal is not output, a predetermined voltage is generated between the output voltage of the inverter and the threshold voltage of the next inverter. Since there is a difference, even if the output voltage of the inverter fluctuates due to the influence of minute power supply noise when the power is turned on, there is no operation that crosses the threshold voltage of the next inverter, and self-excitation Does not cause oscillation. Further, since the pull-up or pull-down of the feedback bias voltage described above is canceled during oscillation in normal operation, an oscillation waveform with 50% output symmetry can be obtained. Also, by providing an output control circuit, only a stable oscillation waveform with 50% output symmetry can be output to the outside.

<First embodiment>
FIG. 1 is a circuit diagram showing a configuration of an oscillation circuit according to a first embodiment of the present invention, and FIG. Reference numeral 1A denotes an oscillation circuit body. In addition to the CMOS inverters INV1 and INV2, the crystal oscillator X1, the feedback resistor Rf, and the capacitors Cg and Cd described in FIG. It has a PMOS transistor MP1 connected to the power supply VDD and having a gate connected to the input side of the CMOS inverter INV1, and a PMOS transistor MP2 having a source connected to the drain of the transistor MP1 and a drain connected to the node N1. The feedback bias voltage of the CMOS inverter INV1 is set to VDD / 2 according to the size ratio of the transistors constituting the CMOS inverter INV1. The transistors MP1 and MP2 constitute a voltage application circuit. The CMOS inverters INV1, 2, and 3 are connected to VDD as a positive power supply and GND as ground, but the illustration is omitted here.

  Reference numeral 2 denotes an oscillation detection circuit, a resistor R1 having one end connected to the output side of the CMOS inverter INV3, a capacitor C1 connected to the other end of the resistor R1 and the ground GND, and a resistor connected in parallel to the capacitor C1. It consists of R2. A node N3, which is a common connection point between the capacitor C1 and the resistors R1 and R2, is connected to the gate of the transistor MP2. The capacitor C1 and the resistor R1 constitute an integrating circuit, the capacitor C1 and the resistor R2 constitute a discharging circuit, and the latter time constant is set larger than the former time constant.

  Reference numeral 3 denotes an output control circuit comprising a delay circuit DL1 and an AND circuit AND1. One input side of the AND circuit AND1 is connected to a node N2 which is an output of the CMOS inverter INV2, and the other input side is connected to the delay circuit DL1. The oscillation detection circuit 2 is connected to the node N3.

  Immediately after the power is turned on, the charge of the capacitor C1 is discharged by the resistor R2, and the node N3 is “L” (= GND). For this reason, the transistor MP2 to which the voltage of the node N3 is applied to the gate is turned on.

  Therefore, when the power is turned on, the transistor MP1 is connected in parallel to the PMOS transistor (not shown) of the CMOS inverter INV1, so that the voltage at the node N1 is pulled up to the supplied power supply voltage VDD side, and the feedback bias voltage Is set to a voltage higher than VDD / 2. This high voltage becomes higher than the threshold voltage of the CMOS inverter INV2, and even if the voltage at the node N1 fluctuates due to minute power supply noise at the time of power-on, the voltage does not drop below the threshold voltage of the CMOS inverter INV2. The output voltage of INV2 does not change. That is, self-excited oscillation does not occur. Further, the output of the AND circuit AND1 connected via the delay circuit DL1 connected to the node N3 which is “L” is fixed to “L”, and the output voltage of the output terminal OUT is in the oscillation output stop state. It becomes.

  The delay circuit DL1 having the above configuration has a known and well-known configuration. A specific configuration example will be described with reference to FIG. In the configuration example shown in FIG. 4, 2N stages of CMOS inverters INV are connected in series according to the required delay time. N is an integer represented by 1, 2, 3,.

  When the parallel resonance circuit including the inductance component of the crystal resonator X1 and the capacitors Cg and Cd resonates and crystal oscillation starts, the CMOS inverter INV1 in which the feedback bias voltage is raised to a voltage higher than VDD / 2 starts to operate. When the output voltage of the CMOS inverter INV1 is inverted by the CMOS inverter INV2, the waveform becomes a waveform having a long “H” time. The waveform of the output signal of the CMOS inverter INV3 is the same, and this output signal starts to be charged into the capacitor C1 via the resistor R1.

  When the voltage of the capacitor C1 (node N3) is charged to a predetermined value, the transistor MP2 is turned off, the pull-up of the node N1 is released, and the feedback bias voltage returns to the voltage of VDD / 2. As a result, the output symmetry of the waveform of the oscillation output (node N2) of the CMOS inverter INV2 is 50%.

  At this time, the “H” voltage of the node N3 is input to one input side of the AND circuit AND1 after receiving a predetermined delay in the delay circuit DL1, so that the AND circuit AND1 opens the gate, and the node N2 The oscillation waveform is output to the output terminal OUT with a slight delay from the time when the output symmetry becomes 50%. Thus, a stable oscillation waveform with 50% output symmetry is output from the output terminal OUT.

<Second embodiment>
FIG. 3 is a circuit diagram showing the configuration of the oscillation circuit according to the second embodiment of the present invention. Reference numeral 1B denotes an oscillation circuit body. In addition to the CMOS inverters INV1, INV2, and INV3, the crystal oscillator X, the feedback resistor Rf, and the capacitors Cg and Cd described in FIG. It has an NMOS transistor MN1 connected to the input side of the CMOS inverter INV1, an NMOS transistor MN2 whose source is connected to the drain of the transistor MN1, whose drain is connected to the node N1, and whose gate is connected to the output of the CMOS inverter INV4. The input of the CMOS inverter INV4 is connected to the node N3 of the oscillation detection circuit 2. The transistors MN1 and MN2 constitute a voltage application circuit. The oscillation detection circuit 2 and the output control circuit 3 are the same as those shown in FIG.

  In this embodiment, immediately after the power is turned on, the charge of the capacitor C1 is discharged by the resistor R2, and the node N3 is “L” (= GND). For this reason, the transistor MN2 to which the output voltage of the CMOS inverter INV4 is applied to the gate is turned on.

  Therefore, when the power is turned on, the transistor MN1 is connected in parallel to the NMOS transistor (not shown) of the CMOS inverter INV1, so that the voltage at the node N1 is pulled down to the GND side and set to a voltage lower than VDD / 2. . This low voltage is lower than the threshold voltage of the CMOS inverter INV2, and even if the voltage of the node N1 fluctuates due to a minute power supply noise at the time of turning on the power, the threshold voltage of the CMOS inverter INV2 is not exceeded. The output of INV2 does not change. That is, self-excited oscillation does not occur. Further, the output of the AND circuit AND1 connected via the delay circuit DL1 connected to the node N3 which is “L” is fixed to “L”, and the output voltage of the output terminal OUT is in the oscillation output stop state. It becomes.

  When the parallel resonance circuit including the inductance component of the crystal resonator X1 and the capacitors Cg and Cd resonates and crystal oscillation starts, the feedback bias voltage is lowered to a voltage lower than the voltage VDD / 2 by the transistors MN1 and MN2, and the CMOS inverter INV1 Begins to work. When the output of the CMOS inverter INV1 is inverted by the CMOS inverter INV2, the waveform becomes a waveform having a long “L” time. The waveform of the output signal of the CMOS inverter INV3 is the same, and this output signal starts to be charged into the capacitor C1 via the resistor R1.

  When the voltage of the capacitor C1 (node N3) is charged to a level exceeding the threshold voltage of the CMOS inverter INV4, the output of the CMOS inverter INV4 becomes “L”, the transistor MN2 is turned OFF, and the pull-down of the node N1 is released. Thus, the feedback bias voltage returns to the voltage of VDD / 2. As a result, the output symmetry of the waveform of the oscillation output (node N2) of the CMOS inverter INV2 is 50%.

  At this time, the “H” voltage of the node N3 is input to one input side of the AND circuit AND1 after receiving a predetermined delay in the delay circuit DL1, so that the AND circuit AND1 opens the gate and the oscillation of the node N2 The waveform is output to the output terminal OUT with a slight delay from the time when the output symmetry becomes 50%. Thus, a stable oscillation waveform with 50% output symmetry is output from the output terminal OUT.

<Other examples>
In the first and second embodiments described above, the crystal oscillator X1 is not limited to this, and may be a vibrator that exhibits a specific inductance at a specific frequency, such as a ceramic vibrator. Further, the transistors constituting each circuit may be bipolar transistors in addition to the field effect transistors.

1 is a circuit diagram of an oscillation circuit according to a first embodiment of the present invention. FIG. 2 is an operation waveform diagram of the oscillation circuit of FIG. 1. It is a circuit diagram of the oscillation circuit of the 2nd Example of this invention. It is a block diagram which shows the structure of a delay circuit. It is a circuit diagram of the conventional oscillation circuit. FIG. 6 is an operation waveform diagram of the oscillation circuit of FIG. 5.

Claims (5)

An inverter connected to the first power source and the second power source, a first capacitor connected between the input side of the inverter and the second power source, an output side of the inverter and the second power source; And a feedback resistor and a vibrator connected in parallel between the input and output of the inverter, and the feedback bias voltage on the output side of the inverter is the voltage of the first power supply. And an oscillation circuit body set to an intermediate voltage between the voltages of the second power supply and an oscillation detection circuit for detecting an oscillation output signal oscillated by the oscillation circuit body, the oscillation circuit body including the oscillation detection When the circuit does not detect the oscillation output signal, it pulls up the output side voltage of the inverter to a voltage higher than the intermediate voltage, and when the oscillation detection circuit detects the oscillation output signal, the pull-up is canceled. In the oscillation circuit provided with a voltage application circuit,
The oscillation detection circuit includes an integration circuit having a first time constant that integrates an oscillation signal output from the oscillation circuit main body, and a discharge circuit having a second time constant that discharges electric charges integrated in the integration circuit. The oscillation circuit is characterized in that the second time constant is set to be larger than the first time constant, and the integration voltage of the integration circuit that has reached a predetermined value is a signal obtained by detecting the oscillation output signal . An inverter connected to the first power source and the second power source, a first capacitor connected between the input side of the inverter and the second power source, an output side of the inverter and the second power source; And a feedback resistor and a vibrator connected in parallel between the input and output of the inverter, and the feedback bias voltage on the output side of the inverter is the voltage of the first power supply. And an oscillation circuit body set to an intermediate voltage between the voltages of the second power supply and an oscillation detection circuit for detecting an oscillation output signal oscillated by the oscillation circuit body, the oscillation circuit body including the oscillation detection When the circuit does not detect the oscillation output signal, the output side voltage of the inverter is pulled down to a voltage lower than the intermediate voltage, and when the oscillation detection circuit detects the oscillation output signal, the pull-down is released. In the oscillation circuit provided with a voltage application circuit,
The oscillation detection circuit includes an integration circuit having a first time constant that integrates an oscillation signal output from the oscillation circuit main body, and a discharge circuit having a second time constant that discharges electric charges integrated in the integration circuit. The oscillation circuit is characterized in that the second time constant is set to be larger than the first time constant, and the integration voltage of the integration circuit that has reached a predetermined value is a signal obtained by detecting the oscillation output signal . The oscillation circuit according to claim 1 or 2,
The voltage application circuit includes an oscillation circuit the oscillation detection circuit is turned ON when not detecting the oscillation output signal, characterized by Oh Rukoto switch element to OFF when the detected. The oscillation circuit according to any one of claims 1 to 3,
When the oscillation detecting circuit does not detect the oscillation output signal, an oscillation circuit, wherein Rukoto an output control circuit for prohibiting the output of the output signal of the oscillating circuit body. The oscillation circuit according to claim 4 ,
The output control circuit, when the oscillation detecting circuit detects the oscillation output signal, an oscillation circuit, wherein that you cancel the output disable output signal of the oscillation circuit body after a predetermined time delay.

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