CN109085412A - A kind of opposite current detection circuit - Google Patents

A kind of opposite current detection circuit Download PDF

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Publication number
CN109085412A
CN109085412A CN201710445983.3A CN201710445983A CN109085412A CN 109085412 A CN109085412 A CN 109085412A CN 201710445983 A CN201710445983 A CN 201710445983A CN 109085412 A CN109085412 A CN 109085412A
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nmos tube
tube
grid
pmos
connects
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CN109085412B (en
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郑辰光
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SG Micro Beijing Co Ltd
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SG Micro Beijing Co Ltd
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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/14Indicating direction of current; Indicating polarity of voltage
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/0092Arrangements for measuring currents or voltages or for indicating presence or sign thereof measuring current only

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  • General Physics & Mathematics (AREA)
  • Measurement Of Current Or Voltage (AREA)

Abstract

A kind of opposite current detection circuit, be conducive to detect faint reverse current (such as flowing to end VIN etc. from the end VOUT) without using low maladjustment voltage comparator circuit using common voltage comparator, it is characterized in that, including the first power MOS pipe, the grid of first power MOS pipe is separately connected drive module and pressure limiting module, and pass through switch connection ground terminal, the source electrode and drain electrode of first power MOS pipe is respectively correspondingly connected with two input terminals of voltage comparator, the output end of the voltage comparator connects the switch control terminal of the switch, the positive input of the voltage comparator connects voltage output end, the negative input of the voltage comparator connects voltage input end, current sensor is set on route between the voltage output end and the power MOS pipe, the electricity Flow sensor connects current detection module, and the current detection module connects the pressure limiting module.

Description

A kind of opposite current detection circuit
Technical field
The present invention relates to reverse current detection technique, especially a kind of opposite current detection circuit is conducive to using common Voltage comparator can detect faint reverse current (such as flowing to end VIN etc. from the end VOUT) without using low maladjustment voltage Comparator circuit.
Background technique
With the development of Low-power Technology, often there are many supply voltages in same system, and at this moment reverse current blocks Function is also just more important.In addition under the widely applied background of On The Go technology, main equipment/all interchangeable from equipment.For It prevents reverse current from flowing into from the output port of low power consuming devices and quiescent current needed for it is provided, so reverse current blocks threshold Value also becomes lower and lower, such as 100mA or 10mA etc..Low reverse current is also required in certain special dimensions such as similar solar energy The observation circuit of threshold value is blocked, to improve efficiency of energy utilization.
Requirement of the market to output electric current in recent years is constantly higher, such as USB PD standard or power battery charging field Deng.Wish to reduce the equivalent impedance in transmission path as far as possible just so to improve efficiency, and traditional pass through detects transmission Reversed pressure drop can not block lower reverse current come the method for realizing that reverse current blocks on path, and cost is excessively high in other words. Be to block faint reverse current using the purpose of opposite current detection circuit, for example, by the circuit be connected on active equipment and Between active equipment, the access between pass hull closure after detecting lower reverse current, to prevent the confession of active load upstream device Electricity/electric leakage.
Summary of the invention
The present invention is in view of the deficiencies in the prior art or insufficient, provides a kind of opposite current detection circuit, is conducive to Faint reverse current (such as flowing to end VIN etc. from the end VOUT) can be detected without using low using common voltage comparator Offset voltage comparator circuit.
Technical scheme is as follows:
A kind of opposite current detection circuit, which is characterized in that including the first power MOS pipe, first power MOS pipe Grid is separately connected drive module and pressure limiting module, and by switch connection ground terminal, the source electrode of first power MOS pipe and Drain electrode is respectively correspondingly connected with two input terminals of voltage comparator, and the output end of the voltage comparator connects opening for the switch Control terminal is closed, the positive input of the voltage comparator connects voltage output end, the negative input of the voltage comparator Voltage input end is connected, current sensor is set on the route between the voltage output end and the power MOS pipe, it is described Current sensor connects current detection module, and the current detection module connects the pressure limiting module.
First power MOS pipe is power NMOS tube, and the source electrode of the power NMOS tube is separately connected the voltage ratio Compared with the positive input of device and the voltage output end, the drain electrode of the power NMOS tube is separately connected the voltage comparator Negative input and the voltage input end.
First power MOS pipe is power NMOS tube, and the source electrode of the power NMOS tube is separately connected the voltage ratio Compared with the positive input of the positive input of device and the voltage output end and amplifier, the negative sense of the amplifier is inputted End is separately connected the source electrode of induction NMOS tube and the source electrode of third PMOS tube, and the grid of the induction NMOS tube connects the power The grid of NMOS tube, the drain electrode of the induction NMOS tube connect the voltage input end, and the output end of the amplifier connects institute The grid of third PMOS tube is stated, the drain electrode of the third PMOS tube connects ground terminal by the first current source.
The drain electrode of the third PMOS tube is separately connected the drain and gate of the 4th NMOS tube, the source of the 4th NMOS tube Pole ground connection, the grid of the 4th NMOS tube connect the grid of the 5th NMOS tube, and the drain electrode of the 5th NMOS tube passes through second Current source connects the voltage input end, the source electrode ground connection of the 5th NMOS tube.
Second current source is accessed between the grid of the 6th metal-oxide-semiconductor and the grid of the 7th metal-oxide-semiconductor, the 6th MOS Six NMOS tube of Guan Wei, the 7th metal-oxide-semiconductor are the 7th PMOS tube, the drain electrode and the 7th PMOS tube of the 6th NMOS tube Drain electrode be connected with each other, the source electrode of the 7th PMOS tube connects the grid of the power NMOS tube, the 6th NMOS tube Source electrode is grounded by the 4th current source.
The output end of the voltage comparator connects the grid of the 8th metal-oxide-semiconductor, and the 8th metal-oxide-semiconductor is the 8th NMOS tube, The source electrode of 8th NMOS tube is grounded, and the drain electrode of the 8th NMOS tube connects the grid of the power NMOS tube, the function The grid of rate NMOS tube connects charge pump, and the charge pump connects the voltage input end by third current source.
First power MOS pipe is power tube PMOS, and the drain electrode of the power tube PMOS is separately connected the voltage ratio Compared with the positive input of the positive input of device and the voltage output end and amplifier, the negative sense of the amplifier is inputted End is separately connected the drain electrode of induction PMOS tube and the source electrode of third PMOS tube, and the grid of the induction PMOS tube connects the power The grid of PMOS tube, the source electrode of the induction PMOS tube connect the voltage input end, and the output end of the amplifier connects institute The grid of third PMOS tube is stated, the drain electrode of the third PMOS tube connects ground terminal by the first current source.
The drain electrode of the third PMOS tube is separately connected the drain and gate of the 4th NMOS tube, the source of the 4th NMOS tube Pole ground connection, the grid of the 4th NMOS tube connect the grid of the 5th NMOS tube, and the drain electrode of the 5th NMOS tube passes through second Current source connects the voltage input end, the source electrode ground connection of the 5th NMOS tube.
The drain electrode of 5th NMOS tube connects the grid of the 6th metal-oxide-semiconductor, the 6th MOS by the second inverting amplifier Six PMOS tube of Guan Wei, the grid of drain electrode the 7th metal-oxide-semiconductor of connection of the 6th PMOS tube, the 7th metal-oxide-semiconductor is the 7th NMOS tube, the drain electrode of the 6th PMOS tube are connected with each other with the drain electrode of the 7th NMOS tube, the source of the 7th NMOS tube Pole connects the grid of the power tube PMOS, and the source electrode of the 6th PMOS tube connects the voltage input by third current source End.
The output end of the voltage comparator by the first inverting amplifier connect the 8th metal-oxide-semiconductor grid, the described 8th Metal-oxide-semiconductor is the 8th PMOS tube, and the source electrode of the 8th PMOS tube connects the voltage input end, the drain electrode of the 8th PMOS tube It is divided into two tunnels, wherein connecting the grid of the power tube PMOS all the way, another way is grounded by the 4th current source.
Technical effect of the invention is as follows: a kind of opposite current detection circuit of the invention, can pass through output electric current inspection Slowdown monitoring circuit judges whether power MOS pipe enters light condition/reverse state, can be actively after light condition/reverse state Increase power MOS pipe conduction impedance, pressure limiting module reduces the absolute value of gate source voltage under the premise of guaranteeing power MOS conducting To realize the purpose for increasing power MOS pipe conduction impedance.Conduction impedance by increasing power MOS pipe just realizes that detection is faint anti- To the function of electric current, faint reverse current is just thus able to achieve using simple method and is detected, without designing putting for low imbalance Big device (A1) circuit.
Detailed description of the invention
Fig. 1 is to implement a kind of first case structural schematic diagram of opposite current detection circuit of the present invention.
Fig. 2 is to implement a kind of second case structural schematic diagram of opposite current detection circuit of the present invention.
Fig. 3 is to implement a kind of third example structural schematic diagram of opposite current detection circuit of the present invention.
Appended drawing reference lists as follows: 1- current detection module;2- pressure limiting module;3- drive module;4- current sensor;5- Ground terminal;6- switch control terminal;7- charge pump;The first power MOS pipe of M1- is (for example, power NMOS tube or power P MOS Pipe);A1- voltage comparator;S1- switching circuit or switch;VGGrid voltage or gate voltage values;VLOWOutput signal is defeated Signal value out;VIN- voltage input end or voltage input levels;VOUT- voltage output end or voltage output value;VRVComparator output Voltage;IOUTExport electric current or output current terminal;M2- incudes metal-oxide-semiconductor;A2- amplifier;M3- third PMOS tube;M4- the 4th NMOS tube;The 5th NMOS tube of M5-;The 6th metal-oxide-semiconductor of M6-;The 7th metal-oxide-semiconductor of M7-;The 8th metal-oxide-semiconductor of M8-;IB1- the first reference current or First current source;IB2- the second reference current or the second current source;ISEInduced current;IUPThird current source or charge pump current Source;IDW- the four current source or the 4th reference current.
Specific embodiment
With reference to the accompanying drawing (Fig. 1-Fig. 3) the present invention will be described.
Fig. 1 is to implement a kind of first case structural schematic diagram of opposite current detection circuit of the present invention.Fig. 2 is to implement the present invention A kind of second case structural schematic diagram of opposite current detection circuit.Fig. 3 is to implement a kind of opposite current detection circuit of the present invention Third example structural schematic diagram.As shown in Figure 1 to Figure 3, a kind of opposite current detection circuit, including the first power MOS pipe M1, it is described The grid of first power MOS pipe M1 is separately connected drive module 3 and pressure limiting module 2, and passes through switch S1 connection ground terminal 5, institute The source electrode and drain electrode for stating the first power MOS pipe M1 is respectively correspondingly connected with two input terminals of voltage comparator A1 (+and -), described The output end of voltage comparator A1 connects the switch control terminal 6 of the switch S1, the positive input of the voltage comparator A1 (+) connects voltage output end VOUT, negative input (-) connection voltage input end VIN of the voltage comparator A1, described Current sensor 4, the current sensor are set on the route between voltage output end VOUT and the first power MOS pipe M1 4 connection current detection modules 1, the current detection module 1 connect the pressure limiting module 2.The first power MOS pipe M1 is function Rate NMOS tube, the source electrode of the power NMOS tube are separately connected the positive input (+) and the electricity of the voltage comparator A1 Output end VOUT is pressed, the drain electrode of the power NMOS tube is separately connected negative input (-) and the institute of the voltage comparator A1 State voltage input end VIN.
The first power MOS pipe M1 is power NMOS tube, and the source electrode of the power NMOS tube is separately connected the voltage The positive input (+) of the positive input (+) of comparator A1 and the voltage output end VOUT and amplifier A2, it is described The negative input (-) of amplifier A2 is separately connected the source electrode and the 3rd PMOS of induction NMOS tube (see metal-oxide-semiconductor M2 is incuded in Fig. 2) The source electrode of pipe M3, the grid of the induction NMOS tube connect the grid of the power NMOS tube, the drain electrode of the induction NMOS tube The voltage input end VIN is connected, the output end of the amplifier A2 connects the grid of the third PMOS tube M3, the third The drain electrode of PMOS tube M3 passes through the first current source IB1Connect ground terminal 5.The drain electrode of the third PMOS tube M3 is separately connected the 4th The drain and gate of NMOS tube M4, the source electrode ground connection of the 4th NMOS tube M4, the grid connection the of the 4th NMOS tube M4 The drain electrode of the grid of five NMOS tube M5, the 5th NMOS tube M5 passes through the second current source IB2The voltage input end VIN is connected, The source electrode of the 5th NMOS tube M5 is grounded.The second current source IB2By the grid and the 7th metal-oxide-semiconductor of the 6th metal-oxide-semiconductor M6 of access Between the grid of M7, the 6th metal-oxide-semiconductor M6 be the 6th NMOS tube, the 7th metal-oxide-semiconductor M7 be the 7th PMOS tube, the described 6th The drain electrode of NMOS tube is connected with each other with the drain electrode of the 7th PMOS tube, and the source electrode of the 7th PMOS tube connects the power The source electrode of the grid of NMOS tube, the 6th NMOS tube passes through the 4th current source IDWGround connection.The output of the voltage comparator A1 The grid of the 8th metal-oxide-semiconductor M8 of end connection, the 8th metal-oxide-semiconductor M8 are the 8th NMOS tube, and the source electrode of the 8th NMOS tube is grounded, The drain electrode of 8th NMOS tube connects the grid of the power NMOS tube, and the grid of the power NMOS tube connects charge pump 7, The charge pump 7 passes through third current source IUPConnect the voltage input end VIN.
The first power MOS pipe M1 is power tube PMOS, and the drain electrode of the power tube PMOS is separately connected the voltage The positive input (+) of the positive input (+) of comparator A1 and the voltage output end VOUT and amplifier A2, it is described The negative input (-) of amplifier A2 is separately connected drain electrode and the 3rd PMOS of induction PMOS tube (see metal-oxide-semiconductor M2 is incuded in Fig. 3) The source electrode of pipe M3, the grid of the induction PMOS tube connect the grid of the power tube PMOS, the source electrode of the induction PMOS tube The voltage input end VIN is connected, the output end of the amplifier A2 connects the grid of the third PMOS tube M3, the third The drain electrode of PMOS tube M3 passes through the first current source IB1Connect ground terminal.The drain electrode of the third PMOS tube M3 is separately connected the 4th The drain and gate of NMOS tube M4, the source electrode ground connection of the 4th NMOS tube M4, the grid connection the of the 4th NMOS tube M4 The drain electrode of the grid of five NMOS tube M5, the 5th NMOS tube M5 passes through the second current source IB2The voltage input end VIN is connected, The source electrode of the 5th NMOS tube M5 is grounded.The drain electrode of the 5th NMOS tube M5 passes through the second inverting amplifier connection the 6th The grid of metal-oxide-semiconductor M6, the 6th metal-oxide-semiconductor M6 are the 6th PMOS tube, and the drain electrode of the 6th PMOS tube connects the 7th metal-oxide-semiconductor M7 Grid, the 7th metal-oxide-semiconductor M7 is the 7th NMOS tube, drain electrode and the drain electrode of the 7th NMOS tube of the 6th PMOS tube It is connected with each other, the source electrode of the 7th NMOS tube connects the grid of the power tube PMOS, and the source electrode of the 6th PMOS tube is logical Cross third current source IUPConnect the voltage input end VIN.
The output end of the voltage comparator A1 connects the grid of the 8th metal-oxide-semiconductor M8 by the first inverting amplifier, described 8th metal-oxide-semiconductor M8 is the 8th PMOS tube, and the source electrode of the 8th PMOS tube connects the voltage input end VIN, the described 8th The drain electrode of PMOS tube is divided into two tunnels, wherein connecting the grid of the power tube PMOS all the way, another way passes through the 4th current source IDW Ground connection.
Fig. 1 includes power NMOS (M1), drive module, current detection module, pressure limiting module, voltage comparator (A1) and opens It closes (S1).Wherein VIN termination power, and VOUT terminating load.Its function is as follows: when the output electric current of current detection module detection When lower, which is in light-load mode, and its output signal VLOW is effective.This will promote to limit module work simultaneously Drag down VG.And the equivalent impedance of M1 will be caused to become larger after VG-VOUT is lower.After the equivalent impedance of M1 becomes larger, faint is reversed Electric current can produce the pressure difference for being enough to make A1 comparator to overturn, and hereafter VRV is high and is closed S1.After S1 closure, VG further drops It is low be zero and cause power NMOS (M1) end.To sum up, this circuit arrangement is just realized by increasing the conduction impedance of power MOS pipe Detect the function of faint reverse current.
The working principle of Fig. 2 circuit is as follows:
1.VIN is power voltage input terminal, and VOUT is output voltage terminal.
2.M1 is larger-size power NMOS tube, and M2 is induction NMOS tube, and M1 is proportional to M2.
3. charge pump serves as the drive module of power NMOS tube, wherein IUP is the current source of charge pump.
4.IOUT is power NMOS tube source current, and ISE is induction NMOS tube source current.
5.A1 is voltage comparator, and A2 is amplifier.
6.A2, M3 and current source IB1 form current detection module, and it forces the ratio between ISE and IOUT to be equal to M2 and M1 The ratio between size.
7.M6, M7 and reference current IDW form pressure limiting module.
8. the ISE proportional to IOUT is less than reference current IB1 when the connect light load of VOUT (light condition), therefore M4 also causes M5 without drain current without drain current, therefore VLOW can become high level with reference current IB2.
9.VLOW be high level when M6 (NMOS) be connected, when IDW be more than or equal to IUP after, VG voltage can decline (VGS1 also under Drop), and VOUT+VGS1=VIN+VSG7 is depended on, wherein VSG7 is M7 (PMOS) for the gate source voltage of VGS1 power NMOS tube Source gate voltage.
10.VGS1 decline, causes the conducting resistance (Rds_on) of M1 to become larger naturally.
11. the source voltage of M2 is equal to VIN, thus compares light condition after VOUT is more than or equal to VIN (reverse state) ISE becomes smaller, so 8 and 9 description is still set up, the conduction impedance of power NMOS tube still remains very big.
12. as described above, as long as the invention circuit setting suitable parameters obtain becoming sufficiently large under reverse state Power NMOS conducting resistance, the A1 of ordinary construction can detect faint reverse current (flowing to the end VIN from the end VOUT), without Design low maladjustment voltage comparator (A1) circuit.
The working principle of Fig. 3 circuit is as follows:
1.VIN is power voltage input terminal, and VOUT is output voltage terminal.
2.M1 is larger-size power tube PMOS, and M2 is induction PMOS tube, and M1 is proportional to M2.
3. the drive module that current source IDW serves as power tube PMOS.
4.IOUT is power tube PMOS source current, and ISE is induction PMOS tube source current.
5.A1 is voltage comparator, and A2 is amplifier circuit.
6.A2, M3 and current source IB1 form current detection module, and it forces the ratio between ISE and IOUT to be equal to M2 and M1 The ratio between size.
7.M6, M7 and reference current IUP form pressure limiting module.
8. the ISE proportional to IOUT is less than reference current IB1 when the connect light load of VOUT (light condition), therefore M4 also causes M5 without drain current without drain current, therefore VLOW can become high level with reference current IB2.
M6 (NMOS) is connected when 9.VLOW is high level, and after IUP is more than or equal to IDW, VG voltage can rise (under VSG1 Drop), and VOUT+VSG1=VIN+VGS7 is depended on, wherein VGS7 is M7 (NMOS) for the source gate voltage of VSG1 power tube PMOS Gate source voltage.
10.VSG1 decline, causes the conducting resistance (Rds_on) of M1 to become larger naturally.
11. the source voltage of M2 is equal to VIN, thus compares light condition after VOUT is more than or equal to VIN (reverse state) ISE becomes smaller, so 8 and 9 description is still set up, the conduction impedance of power tube PMOS still remains very big.
12. as described above, as long as the invention circuit setting suitable parameters obtain becoming sufficiently large under reverse state Power P MOS conducting resistance, the A1 of ordinary construction can detect faint reverse current (flowing to the end VIN from the end VOUT), without Design voltage comparator (A1) circuit of low maladjustment voltage.
It is hereby stated that described above facilitate those skilled in the art understand that the invention, but not limit the present invention The protection scope of creation.Any equivalent replacement described above, modification are improved without disengaging the invention substantive content And/or delete numerous conform to the principle of simplicity and the implementation that carries out, each fall within the protection scope of the invention.

Claims (10)

1. a kind of opposite current detection circuit, which is characterized in that including the first power MOS pipe, the grid of first power MOS pipe Pole is separately connected drive module and pressure limiting module, and passes through switch connection ground terminal, the source electrode of first power MOS pipe and leakage Two input terminals of voltage comparator are extremely respectively correspondingly connected with, the output end of the voltage comparator connects the switch of the switch Control terminal, the positive input of the voltage comparator connect voltage output end, and the negative input of the voltage comparator connects Voltage input end is connect, current sensor, the electricity are set on the route between the voltage output end and the power MOS pipe Flow sensor connects current detection module, and the current detection module connects the pressure limiting module.
2. a kind of opposite current detection circuit according to claim 1, which is characterized in that first power MOS pipe is Power NMOS tube, the source electrode of the power NMOS tube be separately connected the voltage comparator positive input and the voltage it is defeated The drain electrode of outlet, the power NMOS tube is separately connected the negative input and the voltage input end of the voltage comparator.
3. a kind of opposite current detection circuit according to claim 1, which is characterized in that first power MOS pipe is Power NMOS tube, the source electrode of the power NMOS tube be separately connected the voltage comparator positive input and the voltage it is defeated The positive input of outlet and amplifier, the negative input of the amplifier be separately connected induction NMOS tube source electrode and The grid of the source electrode of third PMOS tube, the induction NMOS tube connects the grid of the power NMOS tube, the induction NMOS tube Drain electrode connect the voltage input end, the output end of the amplifier connects the grid of the third PMOS tube, the third The drain electrode of PMOS tube connects ground terminal by the first current source.
4. a kind of opposite current detection circuit according to claim 3, which is characterized in that the drain electrode of the third PMOS tube It is separately connected the drain and gate of the 4th NMOS tube, the source electrode ground connection of the 4th NMOS tube, the grid of the 4th NMOS tube The grid of the 5th NMOS tube is connected, the drain electrode of the 5th NMOS tube connects the voltage input end, institute by the second current source State the source electrode ground connection of the 5th NMOS tube.
5. a kind of opposite current detection circuit according to claim 4, which is characterized in that second current source is accessed Between the grid of 6th metal-oxide-semiconductor and the grid of the 7th metal-oxide-semiconductor, the 6th metal-oxide-semiconductor is the 6th NMOS tube, the 7th metal-oxide-semiconductor For the 7th PMOS tube, the drain electrode of the 6th NMOS tube is connected with each other with the drain electrode of the 7th PMOS tube, the 7th PMOS The source electrode of pipe connects the grid of the power NMOS tube, and the source electrode of the 6th NMOS tube is grounded by the 4th current source.
6. a kind of opposite current detection circuit according to claim 3, which is characterized in that the output of the voltage comparator The grid of the 8th metal-oxide-semiconductor of end connection, the 8th metal-oxide-semiconductor are the 8th NMOS tube, and the source electrode of the 8th NMOS tube is grounded, described The drain electrode of 8th NMOS tube connects the grid of the power NMOS tube, and the grid of the power NMOS tube connects charge pump, described Charge pump connects the voltage input end by third current source.
7. a kind of opposite current detection circuit according to claim 1, which is characterized in that first power MOS pipe is Power tube PMOS, the drain electrode of the power tube PMOS be separately connected the voltage comparator positive input and the voltage it is defeated The positive input of outlet and amplifier, the negative input of the amplifier be separately connected induction PMOS tube drain electrode and The grid of the source electrode of third PMOS tube, the induction PMOS tube connects the grid of the power tube PMOS, the induction PMOS tube Source electrode connect the voltage input end, the output end of the amplifier connects the grid of the third PMOS tube, the third The drain electrode of PMOS tube connects ground terminal by the first current source.
8. a kind of opposite current detection circuit according to claim 7, which is characterized in that the drain electrode of the third PMOS tube It is separately connected the drain and gate of the 4th NMOS tube, the source electrode ground connection of the 4th NMOS tube, the grid of the 4th NMOS tube The grid of the 5th NMOS tube is connected, the drain electrode of the 5th NMOS tube connects the voltage input end, institute by the second current source State the source electrode ground connection of the 5th NMOS tube.
9. a kind of opposite current detection circuit according to claim 8, which is characterized in that the drain electrode of the 5th NMOS tube The grid of the 6th metal-oxide-semiconductor is connected by the second inverting amplifier, the 6th metal-oxide-semiconductor is the 6th PMOS tube, the 6th PMOS Pipe drain electrode connection the 7th metal-oxide-semiconductor grid, the 7th metal-oxide-semiconductor be the 7th NMOS tube, the drain electrode of the 6th PMOS tube with The drain electrode of 7th NMOS tube is connected with each other, and the source electrode of the 7th NMOS tube connects the grid of the power tube PMOS, institute The source electrode for stating the 6th PMOS tube connects the voltage input end by third current source.
10. a kind of opposite current detection circuit according to claim 7, which is characterized in that the voltage comparator it is defeated Outlet by the first inverting amplifier connect the 8th metal-oxide-semiconductor grid, the 8th metal-oxide-semiconductor be the 8th PMOS tube, the described 8th The source electrode of PMOS tube connects the voltage input end, and the drain electrode of the 8th PMOS tube is divided into two tunnels, wherein all the way described in connection The grid of power tube PMOS, another way are grounded by the 4th current source.
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Cited By (2)

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Publication number Priority date Publication date Assignee Title
CN112946351A (en) * 2019-12-11 2021-06-11 圣邦微电子(北京)股份有限公司 Negative follow current monitoring circuit
CN113702790A (en) * 2020-05-23 2021-11-26 圣邦微电子(北京)股份有限公司 Current detection circuit in high-voltage application

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