CN112946351A - Negative follow current monitoring circuit - Google Patents
Negative follow current monitoring circuit Download PDFInfo
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- CN112946351A CN112946351A CN201911264724.6A CN201911264724A CN112946351A CN 112946351 A CN112946351 A CN 112946351A CN 201911264724 A CN201911264724 A CN 201911264724A CN 112946351 A CN112946351 A CN 112946351A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/175—Indicating the instants of passage of current or voltage through a given value, e.g. passage through zero
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
A negative afterflow current monitoring circuit comprises an NMOS power switch tube and an inductive load driven by the NMOS power switch tube through a first node and a second node, wherein the NMOS power switch tube is connected with a closed negative feedback current acquisition circuit; the closed negative feedback current acquisition circuit and the NMOS power switch tube jointly form a closed negative feedback current acquisition loop, the closed negative feedback current acquisition loop monitors and acquires negative follow current flowing through the NMOS power switch tube, the closed negative feedback current acquisition loop acquires the negative follow current flowing through the NMOS power switch tube and converts the negative follow current into positive current of a corresponding proportion to replace an open-loop comparator to monitor the attenuation process of the negative follow current, particularly the zero crossing point of the negative follow current after attenuation is finished, the structure is simple, the design cost is reduced, the closed-loop detection speed is high, the anti-jamming capability is high, and the converted positive current of the corresponding proportion is convenient for subsequent processing, such as comparison with reference current, and then the negative follow current is judged and controlled.
Description
Technical Field
The invention relates to a negative afterflow current monitoring technology, in particular to a negative afterflow current monitoring circuit.
Background
The most remarkable characteristic of the MOS power switch is that the MOS power switch has good switching characteristics, and therefore, the MOS power switch is widely used in a circuit requiring an electronic switch. As shown in fig. 1, in a circuit in which an inductive load L is driven by an NMOS power switching tube Mpwr, since an inductive load current of an inductive load such as a motor, a solenoid valve, or the like is freewheeling in a negative direction, when the NMOS power switching tube Mpwr is turned on, a negative freewheeling current Iload freewheels from a second node B to a first node a, and at this time, the on internal resistance of the NMOS power switching tube Mpwr is Rpwr, a voltage difference VAB between the first node a and the second node B at both ends of the NMOS power switching tube Mpwr is-rrowr Iload <0, and thus the negative freewheeling current Iload is freewheeling current in a circuit from the first node a to the second node B at this time. Some actions of the NMOS power switch tube Mpwr need to be triggered by, for example, a zero crossing point after the attenuation is finished according to the attenuation condition of the negative-going freewheeling current Iload. In the prior art, a technical scheme for monitoring a zero-crossing point of the negative-going afterflow current Iload after the attenuation is finished is to detect and judge the potential of a first node a through an open-loop comparator, and when VAB is equal to 0V, the negative-going afterflow current Iload is indicated to be finished after the attenuation. Specifically, as shown in fig. 2, the open-loop comparator comp has a positive input connected to the first node a and a negative input set to 0V (or ground), i.e., a zero-crossing comparator is constructed by the open-loop comparator comp, and the zero-crossing comparator has a certain measurement error in the measurement mode. Therefore, the scheme has the following disadvantages: 1. because the swing range of the first node a is extremely large and the swing speed is extremely high, the requirement on the input stage of the open-loop comparator comp is high, and the design cost is increased; 2. when the on-resistance Rpwr of the NMOS power switching tube Mpwr is extremely low (possibly in the order of m omega), or the negative follow current Iload is very small, or the negative follow current Iload is attenuated to be very small, VAB-Rpwr Iload, the voltage difference between the first node A and the second node B is very small, so that the precision requirement of the open-loop comparator comp is very high, and once the precision of the open-loop comparator does not meet the requirement, the judgment accuracy of the zero crossing point is greatly influenced; 3. the scheme is an open-loop monitoring process, has low anti-interference performance to the environment and is low in judgment speed.
Disclosure of Invention
In order to solve the problems, the invention provides a negative follow current monitoring circuit, which adopts a closed negative feedback loop to collect negative follow current and convert the negative follow current into positive current with corresponding proportion to replace an open-loop comparator to monitor the attenuation process of the negative follow current, in particular to a zero crossing point of the negative follow current after attenuation is finished.
The invention is realized by the following technical scheme:
a negative afterflow current monitoring circuit comprises an NMOS power switch tube and an inductive load driven by the NMOS power switch tube through a first node and a second node, and is characterized in that the NMOS power switch tube is connected with a closed negative feedback current acquisition circuit, the closed negative feedback current acquisition circuit and the NMOS power switch tube jointly form a closed negative feedback current acquisition loop, and the closed negative feedback current acquisition loop monitors and acquires the negative afterflow current flowing through the NMOS power switch tube.
Preferably, the closed negative feedback current acquisition circuit comprises an NMOS current sampling tube, the NMOS current sampling tube is interconnected with the gate of the NMOS power switch tube and connected to a high level, the drain of the NMOS current sampling tube and the drain of the NMOS power switch tube are connected to the first node, the source of the NMOS power switch tube is connected to the second node, and the source of the NMOS current sampling tube is connected to the third node; the third node is connected with the drain electrode of the second NMOS tube, the source electrode of the first NMOS current input tube and the substrate, and the drain electrode of the first NMOS current input tube is connected with the working voltage through a first current source; the second node is connected with a source electrode of a second NMOS current input tube, and a drain electrode of the second NMOS current input tube is connected with a working voltage through a second current source; the grid electrodes of the first NMOS current input tube and the second NMOS current input tube are interconnected; the second node is connected to the drain electrode of the second NMOS tube through a third current source, the grid electrode of the second NMOS tube is connected with the drain electrode of the second NMOS current input tube, the source electrode of the second NMOS tube is connected with the drain electrode of a third PMOS tube, the source electrode and the substrate of the third PMOS tube are connected with a working voltage, the grid electrodes of the third PMOS tube and a fourth PMOS tube are interconnected, the source electrode of the fourth PMOS tube is connected with the working voltage, the first current source, the second current source, the first NMOS current input tube, the second NMOS tube and the third PMOS tube jointly act to enable the potentials of the third node and the second node to be equal, and negative follow current is led out from the drain electrode of the fourth PMOS tube and converted into positive current in corresponding proportion.
Preferably, the size ratio of the third PMOS transistor to the fourth PMOS transistor is 1: 1.
preferably, the output currents of the first current source and the third current source are much smaller than the current flowing through the NMOS current sampling tube.
Preferably, the output currents of the first current source and the second current source are equal, and the size ratio of the first NMOS current input tube to the second NMOS current input tube is 1: 1.
compared with the prior art, the invention has the advantages that: the negative follow current monitoring circuit provided by the invention has the advantages that the closed negative feedback current acquisition circuit and the NMOS power switch tube jointly form a closed negative feedback current acquisition loop, the negative follow current flowing through the NMOS power switch tube is acquired and converted into the positive current with the corresponding proportion to replace an open-loop comparator to monitor the attenuation process of the negative follow current, particularly the zero crossing point of the negative follow current after the attenuation is finished, the structure is simple, the design cost is reduced, the closed-loop detection speed is high, the anti-jamming capability is strong, and the converted positive current with the corresponding proportion is convenient for subsequent processing, such as comparison with a reference current, so that the negative follow current is judged and controlled.
Drawings
FIG. 1 is a schematic diagram of a negative-going freewheeling circuit for an inductive load driven by an NMOS power switch transistor;
FIG. 2 is a diagram illustrating a conventional open-loop comparator for monitoring negative freewheeling current of an inductive load driven by an NMOS power switch;
FIG. 3 is a schematic diagram of a negative-going current monitoring circuit according to the present invention.
The various reference numbers in the figures are listed below: Mpwr-NMOS power switch tube; an L-inductive load; iload-negative freewheeling current; a-a first node; b-a second node; c-a third node; phi-high potential point; a Msen-NMOS current sampling tube; m1 a-first NMOS current input tube; m1 b-second NMOS current input tube; m2-second NMOS tube; m3-third PMOS tube; m4-fourth PMOS tube; isen — first sample current; i2-second sampling current; i3-third sample current; i4 — fourth sample current; ib1 — first current source; ib2 — second current source; ib3 — third current source; vcc — operating voltage.
Detailed Description
In order to facilitate an understanding of the invention, the invention is described in more detail below with reference to the accompanying drawings and specific examples.
The negative follow current monitoring circuit comprises an NMOS power switch tube Mpwr driving inductive load L, wherein the NMOS power switch tube is connected with a closed negative feedback current acquisition circuit; the closed negative feedback current acquisition circuit and the NMOS power switch tube jointly form a closed negative feedback current acquisition loop, and the closed negative feedback current acquisition loop monitors and acquires negative follow current flowing through the NMOS power switch tube.
Specifically, the NMOS power switch tube Mpwr extracts the negative freewheeling current Iload through the NMOS current sampling tube Msen connected to the NMOS power switch tube Mpwr in a mirror image manner, and transmits the negative freewheeling current Iload to the drain of the fourth PMOS tube M4 through the second NMOS tube M2, the third PMOS tube M3 and the fourth PMOS tube M4. Further, the closed negative feedback current collection circuit comprises an NMOS current sampling tube Msen, the gate of the NMOS current sampling tube Msen and the gate of the NMOS power switch tube Mpwr are interconnected and connected with a high level Φ, the drain of the NMOS current sampling tube Msen and the drain of the NMOS power switch tube Mpwr are connected to the first node a, the source of the NMOS power switch tube Mpwr is connected to the second node B, and the source of the NMOS current sampling tube Msen is connected to a third node C; the third node C is connected to the drain of the second NMOS transistor M2, the source of the first NMOS current input transistor M1a and the substrate, and the drain of the first NMOS current input transistor M1a is connected to the operating voltage Vcc through a first current source Ib 1; the second node B is connected to the source of a second NMOS current input tube M1B, and the drain of the second NMOS current input tube M1B is connected to the operating voltage Vcc through a second current source Ib 2; the gates of the first and second NMOS current input transistors M1a and M1b are interconnected. The second node B is connected to the drain of the second NMOS transistor M2 through a third current source Ib3, and the output currents of the first current source Ib1 and the third current source Ib3 are much smaller than the first sampling current Isen flowing through the NMOS current sampling transistor; the gate of the second NMOS transistor M2 is connected to the drain of the second NMOS current input transistor M2b, the source of the second NMOS transistor M2 is connected to the drain of the third PMOS transistor M3, the source and the substrate of the third PMOS transistor M3 are connected to the operating voltage Vcc, the gate of the third PMOS transistor M3 is connected to the gate of the fourth PMOS transistor M4, the source of the fourth PMOS transistor M4 is connected to the operating voltage Vcc, and the negative freewheeling current is finally transmitted from the drain of the fourth PMOS transistor M4. The first current source Ib1, the second current source Ib2, the first NMOS current input tube M1a, the second NMOS current input tube M1B, the second NMOS tube M2 and the third PMOS tube M3 cooperate to make the potentials of the third node C and the second node B equal. Since the potentials of the third node C and the second node B are equal, and the Φ point is a high level, the potentials of the source electrode, the gate electrode and the drain electrode of the NMOS current sampling tube and the NMOS power switching tube are respectively equal, so that the first sampling current Isen flowing through the NMOS current sampling tube is equal to an integer K times of the negative freewheeling current Iload flowing through the NMOS power switching tube, that is, Isen is K · Iload, where K is a size ratio of the NMOS current sampling tube to the NMOS power switching tube.
Since the current I2 flowing through the second NMOS transistor is Ib3+ (Isen-Ib1), where Ib1, Ib3 are much smaller than Isen, when the size ratio of the third PMOS transistor M3 to the fourth PMOS transistor M4 is 1: when 1, the third sampling current I3 flowing through the third PMOS transistor M3, the fourth sampling current I4 flowing through the fourth PMOS transistor M4, the current I2 flowing through the second NMOS transistor, and the first sampling current Isen flowing through the NMOS current sampling transistor are equal, that is, I4I 3I 2I Isen-K I load, that is, the negative freewheeling current I Iload is collected from the drain of the fourth PMOS transistor M4 through a closed negative feedback current collection loop and converted into a positive current of a corresponding proportion. If no current is detected at the drain end of the fourth PMOS transistor M4, no negative freewheeling current exists in the circuit of the inductive load driven by the NMOS power switch transistor, i.e. the current collected by the closed negative feedback current collection loop is 0 at this time.
Preferably, the output currents of the first current source and the second current source are equal, and the size ratio of the first NMOS current input tube to the second NMOS current input tube is 1: 1.
it should be noted that the above-described embodiments may enable those skilled in the art to more fully understand the present invention, but do not limit the present invention in any way. Therefore, although the present invention has been described in detail with reference to the drawings and examples, it will be understood by those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention.
Claims (5)
1. A negative afterflow current monitoring circuit comprises an NMOS power switch tube and an inductive load driven by the NMOS power switch tube through a first node and a second node, and is characterized in that the NMOS power switch tube is connected with a closed negative feedback current acquisition circuit, the closed negative feedback current acquisition circuit and the NMOS power switch tube jointly form a closed negative feedback current acquisition loop, and the closed negative feedback current acquisition loop monitors and acquires the negative afterflow current flowing through the NMOS power switch tube.
2. The negative-going freewheeling current monitoring circuit according to claim 1, wherein the closed negative feedback current collection circuit comprises an NMOS current sampling tube, the NMOS current sampling tube is interconnected with the gate of the NMOS power switch tube and connected to a high level, the NMOS current sampling tube and the drain of the NMOS power switch tube are connected to the first node, the source of the NMOS power switch tube is connected to the second node, and the source of the NMOS current sampling tube is connected to a third node; the third node is connected with the drain electrode of the second NMOS tube, the source electrode of the first NMOS current input tube and the substrate, and the drain electrode of the first NMOS current input tube is connected with the working voltage through a first current source; the second node is connected with a source electrode of a second NMOS current input tube, and a drain electrode of the second NMOS current input tube is connected with a working voltage through a second current source; the grid electrodes of the first NMOS current input tube and the second NMOS current input tube are interconnected; the second node is connected to the drain electrode of the second NMOS tube through a third current source, the grid electrode of the second NMOS tube is connected with the drain electrode of the second NMOS current input tube, the source electrode of the second NMOS tube is connected with the drain electrode of a third PMOS tube, the source electrode and the substrate of the third PMOS tube are connected with a working voltage, the grid electrodes of the third PMOS tube and a fourth PMOS tube are interconnected, the source electrode of the fourth PMOS tube is connected with the working voltage, the first current source, the second current source, the first NMOS current input tube, the second NMOS tube and the third PMOS tube jointly act to enable the potentials of the third node and the second node to be equal, and negative follow current is led out from the drain electrode of the fourth PMOS tube and converted into positive current in corresponding proportion.
3. The negative freewheeling current monitoring circuit of claim 2, wherein the size ratio of the third PMOS transistor to the fourth PMOS transistor is 1: 1.
4. the negative-going freewheel current monitoring circuit according to claim 2, characterized in that, the output currents of the first and third current sources are much smaller than the current flowing through the NMOS current sampling tube.
5. The negative-going freewheel current monitoring circuit of claim 2 characterized in that, the output current of first current source and the second current source is equal, the size ratio of the first NMOS current input tube and the second NMOS current input tube is 1: 1.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201911264724.6A CN112946351B (en) | 2019-12-11 | 2019-12-11 | Negative follow current monitoring circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201911264724.6A CN112946351B (en) | 2019-12-11 | 2019-12-11 | Negative follow current monitoring circuit |
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| CN112946351A true CN112946351A (en) | 2021-06-11 |
| CN112946351B CN112946351B (en) | 2023-04-11 |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101795087A (en) * | 2010-04-02 | 2010-08-04 | 河南科技大学 | Inductive load commutation method |
| US20140021979A1 (en) * | 2012-07-19 | 2014-01-23 | Fairchild Semiconductor Corporation | Circuit and method for overcurrent detection of power switch |
| CN104977450A (en) * | 2014-04-03 | 2015-10-14 | 深圳市中兴微电子技术有限公司 | Current sampling circuit and method |
| CN109061272A (en) * | 2018-08-30 | 2018-12-21 | 广州金升阳科技有限公司 | A kind of current detection circuit |
| CN109085412A (en) * | 2017-06-14 | 2018-12-25 | 圣邦微电子（北京）股份有限公司 | A kind of opposite current detection circuit |
| CN110261661A (en) * | 2019-04-18 | 2019-09-20 | 矽力杰半导体技术(杭州)有限公司 | Current detection circuit and power inverter |
-
2019
- 2019-12-11 CN CN201911264724.6A patent/CN112946351B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101795087A (en) * | 2010-04-02 | 2010-08-04 | 河南科技大学 | Inductive load commutation method |
| US20140021979A1 (en) * | 2012-07-19 | 2014-01-23 | Fairchild Semiconductor Corporation | Circuit and method for overcurrent detection of power switch |
| CN103575964A (en) * | 2012-07-19 | 2014-02-12 | 快捷半导体(苏州)有限公司 | Over-current detection circuit and method for power switch tube |
| CN104977450A (en) * | 2014-04-03 | 2015-10-14 | 深圳市中兴微电子技术有限公司 | Current sampling circuit and method |
| CN109085412A (en) * | 2017-06-14 | 2018-12-25 | 圣邦微电子（北京）股份有限公司 | A kind of opposite current detection circuit |
| CN109061272A (en) * | 2018-08-30 | 2018-12-21 | 广州金升阳科技有限公司 | A kind of current detection circuit |
| CN110261661A (en) * | 2019-04-18 | 2019-09-20 | 矽力杰半导体技术(杭州)有限公司 | Current detection circuit and power inverter |
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| CN112946351B (en) | 2023-04-11 |
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