CN106405212B - Double edge triggering differential method peak detectors and peak-value detection method - Google Patents
Double edge triggering differential method peak detectors and peak-value detection method Download PDFInfo
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- CN106405212B CN106405212B CN201611139197.2A CN201611139197A CN106405212B CN 106405212 B CN106405212 B CN 106405212B CN 201611139197 A CN201611139197 A CN 201611139197A CN 106405212 B CN106405212 B CN 106405212B
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Abstract
The invention discloses double along triggering differential method peak detector and peak-value detection method；It is a kind of double along triggering differential method signal peak detectors, including it is differential circuit, double along trigger comparator circuit and sampling hold circuit；It is characterized by: the differential circuit be used for input signal carry out differential transform processing, obtain the differential transform of input signal as a result, and when input signal is in peak value or valley, obtained differential transform output signal is exactly in zero point or reference voltage；Double output signals that differential circuit is received along trigger comparator circuit, it is compared with zero-point voltage or reference voltage, and exports double digital controlled signals along triggering according to comparison result, is sampled or kept to operate to control sampling hold circuit；The present invention has many advantages, such as that working frequency is high, detection accuracy is high, Self-resetting, realizes the high-precision peak detection of high-frequency, can be widely used in various sophisticated signal sampling systems.
Description
Technical field
The present invention relates to peak detections, and in particular to double along triggering differential method peak detector and peak-value detection method.
Background technique
The effect of peak detection is extracted to the peak value of input signal, is generated output voltage and is equal to input signal peak value
Voltage.Peak detection circuit is sought circuit in automatic growth control (AGC) circuit, sensor most value, is answered in AD/DA circuit extensively
With usually generally as the foundation of gain-programmed amplifier multiple selection, the detection accuracy and working frequency of peak detection circuit
Etc. indexs directly determine the performance of parameter acquisition system.With the continuous improvement of current demand signal frequency, the multiplicity of signal kinds
Change development, higher requirements are also raised for working frequency and detection accuracy to peak detector etc..
Conventional peak detection circuit judges there is detection essence using the instruction that the positively biased characteristic of diode is kept as sampling
Degree height, the simple advantage of structure, but due to the frequency response characteristic of diode, input signal working frequency is by the very day of one's doom
System, and when being applied to the continually changing complicated sampling system of input signal amplitude, need to introduce additional reset circuit and
Corresponding logical algorithm, it is more difficult to meet the needs of complex parameters sampling system.
Summary of the invention
Technical problem to be solved by the present invention lies in provide double edge triggering differential method peak detectors and peak detection inspection
Survey method is realized and is detected to the peak values in real time of high-frequency input signal.
In order to solve the above-mentioned technical problem, first technical solution of the invention is: a kind of double along triggering differential method signal
Peak detector, including it is differential circuit, double along trigger comparator circuit and sampling hold circuit；Its main feature is that:
The differential circuit is used to carry out differential transform processing to input signal, obtains the differential transform knot of input signal
Fruit, and when input signal is in peak value or valley, obtained differential transform output signal is exactly in zero point or reference voltage；
Processing is compared convenient for comparator；
Double output signals that differential circuit is received along trigger comparator circuit, by itself and zero-point voltage or reference voltage
It is compared, and double digital controlled signals along triggering is exported according to comparison result, sampled with controlling sampling hold circuit
Or keep operation；
The sampling hold circuit includes two-stage emitter follower, high-speed switching circuit and holding capacitor；First order emitter-base bandgap grading
Follower and differential circuit receive input signal simultaneously, and output follows input signal, and the output of second level emitter follower is
It is exported for final peak detection result；High-speed switching circuit is connected to output and the second level emitter-base bandgap grading of first order emitter follower
Between the input of follower, and the input terminal of second level emitter follower is grounded by holding capacitor, high-speed switching circuit
On-off is by double along the double along triggering digital controlled signal control of trigger comparator circuit output；When high-speed switching circuit conducting,
The output signal of first order emitter follower charges to holding capacitor, and when high-speed switching circuit disconnects, holding capacitor passes through the
The electric discharge of second level emitter follower；The control signal of high-speed switch is provided by double along trigger comparator circuit.
The present invention realizes the differential transform of input signal using differential circuit, when input signal is in peak value or valley
When, obtained differential transform output signal is exactly in zero point or reference voltage value, realizes to the high-precision of input signal peak value
Degree judgement；It is obtained along trigger comparator circuit for controlling the double along triggering digital control letter of sampling hold circuit using double
Number.Differential transform output signal is compared with zero-point voltage or reference voltage value along trigger comparator circuit by using double
Compared with when input signal is also not up to peak value, differential transform output signal is higher than zero-point voltage or reference voltage value, then double along touching
It sends out comparator circuit and exports high level.When input signal reaches peak value, differential transform output signal is equal to zero-point voltage or ginseng
Examine voltage value, then it is double to be jumped by high level to low level along trigger comparator circuit output.In next cycle, when input is believed
Number be in rising edge when, differential transform output signal be higher than zero-point voltage or reference voltage value, then output again jumped by low level
To high level.To obtain in double along triggering digital controlled signals, the real-time control to the high-speed switch of sampling hold circuit is realized.
The present invention is sampled to input signal and is kept two kinds of operations using sampling hold circuit, when double along trigger comparator circuit
When double edge triggering digital controlled signals of output are high level, high-speed switch conducting, output signal follows input signal to change, is
Sample states.When double double edge triggering digital controlled signals along trigger comparator circuit output are low level, high-speed switch is closed
Disconnected, output voltage values when output signal is held off within a certain period of time are hold mode.When the present invention turns applied to A/D
When changing circuit, corresponding Analog-digital Converter can be carried out within the retention time.
Double preferred embodiments along triggering differential method peak detector according to the present invention, it is described double along trigger comparator
It include comparator core circuit and digital control signal generating circuit in circuit；The comparator core circuit is in open loop shape
The operational amplifier of state, when the output signal of differential circuit reaches zero-point voltage or reference voltage, operational amplifier output electricity
Pressure is high level, and when the output signal of differential circuit is lower than zero-point voltage or reference voltage, op-amp output voltage is
Low level；The output signal of operational amplifier is converted into digital level by digital controlled signal generation circuit.
Since in practical work process, op-amp output voltage is limited by operational amplifier open-loop gain, no
Supply voltage or ground level can be reached, it is therefore desirable to which digital controlled signal generation circuit is converted, and output signal is amplified to
Mains voltage level, so that the square wave control signal of standard is obtained, for controlling the switching of sampling hold circuit.
Double preferred embodiments along triggering differential method peak detector according to the present invention, comparator core circuit include
PMOS tube MP1~MP13 and NMOS tube MN1~MN10；PMOS tube MP1 grid and drain electrode connection, are current input terminal, the source of MP1
Pole connects power supply；The grid of PMOS tube MP1, MP2, MP3 are connected with each other, and the source electrode of MP2, MP3 connect power supply；PMOS tube MP4, MP5
Grid grade is connected with each other, and the grid of PMOS tube MP5 is connected with drain electrode, and the source level of PMOS tube MP4, MP5 connects power supply；PMOS tube MP6,
MP7 constitutes input stage, and the grid of MP6 connects input anode, and the grid of MP7 connects input negative terminal, and the source level of PMOS tube MP6, MP7 connects
The drain electrode of MP3；The drain of MP7 connects the drain electrode of MN13；The grid of PMOS tube MP8 and drain electrode are connected with each other, and the source electrode of MP8 meets MP9
Drain electrode, the grid of PMOS tube MP8, MP9 is connected with each other, and the source electrode of MP9 connects power supply；The grid of PMOS tube MP10, MP11 is mutual
Connection, the source electrode of MP10 connect the drain electrode of MP11, and the source electrode of MP11 connects power supply；The grid of PMOS tube MP12, MP13 is connected with each other,
The source electrode of MP12 connects the drain electrode of MP13, and the source electrode of MP13 connects power supply, and the drain electrode of MP12 connects the source electrode of MP10；The grid of NMOS tube MN1
Pole is connected with drain electrode, and is connected to the drain electrode of PMOS tube MP2, and the grid of NMOS tube MN1, MN2 is connected with each other, NMOS tube MN2's
Drain electrode is connected to the source electrode of NMOS tube MN7, MN8, the source electrode ground connection of NMOS tube MN1, MN2；The grid of NMOS tube MN3, MN4 is mutual
Connection, the grid grade of NMOS tube MN3 and drain electrode are connected with each other, and are connected to the drain electrode of PMOS tube MP4 and MP6, the source of NMOS tube MN4
Pole ground connection；The grid of NMOS tube MN5, MN6 is connected with each other, and the drain electrode of NMOS tube MN5 is connected to the drain electrode of PMOS tube MP10, NMOS
The source electrode of pipe MN6 is grounded；The grid of NMOS tube MN13, MN14 is connected with each other, and the grid of NMOS tube MN13 and drain electrode are connected with each other,
And it is connected to the drain electrode of PMOS tube MP7, the source electrode ground connection of NMOS tube MN6；NMOS tube MN7, MN8 constitutes input stage, the grid of MN7
Input negative terminal is connect, the grid of MN8 connects input anode, and the drain electrode of MN7 connects the drain electrode of PMOS tube MP5, and the drain electrode of MN8 connects PMOS tube
The drain electrode of MP8 and the drain electrode of NMOS tube MN14；The source electrode of NMOS tube MN13, MN14 is grounded；The grid phase of NMOS tube MN9, MN10
It connects, and is connected to the grid of PMOS tube MP12 and MP13, the source electrode of NMOS tube MN9 is connected to the drain electrode of MN10, MN10's
Source electrode ground connection.
Double preferred embodiments along triggering differential method peak detector according to the present invention, the digital controlled signal produce
Raw circuit includes sign-changing amplifier and output buffer；Sign-changing amplifier is by PMOS tube MP14, NMOS tube MN11 and resistance R1 structure
At output buffer is made of NMOS tube MN12 and PMOS tube MP15；PMOS tube MP14 is mutually interconnected with the grid of NMOS tube MN11
It connects, and is connected to comparator core circuit；The drain electrode of PMOS tube MP14 is connected with the drain electrode of NMOS tube MN11, and is connected to resistance
The one end R1, the source electrode of PMOS tube MP14 connect power supply, the source electrode ground connection of NMOS tube MN11, another termination PMOS tube MP14 of resistance R1 with
The grid of NMOS tube MN11；The drain electrode of PMOS tube MP15 is connected with the drain electrode of NMOS tube MN12, and the source electrode of PMOS tube MP15 connects electricity
Source, the source electrode ground connection of NMOS tube MN12, the drain electrode of PMOS tube MP15 is connected with the grid of NMOS tube MN12, and is connected to PMOS tube
The drain electrode of MP14 and the drain electrode of NMOS tube MN11.
Second technical solution of the invention is, a kind of to utilize the differential method and double sides that signal peak detection is carried out along triggering
Method, its main feature is that:
Be arranged differential method signal peak detector, including differential circuit, it is double along trigger comparator circuit and sampling keep electricity
Road；
The differential circuit is used to carry out differential transform processing to input signal, obtains the differential transform knot of input signal
Fruit, and when input signal is in peak value or valley, obtained differential transform output signal is exactly in zero point or reference voltage；
Processing is compared convenient for comparator；
Double output signals that differential circuit is received along trigger comparator circuit, by itself and zero-point voltage or reference voltage
It is compared, it is described double along trigger comparator circuit when the output signal of differential circuit reaches zero-point voltage or reference voltage
High level digital signal is exported, high-speed switch is connected, when the output signal of differential circuit is lower than zero-point voltage or reference voltage
When, it is described double along trigger comparator circuit output low level digital signal, disconnect high-speed switch；
The sampling hold circuit is for sampling input signal and being kept to operate；When high-speed switch conducting, institute
The output signal for stating sampling hold circuit follows input signal to change, and is sample states；When high-speed switch shutdown, the sampling
The output voltage values when output signal of holding circuit is held off are hold mode.
Preferred embodiment according to the present invention using the differential method and double methods for carrying out signal peak detection along triggering,
The sampling hold circuit includes two-stage emitter follower, high-speed switch and holding capacitor；
First order emitter follower and differential circuit receive input signal simultaneously, and output follows input signal, the second level
The output of emitter follower is final peak detection result output；High-speed switch is connected to the defeated of first order emitter follower
Out between the input of second level emitter follower, and the input terminal of second level emitter follower is grounded by holding capacitor；
When high-speed switch conducting, the output signal of first order emitter follower charges to holding capacitor, when high-speed switch disconnects, protects
It holds capacitor to discharge by second level emitter follower, the on-off of high-speed switching circuit is by double along the double of trigger comparator circuit output
Along triggering digital controlled signal control.
Double beneficial effects along triggering differential method peak detector and peak-value detection method of the present invention are: the present invention
Differential transform is carried out to input signal by using differential circuit, realizes the high-precision judgement to input signal peak value, and lead to
Double edge triggering digital controlled signals control sampling hold circuits are crossed, Self-resetting mechanism is introduced, is not required to additional reset unit and answers
Position logic；The present invention compared with traditional diode-type latches peak detector, have working frequency is high, detection accuracy is high, from
The advantages that reset, realizes the high-precision peak detection of high-frequency, can be widely used in various sophisticated signal sampling systems.
Detailed description of the invention
Fig. 1 is double along triggering differential method signal peak detector concept block diagram.
Fig. 2 is the circuit diagram of high-speed switching circuit 5.
Fig. 3 is double circuit diagrams along trigger comparator circuit 2.
Fig. 4 is the implementation result figure of differential circuit 1.
Fig. 5 is double along triggering differential method peak detector realization effect picture.
Specific embodiment
It is a kind of double along triggering differential method signal peak detectors referring to Fig. 1 including differential circuit 1, double along trigger comparator
Circuit 2 and sampling hold circuit 3；Wherein:
The differential circuit 1 is used to carry out differential transform processing to input signal, obtains the differential transform knot of input signal
Fruit, and when input signal is in peak value or valley, obtained differential transform output signal is exactly in zero point or reference voltage；
Double output signals that differential circuit 1 is received along trigger comparator circuit 2, by it with zero-point voltage or with reference to electricity
Pressure is compared, and exports double digital controlled signals along triggering according to comparison result, and control sampling hold circuit 3 is sampled
Or keep operation；
The sampling hold circuit 3 includes two-stage emitter follower, high-speed switching circuit 5 and holding capacitor C4；The first order
Emitter follower 4 and differential circuit 1 receive input signal simultaneously, and output follows input signal, second level emitter follower
Output is final peak detection result output；High-speed switching circuit 5 is connected to the output of first order emitter follower 4 and the
Between the input of second level emitter follower 6, and the input terminal of second level emitter follower is grounded by holding capacitor, is opened at a high speed
The on-off on powered-down road 5 is controlled by double along trigger comparator circuit 2；When high-speed switching circuit 5 is connected, first order emitter follower
4 output signal to holding capacitor C4 charge, when high-speed switching circuit 5 disconnect when, holding capacitor C4 by second level emitter-base bandgap grading with
It discharges with device 6；The control signal of high-speed switch 5 is provided by double along trigger comparator circuit 2；Two-stage emitter follower is all made of phase
The unit gain follow-up amplifier that output end and negative input end are connected to form by same operational amplifier is constituted.
In a particular embodiment, the differential circuit 1 includes operational amplifier 10, capacitor C1, C2 and resistance R1；Capacitor C1
For ac coupling capacitor, a termination input signal, the input negative terminal of another termination operational amplifier 10；Resistance R1 is bridging electricity
Resistance, the input negative terminal of a termination operational amplifier 10, the output end of another termination operational amplifier 10；Capacitor C2 is bridging electricity
Hold, the input negative terminal of a termination operational amplifier, the output end of another termination operational amplifier.The positive termination of operational amplifier 10
Receive the reference voltage for connecing the generation of reference circuit 7.The differential circuit 1 can carry out differential transform to input signal, work as input signal
When in peak value or valley, obtained differential transform output signal is exactly in reference voltage value.
The working principle of differential circuit is: when input signal is in rising edge, level is height by low jump, is equivalent to
Suddenly switched on high level in the circuit R1C1, since the voltage at the both ends capacitor C1 cannot be mutated, i.e., the voltage on capacitor needs
It is just gradually increasing by a charging process, then capacitor C1 both end voltage is 0 at this time, and input voltage fully falls in bridging resistance R1
On, output voltage reaches highest at this time.Hereafter input signal starts to charge to capacitor C1, and capacitor C1 both end voltage is exponentially
Rise, and resistance R1 both end voltage exponentially declines, when input signal reaches peak value, output voltage drop is as low as zero.When
When input signal is in failing edge, level by height jump be it is low, be equivalent to and removed high level suddenly in the circuit R1C1, equally
Since the voltage at the both ends capacitor C1 cannot be mutated, need to discharge by bridging resistance R1, therefore capacitor C1 both end voltage
The both ends resistance R1 are fallen in, and since discharge current and charging current are reversed, so output voltage reaches minimum.When input signal reaches
When to valley, capacitor C1 electric discharge closes to an end, so that output voltage gos up to zero.In conclusion when input signal reaches
When peak value or valley, output voltage is zero, to realize the effect for carrying out differential transform to input signal.In practical electricity
In the application of road, in order not to joined reference voltage value using the input anode of negative supply, operational amplifier, so that differential becomes
Zero in changing is converted to reference voltage value, is compared convenient for comparator.
As shown in Figure 4, horizontal axis is the time to differential circuit implementation result, and the longitudinal axis is voltage.It include two curves, input in figure
Signal curve and differential transform curve of output, as seen from Figure 4, when input signal reaches peak value, differential transform output letter
Number reach reference voltage value；When input signal reaches valley, differential transform output signal reaches reference voltage value.Fig. 4 shows:
Differential transform output may be implemented in the differential circuit.
The present invention using high-gain operational amplifier constitute differential circuit, it is double along trigger comparator and sampling keep electricity
Road, while high-speed switch is constituted using NMOS tube, as long as design forms the operational amplifier of high frequency high-bandwidth high-gain, so that it may
It realizes high-frequency work characteristic, breaches the working frequency limitation of conventional diode structure.
The sampling hold circuit is by two-stage emitter follower 4,6, high-speed switching circuit 5 and holding capacitor C4, exchange coupling
It closes capacitor C3 to constitute, high-speed switching circuit 5 is connected to output and the second level emitter follower 6 of first order emitter follower 4
Between input, two-stage emitter follower is by identical operational amplifier, and the list that output end and negative input end are connected to form
Position gain follow-up amplifier is constituted；One end of capacitor C3 receives input signal, the input of another termination first order emitter follower 4
Anode；The input terminal of second level emitter follower also passes through holding capacitor C4 and is grounded, and the control signal of high-speed switching circuit 5 is by double
It is provided along trigger comparator circuit 2；The output end of second level emitter follower is final peak detection result output.
The working principle of sampling hold circuit is: when being in sample states, the output signal of sampling hold circuit is followed
Input signal changes and changes, and when being in hold mode, the output signal of sampling hold circuit, which remains, is connected to holding order
Moment input signal level values.When circuit is in sample states, high-speed switching circuit 5 is connected, and at this moment holding capacitor charges
C4, if capacitance very little, capacitor C4 can complete charge and discharge in a short period of time, and at this moment output end output signal follows defeated
Enter signal intensity and changes；When circuit is in hold mode, high-speed switching circuit 5 disconnect, at this moment due to second level emitter-base bandgap grading with
Input terminal with device is in high-impedance state, and capacitor C4 electric discharge is slow, so output signal remains essentially as disconnecting the signal electricity of moment
Level values.
In a particular embodiment, the operational amplifier of the operational amplifier and emitter follower that constitute differential circuit can wrap
Enlarged structure containing two-stage, the open-loop gain for effectively increasing operational amplifier is amplified at the two poles of the earth, convenient for forming the differential of high-frequency work
Circuit and emitter follower circuit, while cascode structure is used, it can make circuit work under lower operating voltage.
Referring to fig. 2, high-speed switching circuit 5 is mainly made of NMOS tube 5MN1 and resistance 5R1,5R2, the leakage of NMOS tube 5MN1
Pole is as input terminal, and the source electrode of NMOS tube 5MN1 is as output end, one end of the grid connection resistance 5R1 of NMOS tube 5MN1, electricity
The other end of 5R1 is hindered as control signal input；One end of resistance 5R2 is connected to the substrate of NMOS tube 5MN1, and the other end connects
It is connected to ground.
The working principle of high-speed switching circuit 5 is that, when controlling signal is high level, the gate source voltage of NMOS tube 5MN1 is poor
Value is greater than its threshold voltage, NMOS tube 5MN1 conducting switchs in the conductive state.When controlling signal is low level, NMOS
The gate source voltage difference of pipe 5MN1 is less than its threshold voltage, and NMOS tube 5MN1 cut-off, i.e. switch are in an off state.Resistance 5R1,
The grid and source-drain electrode that 5R2 can effectively reduce NMOS tube 5MN1 reduce signal when high-frequency operation to the parasitic capacitance on ground
Loss, to improve Peak detection accuracy.
It is double to include comparator core circuit 8 and digital control signal generating circuit 9 along trigger comparator circuit referring to Fig. 3；
The comparator core circuit 8 is the operational amplifier in open loop situations, when the output signal of differential circuit 1 reaches zero point electricity
Pressure or when reference voltage, op-amp output voltage is high level, when differential circuit 1 output signal lower than zero-point voltage or
When reference voltage, op-amp output voltage is low level；Digital controlled signal generation circuit 9 is by the output of operational amplifier
Signal is converted into digital level.
In a particular embodiment, the comparator core circuit 8 include PMOS tube MP1~MP13 and NMOS tube MN1~
MN10；PMOS tube MP1 grid and drain electrode connection, are current input terminal, the source electrode of MP1 connects power supply；PMOS tube MP1, MP2, MP3's
Grid is connected with each other, and the source electrode of MP2, MP3 connect power supply；The grid grade of PMOS tube MP4, MP5 is connected with each other, the grid of PMOS tube MP5
It is connected with drain electrode, the source level of PMOS tube MP4, MP5 connects power supply；PMOS tube MP6, MP7 constitutes input stage, and the grid of MP6 connects input
Anode, the grid of MP7 connect input negative terminal, and the source level of PMOS tube MP6, MP7 connects the drain electrode of MP3；The drain of MP7 connects the leakage of MN13
Pole；The grid of PMOS tube MP8 and drain electrode are connected with each other, and the source electrode of MP8 connects the drain electrode of MP9, and the grid of PMOS tube MP8, MP9 is mutual
Connection, the source electrode of MP9 connect power supply；The grid of PMOS tube MP10, MP11 is connected with each other, and the source electrode of MP10 connects the drain electrode of MP11,
The source electrode of MP11 connects power supply；The grid of PMOS tube MP12, MP13 is connected with each other, and the source electrode of MP12 connects the drain electrode of MP13, MP13's
Source electrode connects power supply, and the drain electrode of MP12 connects the source electrode of MP10；The grid of NMOS tube MN1 is connected with drain electrode, and is connected to PMOS tube MP2
Drain electrode, the grid of NMOS tube MN1, MN2 is connected with each other, and the drain electrode of NMOS tube MN2 is connected to the source electrode of NMOS tube MN7, MN8,
The source electrode of NMOS tube MN1, MN2 is grounded；The grid of NMOS tube MN3, MN4 is connected with each other, and the grid grade of NMOS tube MN3 and drain electrode are mutual
Connection, and it is connected to the drain electrode of PMOS tube MP4 and MP6, the source electrode ground connection of NMOS tube MN4；The grid of NMOS tube MN5, MN6 is mutual
Connection, the drain electrode of NMOS tube MN5 are connected to the drain electrode of PMOS tube MP10, the source electrode ground connection of NMOS tube MN6；NMOS tube MN13,
The grid of MN14 is connected with each other, and the grid of NMOS tube MN13 and drain electrode are connected with each other, and are connected to the drain electrode of PMOS tube MP7,
The source electrode of NMOS tube MN6 is grounded；NMOS tube MN7, MN8 constitutes input stage, and the grid of MN7 connects input negative terminal, and the grid of MN8 connects defeated
Enter anode, the drain electrode of MN7 connects the drain electrode of PMOS tube MP5, and the drain electrode of MN8 connects the drain electrode of PMOS tube MP8 and the leakage of NMOS tube MN14
Pole；The source electrode of NMOS tube MN13, MN14 is grounded；The grid of NMOS tube MN9, MN10 is connected with each other, and is connected to PMOS tube MP12
And the grid of MP13, the source electrode of NMOS tube MN9 are connected to the drain electrode of MN10, the source electrode ground connection of MN10.
The digital controlled signal generation circuit 9 includes sign-changing amplifier and output buffer；Sign-changing amplifier is by PMOS
Pipe MP14, NMOS tube MN11 and resistance R1 are constituted, and output buffer is made of NMOS tube MN12 and PMOS tube MP15；PMOS tube
The grid of MP14 and NMOS tube MN11 are connected with each other, and are connected to comparator core circuit 8, i.e., PMOS tube MP12, MP13 and
The grid of NMOS tube MN9, MN10；The drain electrode of PMOS tube MP14 is connected with the drain electrode of NMOS tube MN11, and is connected to resistance R1 mono-
End, the source electrode of PMOS tube MP14 meet power supply, the source electrode ground connection of NMOS tube MN11, another termination PMOS tube MP14 and NMOS of resistance R1
The grid of pipe MN11；The drain electrode of PMOS tube MP15 is connected with the drain electrode of NMOS tube MN12, and the source electrode of PMOS tube MP15 connects power supply,
The source electrode of NMOS tube MN12 is grounded, and the drain electrode of PMOS tube MP15 is connected with the grid of NMOS tube MN12, and is connected to PMOS tube
The drain electrode of MP14 and the drain electrode of NMOS tube MN11.
Due to inverting amplifier gain with higher and voltage margin, output signal can be amplified to supply voltage electricity
It is flat, so that the square wave control signal of standard is obtained, for controlling the switching of sampling hold circuit.
Double working principles along trigger comparator circuit 2 are: double be in along trigger comparator circuit comprising one is opened
The operational amplifier of ring status and one for comparison result to be converted to the digital controlled signal generation circuit of digital level, when
When the output signal of differential circuit 1 reaches reference voltage value, output voltage is height, when the output signal of differential circuit 1 is lower than ginseng
When examining voltage value, output voltage be it is low,
A kind of to utilize the differential method and double methods for carrying out signal peak detection along triggering, including setting differential method signal peak
It is worth detector, including differential circuit 1, double along trigger comparator circuit 2 and sampling hold circuit 3；
The differential circuit 1 is used to carry out differential transform processing to input signal, obtains the differential transform knot of input signal
Fruit, and when input signal is in peak value or valley, obtained differential transform output signal is exactly in zero point or reference voltage；
Processing is compared convenient for comparator；
Double output signals that differential circuit 1 is received along trigger comparator circuit 2, by it with zero-point voltage or with reference to electricity
Pressure is compared, described double along trigger comparator electricity when the output signal of differential circuit 1 reaches zero-point voltage or reference voltage
Road 2 exports high level digital signal, and high-speed switch 5 is connected, when the output signal of differential circuit 1 is lower than zero-point voltage or reference
It is described double along the output low level digital signal of trigger comparator circuit 2 when voltage, disconnect high-speed switching circuit 5；
The sampling hold circuit 3 is for sampling input signal and being kept to operate；When high-speed switch conducting, institute
The output signal for stating sampling hold circuit 3 follows input signal to change, and is sample states；It is described to adopt when high-speed switch shutdown
The output voltage values when output signal of sample holding circuit 3 is held off are hold mode.
In a particular embodiment, the sampling hold circuit 3 includes two-stage emitter follower, high-speed switch 5 and keeps electric
Hold C4；
First order emitter follower 4 and differential circuit 1 receive input signal simultaneously, export and follow input signal, and second
The output of grade emitter follower is final peak detection result output；High-speed switching circuit 5 be connected to first order emitter-base bandgap grading with
With between the output of device 4 and the input of second level emitter follower 6, and the input terminal of second level emitter follower passes through holding
Capacitor C4 ground connection；When high-speed switching circuit 5 is connected, the output signal of first order emitter follower 4 charges to holding capacitor C4,
When high-speed switching circuit 5 disconnects, holding capacitor C4 is discharged by second level emitter follower 6, the on-off of high-speed switching circuit 5
By double double edge triggering digital controlled signal controls exported along trigger comparator circuit 2.
As shown in Figure 5, horizontal axis is the time to double edge touching method differential method peak detection circuit implementation results, and the longitudinal axis is voltage.Figure
In include three curves, input signal curve, it is double along triggering digital controlled signal curve, output signal curve, can be seen by Fig. 5
Out, when input signal is not up to peak value, double along digital controlled signal is triggered as high level, output signal follows input signal；
When input signal reaches peak value, double jumped along triggering digital controlled signal by high level is low level, and output signal keeps peak
Threshold voltage is constant, the retention time >=0.5* input signal cycle, can carry out data conversion to output signal at this time；Then double edges
It is high level that digital controlled signal, which is triggered, by low level jump, completes to automatically reset, output signal continues to follow input signal straight
Peak value to next period arrives.Fig. 5 shows: peak may be implemented in double edge touching method differential method peak detection circuits proposed by the present invention
Value detection output.
Result of implementation above shows: one kind of the invention it is double along touching method differential method peak detectors have high-frequency work,
The features such as high-precision detects.The technology of the present invention can be applied to the fields such as high-speed AD/DA, complex parameters acquisition system.
Claims (4)
1. a kind of double along triggering differential method signal peak detectors, including it is differential circuit (1), double along trigger comparator circuit (2)
And sampling hold circuit (3)；It is characterized by:
The differential circuit (1) be used for input signal carry out differential transform processing, obtain the differential transform of input signal as a result,
And when input signal is in peak value or valley, obtained differential transform output signal is exactly in zero point or reference voltage；
Double output signals that differential circuit (1) is received along trigger comparator circuit (2), by it with zero-point voltage or with reference to electricity
Pressure is compared, and exports double edge triggering digital controlled signals according to comparison result, and control sampling hold circuit (3) is sampled
Or keep operation；
The sampling hold circuit (3) includes two-stage emitter follower, high-speed switching circuit (5) and holding capacitor (C4)；First
Grade emitter follower (4) and differential circuit (1) receives input signal simultaneously；High-speed switching circuit (5) is connected to first order emitter-base bandgap grading
Between the output of follower (4) and the input of second level emitter follower (6), and the input terminal of second level emitter follower is logical
Holding capacitor ground connection is crossed, the on-off of high-speed switching circuit (5) is by double along the double along triggering number of trigger comparator circuit (2) output
Control signal control；
Described pair includes comparator core circuit (8) and digital control signal generating circuit along trigger comparator circuit (2)
(9)；The comparator core circuit (8) is the operational amplifier in open loop situations, when the output signal of differential circuit (1) reaches
When to zero-point voltage or reference voltage, op-amp output voltage is high level, when the output signal of differential circuit (1) is lower than
When zero-point voltage or reference voltage, op-amp output voltage is low level；Digital controlled signal generation circuit puts operation
The output signal of big device is converted into digital level.
2. according to claim 1 double along triggering differential method signal peak detector, it is characterised in that: comparator core electricity
Road (8) includes PMOS tube MP1~MP13 and NMOS tube MN1~MN10；PMOS tube MP1 grid and drain electrode connection, input for electric current
End, the source electrode of MP1 connect power supply；The grid of PMOS tube MP1, MP2, MP3 are connected with each other, and the source electrode of MP2, MP3 connect power supply；PMOS tube
The grid grade of MP4, MP5 are connected with each other, and the grid of PMOS tube MP5 is connected with drain electrode, and the source level of PMOS tube MP4, MP5 connects power supply；
PMOS tube MP6, MP7 constitutes input stage, and the grid of MP6 connects input anode, and the grid of MP7 connects input negative terminal, PMOS tube MP6, MP7
Source level connect the drain electrode of MP3；The drain of MP7 connects the drain electrode of MN13；The grid of PMOS tube MP8 and drain electrode are connected with each other, the source of MP8
Pole connects the drain electrode of MP9, and the grid of PMOS tube MP8, MP9 is connected with each other, and the source electrode of MP9 connects power supply；The grid of PMOS tube MP10, MP11
Pole is connected with each other, and the source electrode of MP10 connects the drain electrode of MP11, and the source electrode of MP11 connects power supply；The grid of PMOS tube MP12, MP13 is mutual
Connection, the source electrode of MP12 connect the drain electrode of MP13, and the source electrode of MP13 connects power supply, and the drain electrode of MP12 connects the source electrode of MP10；NMOS tube MN1
Grid be connected with drain electrode, and be connected to the drain electrode of PMOS tube MP2, the grid interconnection of NMOS tube MN1, MN2, NMOS tube
The drain electrode of MN2 is connected to the source electrode of NMOS tube MN7, MN8, the source electrode ground connection of NMOS tube MN1, MN2；The grid of NMOS tube MN3, MN4
Pole is connected with each other, and the grid grade of NMOS tube MN3 and drain electrode are connected with each other, and are connected to the drain electrode of PMOS tube MP4 and MP6, NMOS tube
The source electrode of MN4 is grounded；The grid of NMOS tube MN5, MN6 is connected with each other, and the drain electrode of NMOS tube MN5 is connected to the leakage of PMOS tube MP10
Pole, the source electrode ground connection of NMOS tube MN6；The grid of NMOS tube MN13, MN14 is connected with each other, the grid and drain electrode phase of NMOS tube MN13
It connects, and is connected to the drain electrode of PMOS tube MP7, the source electrode ground connection of NMOS tube MN6；NMOS tube MN7, MN8 constitutes input stage,
The grid of MN7 connects input negative terminal, and the grid of MN8 connects input anode, and the drain electrode of MN7 connects the drain electrode of PMOS tube MP5, the drain electrode of MN8
Connect the drain electrode of PMOS tube MP8 and the drain electrode of NMOS tube MN14；The source electrode of NMOS tube MN13, MN14 is grounded；NMOS tube MN9, MN10
Grid be connected with each other, and be connected to the grid of PMOS tube MP12 and MP13, the source electrode of NMOS tube MN9 is connected to the leakage of MN10
Pole, the source electrode ground connection of MN10.
3. according to claim 1 or 2 double along triggering differential method signal peak detector, it is characterised in that: the number
Controlling signal generating circuit (9) includes sign-changing amplifier and output buffer；Sign-changing amplifier is by PMOS tube MP14, NMOS tube
MN11 and resistance R1 is constituted, and output buffer is made of NMOS tube MN12 and PMOS tube MP15；PMOS tube MP14 and NMOS tube
The grid of MN11 is connected with each other, and is connected to comparator core circuit (8)；The drain electrode of PMOS tube MP14 and the leakage of NMOS tube MN11
Extremely it is connected, and is connected to the one end resistance R1, the source electrode of PMOS tube MP14 meets power supply, the source electrode ground connection of NMOS tube MN11, resistance R1
The grid of another termination PMOS tube MP14 and NMOS tube MN11；The drain electrode of PMOS tube MP15 is connected with the drain electrode of NMOS tube MN12,
The source electrode of PMOS tube MP15 connects power supply, the source electrode ground connection of NMOS tube MN12, the drain electrode of PMOS tube MP15 and the grid of NMOS tube MN12
Extremely it is connected, and is connected to the drain electrode of PMOS tube MP14 and the drain electrode of NMOS tube MN11.
4. a kind of utilize the differential method and double methods for carrying out signal peak detection along triggering, it is characterised in that:
Be arranged differential method signal peak detector, including differential circuit (1), it is double along trigger comparator circuit (2) and sampling keep
Circuit (3)；
The differential circuit (1) be used for input signal carry out differential transform processing, obtain the differential transform of input signal as a result,
And when input signal is in peak value or valley, obtained differential transform output signal is exactly in zero point or reference voltage；
Double output signals that differential circuit (1) is received along trigger comparator circuit (2), by it with zero-point voltage or with reference to electricity
Pressure is compared, described double along trigger comparator when the output signal of differential circuit (1) reaches zero-point voltage or reference voltage
Circuit (2) exports high level digital signal, and high-speed switching circuit (5) are connected, when the output signal of differential circuit (1) is lower than zero
It is described double along trigger comparator circuit (2) output low level digital signal when point voltage or reference voltage, make high-speed switching circuit
(5) it disconnects；
The sampling hold circuit (3) is for sampling input signal and being kept to operate；It is described when high-speed switch conducting
The output signal of sampling hold circuit (3) follows input signal to change, and is sample states；It is described to adopt when high-speed switch shutdown
The output voltage values when output signal of sample holding circuit (3) is held off are hold mode；
The sampling hold circuit (3) includes two-stage emitter follower, high-speed switch (5) and holding capacitor (C4)；
First order emitter follower (4) and differential circuit (1) receive input signal simultaneously, and high-speed switching circuit (5) is connected to the
Between the output of level-one emitter follower (4) and the input of second level emitter follower (6), and second level emitter follower
Input terminal is grounded by holding capacitor (C4)；When high-speed switching circuit (5) conducting, the output of first order emitter follower (4)
Signal charges to holding capacitor (C4), and when high-speed switching circuit (5) disconnect, holding capacitor (C4) passes through second level emitter following
Device (6) electric discharge；The on-off of high-speed switching circuit (5) is by double along the double digital control along triggering of trigger comparator circuit (2) output
Signal control.
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| CN109633245B (en) * | 2019-01-15 | 2020-12-01 | 电子科技大学 | Novel peak detection circuit |
| CN112881784B (en) * | 2019-11-29 | 2022-09-02 | 深圳市帝迈生物技术有限公司 | Peak detector and blood coagulation analyzer |
| CN111024761B (en) * | 2019-12-31 | 2022-07-26 | 中国计量大学 | Ignition energy measuring method based on high-voltage discharge peak detection |
| CN113419102B (en) * | 2021-06-26 | 2022-09-13 | 广州金升阳科技有限公司 | Wave crest detection circuit and application thereof |
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