CN105915207B - A kind of level shift circuit - Google Patents
A kind of level shift circuit Download PDFInfo
- Publication number
- CN105915207B CN105915207B CN201610218940.7A CN201610218940A CN105915207B CN 105915207 B CN105915207 B CN 105915207B CN 201610218940 A CN201610218940 A CN 201610218940A CN 105915207 B CN105915207 B CN 105915207B
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- pmos
- nmos tube
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
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Abstract
The invention belongs to electronic technology field, and in particular to a kind of level shift circuit.The level shift circuit of the present invention, including the first PMOS MP1, the second PMOS MP2, the 3rd PMOS MP3, the 4th PMOS MP4, the 5th PMOS MP5, the 6th PMOS MP6, the first NMOS tube MN1, the second NMOS tube MN2, the 3rd NMOS tube MN3, the 4th NMOS tube MN4, the 5th NMOS tube MN5, the 6th NMOS tube MN6, the first current source, the second current source and phase inverter.Beneficial effects of the present invention are, level displacement circuit of the invention is compared with stability is high, fireballing feature with current typical level displacement circuit.
Description
Technical field
The invention belongs to electronic technology field, and in particular to a kind of level shift circuit.
Background technology
It is to realize the conversion between varying level that level displacement circuit acts in the driving circuit, and control signal is electric from one kind
Mean longitude over level shift circuit is converted into another level controling signal.Level displacement circuit is a kind of important in the driving circuit
Circuit.At present it has been reported that level displacement circuit, can't in circuit structure cost, power consumption, stability, speed etc.
Take into account well, the problems such as example initial state is disorderly, speed is slow, power consumption is big.How to design and meet high stable state, quick level position
Shift circuit plays the role of important for the overall drive circuit of optimization.Typical level displacement circuit is as shown in Figure 1 at present.Substantially
Operation principle is：Vin inputs are a kind of level logic signal, and phase is formed in MN1, the signal of MN2 pipes by INV phase inverters
The opposite complementary logic level in position, control MN1, the switch of MN2 pipes, the latch structure formed with reference to MP1 and MP2, by output electricity
Vout1 is pressed, Vout2 exports corresponding low and high level respectively, by signal level from INV Power convert in the range of GND and VDD
Signal, realize the function of level shift.Resistance R in dotted line frame in figure, electric capacity C are in order that circuit has the initial state of determination and taken
Method, resistance and electric capacity can reach effect using any of which, but this quadrat method can be to the work(of level displacement circuit
Consumption produces considerable influence；Meanwhile the circuit, due to the influence of resistance or electric capacity, causes electricity when incoming level redirects
Road response speed is slower.
The content of the invention
The invention aims to solve above mentioned problem existing for typical level displacement circuit, it is proposed that new circuit
Structure, improve the performance of level displacement circuit.
The technical scheme is that：A kind of level shift circuit, including the first PMOS MP1, the second PMOS MP2,
3rd PMOS MP3, the 4th PMOS MP4, the 5th PMOS MP5, the 6th PMOS MP6, the first NMOS tube MN1, second
NMOS tube MN2, the 3rd NMOS tube MN3, the 4th NMOS tube MN4, the 5th NMOS tube MN5, the 6th NMOS tube MN6, the first current source,
Second current source and phase inverter；Wherein,
First PMOS MP1 source electrode connects power supply, and its grid meets the second PMOS MP2 drain electrode and the 5th PMOS MP5
Drain electrode；
Second PMOS MP2 source electrode connects power supply, and its grid meets the first PMOS MP1 drain electrode and the 3rd PMOS MP3
Drain electrode；
3rd PMOS MP3 source electrode connects power supply, and its grid connects the 4th PMOS MP4 drain electrode；
4th PMOS MP4 source electrode connects power supply, its grid and drain interconnection；
5th PMOS MP5 source electrode connects power supply, and its grid connects the 6th PMOS MP6 drain electrode；
6th PMOS MP6 source electrode connects power supply, its grid and drain interconnection；
First NMOS tube MN1 drain electrode connect the first PMOS MP1 drain electrode and the 3rd PMOS MP3 drain electrode, first
NMOS tube MN1 grid connects external input signal, the first NMOS tube MN1 source ground；
Second NMOS tube MN2 drain electrode connect the second PMOS MP2 drain electrode and the 5th PMOS MP5 drain electrode, second
NMOS tube MN2 grid connects the output end of phase inverter；Second NMOS tube MN2 source ground；
The input termination external input signal of phase inverter；
3rd NMOS tube MN3 drain electrode connects the 6th NMOS tube MN6 source electrode, and the 3rd NMOS tube MN3 grid connects phase inverter
Output end, the 3rd NMOS tube MN3 source ground；
4th NMOS tube MN4 drain electrode connects the 5th NMOS tube MN5 source electrode, and the 4th NMOS tube MN4 grid connects outside defeated
Enter signal, the 4th NMOS tube MN4 source ground；
5th NMOS tube MN5 drain electrode connects the 6th PMOS MP6 drain electrode, and the 5th NMOS tube MN5 grid connects first
PMOS MP1 drain electrode and the 3rd PMOS MP3 drain electrode；
6th NMOS tube MN6 drain electrode connects the 4th PMOS MP4 drain electrode, and the 6th NMOS tube MN6 grid connects second
PMOS MP2 drain electrode and the 5th PMOS MP5 drain electrode；
One the first NMOS tube MN1 of termination of the first current source drain electrode, the other end ground connection of the first current source；
One the 4th NMOS tube MN4 of termination of the second current source drain electrode, the other end ground connection of the second current source；
The first output that second PMOS MP2 drains with the tie point of the 5th PMOS MP5 drain electrodes for level shift circuit
The tie point of end, the first PMOS MP1 drain electrodes and the 3rd PMOS MP3 drain electrodes is the second output end that level thinks circuit.
Beneficial effects of the present invention are that level displacement circuit of the invention has compared with current typical level displacement circuit
Have that stability is high, fireballing feature.
Brief description of the drawings
Fig. 1 is traditional level displacement circuit figure；
Fig. 2 be set forth herein the quick level displacement circuit figure of high stable state；
Fig. 3 be set forth herein the quick saltus step of level displacement circuit incoming level 0 of high stable state be 1 when first stage signal
Figure；
Fig. 4 be set forth herein the quick saltus step of level displacement circuit incoming level 0 of high stable state be 1 when second stage signal
Figure；
Fig. 5 be set forth herein the quick saltus step of level displacement circuit incoming level 0 of high stable state be 1 when phase III signal
Figure；
Fig. 6 be set forth herein the quick saltus step of level displacement circuit incoming level 1 of high stable state be 0 when first stage signal
Figure；
Fig. 7 be set forth herein the quick saltus step of level displacement circuit incoming level 1 of high stable state be 0 when second stage signal
Figure；
Fig. 8 be set forth herein the quick saltus step of level displacement circuit incoming level 1 of high stable state be 0 when phase III signal
Figure.
Embodiment
Below in conjunction with the accompanying drawings, technical scheme is described in detail：
Current source I effect is to determine the initial state of circuit in circuit, such as：On circuit during electricity, Vin state is not
Surely MN1, MN2, MN3, MN4 pipe may be caused all to turn off, if without current source I presence, cause output Vout1,
Vout2 is nondeterministic statement, causes output state disorderly, at this moment current source I2 is filled by MP5, MP6 current mirror to Vout1 nodes
Electricity draws high Vout1, and current source I1 is dragged down Vout2 by discharging node Vout2, determines circuit original state.
The framework that the characteristics of quick in the present invention is strengthened by transient state is realized.Circuit during lower surface analysis input Vin saltus steps
Working condition.When Vin from 0 redirect for 1 when：When Vin is 0, Vout1 0, Vout2 1；When Vin saltus steps are 1 so that MN1,
MN4 pipes are opened, the shut-off of MN3, MN2 pipe；First stage be Vout2 (shown in Fig. 3) from high level VDD drop to VDD-VTHP when,
MP2 pipes turn off, and MN5 pipes are in opening, and the electric current of such this branch road of MN5, MP6 passes through MP5, MP6 (in Fig. 3 shown in I3)
Current mirror is charged to node Vout1, draws high Vout1 current potential, and Vout2 node potentials are opened due to MN1 pipes to be discharged
And drag down；When second stage is that Vout2 drops to less than VDD-VTHP and is more than VDSN4+VTHN (shown in Fig. 4), during this
MP2, MN5 pipe are switched on, and the electric current (in Fig. 4 shown in I4) for flowing through MP2 is right together with the electric current (in Fig. 4 shown in I3) for flowing through MN5
Node Vout1 is charged, and draws high Vout1 current potential；At the same time, it can reduce when Vout1 current potentials are drawn high and flow through MP1 pipes
Electric current (in Fig. 4 shown in I5), so as to avoid because MN1 pull-down capabilities not enough prevent Vout2 voltages from situation about declining, in transient state
When there is high stability；Moreover, Vout2 voltages decline can cause the electric current (in Fig. 4 shown in I4) for flowing through MP2 increase in turn,
Acceleration rises Vout1, forms positive feedback process, and first and second stage was the mechanism of this circuit realiration transient state enhancing, accelerated to make
Vout1 is drawn high, and Vout2 is dragged down；When phase III is that Vout2 drops to less than VDSN4+VTHN (shown in Fig. 5), the shut-off of MN5 pipes,
The electric current (in Fig. 5 shown in I4) for now only flowing through MP2 is charged to node Vout1, and Vout1 node potentials are drawn high to VDD, process
In when Vout1 is more than VDD-VTHP, the shut-off of MP1 pipes, Vout2 node voltages drop to 0 by MN1 tube discharges.
When Vin from 1 redirect for 0 when：When Vin is 1, Vout1 1, Vout2 0；When Vin is 0 so that MN2, MN3 pipe are opened
Open, the shut-off of MN1, MN4 pipe；First stage be Vout1 (shown in Fig. 6) from high level VDD drop to VDD-VTHP when, MP1 pipes close
Disconnected, MN6 pipes are in opening, and at this moment the electric current (in Fig. 6 shown in I6) of this branch road of MN3, MN6, MP4 passes through MP3, MP4 electricity
Electric current comparison is carried out after stream mirror mirror image with current source I1, and because I1 value very littles, node Vout2 current potentials are drawn high, node Vout1 electricity
Position is as flowing through MN2 tube currents (shown in I9 in Fig. 6) and flowing through MP2 tube currents (shown in I8 in Fig. 6) and current mirror MP5, MP6 mirror image
Electric current I2 sums are compared, and drag down Vout1 current potentials；Second stage be (shown in Fig. 7) Vout1 drop to less than VDD-VTHP and
During more than VDSN4+VTHN；MN6, MP1 pipe are switched on during this, are flowed through the electric current (in Fig. 7 shown in I6) of MP3 pipes and are flowed through MP1
After electric current (in Fig. 7 shown in the I7) summation of pipe compared with electric current I1, Vout2 current potential is drawn high；At the same time, in Vout2
Current potential can reduce the electric current (in Fig. 7 shown in I8) for flowing through MP2 pipes when drawing high, so as to avoid because MN2 pull-down capabilities not enough make
The situation that Vout1 voltages can not decline, there is high stability in transient state；It can cause to flow in turn moreover, Vout1 voltages decline
MP1 electric current (in Fig. 7 shown in I7) increase is crossed, acceleration rises Vout2, forms positive feedback process, first and second stage was this electricity
The mechanism of transient state enhancing is realized on road, and acceleration draws high Vout2, and Vout1 is dragged down；Phase III is that Vout1 drops to (shown in Fig. 8)
During less than VDSN3+VTHN, the shut-off of MN6 pipes, MP1 electric current (in Fig. 8 shown in I7) is now only flowed through compared with electric current I1, this
When MP1 pipes gate source voltage it is very big, I1 again draw high to being approximately VDD by very little, such Vout2 node potentials, during work as Vout2
During more than VDD-VTHP, the shut-off of MP2 pipes, Vout1 node voltages are as MN2 tube currents (shown in I9 in Fig. 8) and MP5, MP6 current mirror
Image current I2 is compared, and because MN2 gate source voltages are very big, I2 and very little, it is approximately 0 that node Vout1 current potentials, which drag down,.More than
Analysis is carried out by the saltus step to Vin it can be seen that output redirects speed quickly, and the steady of circuit is also ensure that in transient state
It is qualitative.
Beneficial effects of the present invention are to devise a kind of quick level displacement circuit of high stable state, in circuit initial state and transient state
In keep high stable state, saltus step speed is strengthened quickly by transient state in level saltus step, there is high stable state, quickly spy
Point.
Claims (1)
1. a kind of level shift circuit, including the first PMOS MP1, the second PMOS MP2, the 3rd PMOS MP3, the 4th PMOS
Pipe MP4, the 5th PMOS MP5, the 6th PMOS MP6, the first NMOS tube MN1, the second NMOS tube MN2, the 3rd NMOS tube MN3,
4th NMOS tube MN4, the 5th NMOS tube MN5, the 6th NMOS tube MN6, the first current source, the second current source and phase inverter；Wherein,
First PMOS MP1 source electrode connects power supply, and its grid connects the second PMOS MP2 drain electrode and the 5th PMOS MP5 leakage
Pole；
Second PMOS MP2 source electrode connects power supply, and its grid connects the first PMOS MP1 drain electrode and the 3rd PMOS MP3 leakage
Pole；
3rd PMOS MP3 source electrode connects power supply, and its grid connects the 4th PMOS MP4 drain electrode；
4th PMOS MP4 source electrode connects power supply, its grid and drain interconnection；
5th PMOS MP5 source electrode connects power supply, and its grid connects the 6th PMOS MP6 drain electrode；
6th PMOS MP6 source electrode connects power supply, its grid and drain interconnection；
First NMOS tube MN1 drain electrode connects the first PMOS MP1 drain electrode and the 3rd PMOS MP3 drain electrode, the first NMOS tube
MN1 grid connects external input signal, the first NMOS tube MN1 source ground；
Second NMOS tube MN2 drain electrode connects the second PMOS MP2 drain electrode and the 5th PMOS MP5 drain electrode, the second NMOS tube
MN2 grid connects the output end of phase inverter；Second NMOS tube MN2 source ground；
The input termination external input signal of phase inverter；
3rd NMOS tube MN3 drain electrode connects the 6th NMOS tube MN6 source electrode, and the 3rd NMOS tube MN3 grid connects the defeated of phase inverter
Go out end, the 3rd NMOS tube MN3 source ground；
4th NMOS tube MN4 drain electrode connects the 5th NMOS tube MN5 source electrode, and the 4th NMOS tube MN4 grid connects outside input letter
Number, the 4th NMOS tube MN4 source ground；
5th NMOS tube MN5 drain electrode connects the 6th PMOS MP6 drain electrode, and the 5th NMOS tube MN5 grid connects the first PMOS
MP1 drain electrode and the 3rd PMOS MP3 drain electrode；
6th NMOS tube MN6 drain electrode connects the 4th PMOS MP4 drain electrode, and the 6th NMOS tube MN6 grid connects the second PMOS
MP2 drain electrode and the 5th PMOS MP5 drain electrode；
One the first NMOS tube MN1 of termination of the first current source drain electrode, the other end ground connection of the first current source；
One the 4th NMOS tube MN4 of termination of the second current source drain electrode, the other end ground connection of the second current source；
The first output end that second PMOS MP2 drains with the tie point of the 5th PMOS MP5 drain electrodes is level shift circuit, the
The second output end that one PMOS MP1 drains with the tie point of the 3rd PMOS MP3 drain electrodes is level shift circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610218940.7A CN105915207B (en) | 2016-04-11 | 2016-04-11 | A kind of level shift circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610218940.7A CN105915207B (en) | 2016-04-11 | 2016-04-11 | A kind of level shift circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105915207A CN105915207A (en) | 2016-08-31 |
| CN105915207B true CN105915207B (en) | 2018-01-09 |
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| CN201610218940.7A Expired - Fee Related CN105915207B (en) | 2016-04-11 | 2016-04-11 | A kind of level shift circuit |
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Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI584596B (en) * | 2016-06-15 | 2017-05-21 | 智原科技股份有限公司 | Level shifter |
| CN106656160A (en) * | 2016-09-20 | 2017-05-10 | 上海集成电路研发中心有限公司 | High-speed potential conversion circuit |
| JP2018186400A (en) * | 2017-04-26 | 2018-11-22 | ラピスセミコンダクタ株式会社 | Level shift circuit |
| CN107612317A (en) * | 2017-09-26 | 2018-01-19 | 上海华虹宏力半导体制造有限公司 | A kind of charge pump circuit |
| CN108011629A (en) * | 2017-12-14 | 2018-05-08 | 电子科技大学 | A kind of high-speed low-power-consumption level displacement circuit |
| CN113114218A (en) * | 2021-04-21 | 2021-07-13 | 湖南融创微电子有限公司 | Level conversion circuit with pseudo-differential amplification |
| CN114285402A (en) * | 2021-12-09 | 2022-04-05 | 中国电子科技集团公司第五十八研究所 | High-speed high-stability level shift circuit |
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| CN1764069A (en) * | 2005-09-30 | 2006-04-26 | 威盛电子股份有限公司 | Voltage level converter |
| US7227400B1 (en) * | 2005-03-30 | 2007-06-05 | Integrated Device Technology, Inc. | High speed MOSFET output driver |
| CN103138741A (en) * | 2013-01-25 | 2013-06-05 | 电子科技大学 | Ultra-low power consumption level shift circuit |
| CN104038209A (en) * | 2014-06-19 | 2014-09-10 | 电子科技大学 | Level shifting circuit |
| CN105187047A (en) * | 2015-08-13 | 2015-12-23 | 电子科技大学 | Ultra-high-voltage level shifting circuit for IGBT (Insulated Gate Bipolar Translator) driving chip |
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2016
- 2016-04-11 CN CN201610218940.7A patent/CN105915207B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7227400B1 (en) * | 2005-03-30 | 2007-06-05 | Integrated Device Technology, Inc. | High speed MOSFET output driver |
| CN1764069A (en) * | 2005-09-30 | 2006-04-26 | 威盛电子股份有限公司 | Voltage level converter |
| CN103138741A (en) * | 2013-01-25 | 2013-06-05 | 电子科技大学 | Ultra-low power consumption level shift circuit |
| CN104038209A (en) * | 2014-06-19 | 2014-09-10 | 电子科技大学 | Level shifting circuit |
| CN105187047A (en) * | 2015-08-13 | 2015-12-23 | 电子科技大学 | Ultra-high-voltage level shifting circuit for IGBT (Insulated Gate Bipolar Translator) driving chip |
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| Publication number | Publication date |
|---|---|
| CN105915207A (en) | 2016-08-31 |
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Granted publication date: 20180109 Termination date: 20210411 |