CN108768363A - A kind of tri-state Zero-cross comparator circuit and power management chip - Google Patents
A kind of tri-state Zero-cross comparator circuit and power management chip Download PDFInfo
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- CN108768363A CN108768363A CN201810971655.1A CN201810971655A CN108768363A CN 108768363 A CN108768363 A CN 108768363A CN 201810971655 A CN201810971655 A CN 201810971655A CN 108768363 A CN108768363 A CN 108768363A
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- cross comparator
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/296—Time-programme switches providing a choice of time-intervals for executing more than one switching action and automatically terminating their operation after the programme is completed
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/28—Modifications for introducing a time delay before switching
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/567—Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
Abstract
The invention discloses a kind of tri-state Zero-cross comparator circuit and power management chips, including：Zero-cross comparator module, logic module output, start-up study module, negative sense imbalance handover module and underloading detection module, wherein, Zero-cross comparator module is used to compare the voltage of output end VOUT and the ends SW, generates logic level and overturns and control the shutdown of master power switch pipe；Start-up study module is used in DRVP signals be low, when Zero-cross comparator module is opened, generate it is suitable start sequential, to avoid the ends SW voltage disturbance during establishing caused by accidentally turn over；Logic module output is used to the voltage that Zero-cross comparator module exports being converted to digital logic control signals；Negative current lacks of proper care handover module for when load current being extremely low, the overturning point of Zero-cross comparator module being set as negative current, is played a protective role.The false triggering during switch power supply power tube moment switches of zero passage detection signal can be prevented through the invention, and master power switch pipe is avoided to be burned out.
Description
Technical field
The present invention relates to Analogous Integrated Electronic Circuits technical fields, and more specifically, it relates to a kind of tri-state Zero-cross comparator circuits
And power management chip, it is suitable for switching power circuits.
Background technology
Switching power source chip is a very wide range of chip of a kind of purposes in Analogous Integrated Electronic Circuits, can be according to the demand of load
Input voltage is reduced or promoted, the load circuit that stable output voltage is supplied to rear class is generated, usually there is conversion effect
The features such as rate is high, control mode is flexible, input/output bound is wide.And in switching power source chip, the switch of BOOST boost types
Power supply chip has particularly important purposes, its main feature is that the conducting and shutdown of power tube can be controlled, output voltage is made to be higher than
Input voltage.
As shown in Figure 1, power tube drive signal DRVP indicates that duty ratio is the square-wave signal of D, when DRVP is high level,
The MP1 shutdowns of master power switch pipe, the MN1 conductings of N-type power switch tube, then the ends SW are pulled to ground potential, the power supply V of input terminal VININ
The electric current generated on inductance L1 over the ground makes inductance L1 storage energies, is powered at this time to output end VOUT by capacitance C1；When
When DRVP is low level, the MP1 conductings of master power switch pipe, the MN1 shutdowns of N-type power switch tube, not due to the electric current on inductance L1
It can be mutated, therefore, SW terminal potentials are elevated, VSW>VOUT, supplied to capacitance C1 and output end VOUT by master power switch pipe MP1
Electricity can be obtained by law of conservation of energy when circuit stability works：VOUT=VIN/D.In BOOST booster circuits, if load current
It is smaller, during the MP1 conductings of master power switch pipe, as inductive current iLWhen being gradually reduced, the voltage V of output end VOUTOUTWith
The voltage V at the ends SWSWIt gradually approaches, works as iLWhen being negative, VOUT>VSW, will produce at this time from output end VOUT to the anti-of input terminal VIN
It, can be to the power supply V of input terminal VIN to reverse irrigated currentINBring damage.Therefore, increase zero passage detection is needed to compare in BOOST circuits
Circuit 1, when zero passage detection comparison circuit 1 detects that the electric current on inductance L1 gradually approaches 0, then BOOST_NCD signals can be from
Low level overturning is high level, and controlling power driving circuit 2 makes power tube drive signal DRVP be high level, and main power is opened
Pipe MP1 shutdowns are closed, have the function that protect power stage.
As shown in Fig. 2, being existing zero passage detection comparison circuit schematic diagram, specifically, zero passage detection comparison circuit 1 wraps
It includes：Zero-cross comparator module 21 and logic module output 22, in BOOST circuits, when the driving that DRVP is main power switch tube MP1
Signal, DRVN are the reverse signal of DRVP, when DRVP is low level, the MP1 conductings of master power switch pipe, zero passage detection comparison circuit
1 starts to work, if detecting VSW>VOUT, then generated without reverse current, zero passage detection comparison circuit 1 exports BOOST_NCD and maintains
Low level；Work as VSW<VOUTWhen, the anti-sink current of negative sense at the end from output end VOUT to SW is will produce on master power switch pipe MP1, this
When zero passage detection comparison circuit 1 export high level, and control DRVP signals shutdown master power switch pipe MP1.But the zero passage is examined
Surveying comparison circuit 1, there are following two defects：
First, when DRVP becomes low level, zero-crossing comparator can enable relatively V at onceOUTAnd VSWSize, but at this time
The current potential at the ends SW needs the regular hour when being raised to high potential from lower current potential, and before the current potential at the ends SW stabilization, meeting
There is certain damped oscillation phenomenon, this can cause zero-crossing comparator to occur accidentally to overturn, and generate the power tube drive signal of mistake
DRVP；
Second, in inductive current iLWhen bigger, the offset that the factors such as technique, temperature drift are brought in order to prevent, usually in SW
End is added imbalance unit second switch pipe MP2 and so that the comparison point of zero passage detection comparison circuit is positive inductive current, when strong
Under PWM modulation pattern processed, when load current is smaller, it will appear negative sense on inductance during master power switch pipe MP1 normallies
Electric current causes BOOST circuits can not work normally if enabling existing zero passage detection comparator and can occur accidentally to overturn, therefore usually
Zero passage detection module can be closed at light load in pole, but such scheme has systematic risk, i.e., when intense source is so added in VOUT distal process
Or when the exception such as generation overvoltage, master power switch pipe MP1 can flow through reversed high current, and master power switch pipe MP1 is caused to burn, from
And damage power management chip.
Invention content
In view of this, the present invention provides a kind of tri-state Zero-cross comparator circuit and power management chip, it is suitable for switch electricity
Source circuit to prevent the false triggering during switch power supply power tube moment switches of zero passage detection signal, and can be selected according to pattern
It selects while providing forward current offset and negative current deviates two kinds of protection trigger mechanisms.
To achieve the above object, the present invention provides the following technical solutions：
A kind of tri-state Zero-cross comparator circuit, is suitable for switching power circuit, and the tri-state Zero-cross comparator circuit includes：Zero passage
Comparison module, logic module output, start-up study module, negative sense imbalance handover module and underloading detection module, wherein：
The Zero-cross comparator module includes first end, second end, third end, the 4th end, the 5th end, the 6th end and the 7th
End；The start-up study module includes first end, second end, third end and the 4th end；The logic module output includes first
End, second end, third end and the 4th end；The negative sense imbalance handover module includes first end, second end and third end；It is described light
It includes first end and second end to carry detection module；
Output end VOUT of the first end of the Zero-cross comparator module as the tri-state Zero-cross comparator circuit, the zero passage
SW end of the second end of comparison module as the tri-state Zero-cross comparator circuit；The third end of the Zero-cross comparator module with it is described
The second end of start-up study module is connected, the 4th end of the Zero-cross comparator module and the third end phase of the start-up study module
Even, the 5th end of the Zero-cross comparator module is connected with the first end of negative sense imbalance handover module, the Zero-cross comparator mould
6th end of block is connected with the second end of negative sense imbalance handover module, and the 7th end of the Zero-cross comparator module is patrolled with described
The first end for collecting output module is connected, and the third end of the negative sense imbalance handover module is as negative sense imbalance handover module
FPWM input terminals；
The second end of the logic module output is connected with the 4th end of the start-up study module, and the logic exports mould
The third end of block is connected with the first end of the start-up study module, and the 4th end of the logic module output is as the tri-state
The output end of Zero-cross comparator circuit；
The underloading detection module loses for detecting inductive current, the output end of the underloading detection module with the negative sense
It adjusts the third end of handover module to be connected, is underloading and needs to be operated in when the underloading detection module detects the circuit current
When under PWM mode, the output high level of the underloading detection module, otherwise, the output low level of the underloading detection module；
The Zero-cross comparator module is used for the voltage of the output end VOUT and the ends SW, generates logic level and turns over
Turn and control the shutdown of master power switch pipe；
The start-up study module is used in DRVP signals be low, and when the Zero-cross comparator module is opened, it is suitable to generate
Start sequential, is accidentally turned over caused by foundation in the process to avoid the voltage disturbance at the ends SW；
The logic module output is used to the voltage that the Zero-cross comparator module exports being converted to Digital Logic control letter
Number；
The negative current imbalance handover module is used for when load current is extremely low, by the overturning of the Zero-cross comparator module
Point is set as negative current, plays a protective role.
Further, the Zero-cross comparator module includes：Current source (I), the second PMOS tube (MP2), the 4th PMOS tube
(MP4), the 5th PMOS tube (MP5), the 6th PMOS tube (MP6), the 7th PMOS tube (MP7), the second NMOS tube (MN2), third
NMOS tube (MN3), the 6th NMOS tube (MN6), the 7th NMOS tube (MN7), wherein：
The first end of the current source (I), the first end of the 4th PMOS tube (MP4) and the 5th PMOS tube
(MP5) common end of second end, the 7th PMOS tube (MP7) second end as the Zero-cross comparator module first
End；Second end of the second end of second PMOS tube (MP2) as the Zero-cross comparator module；7th PMOS tube
(MP7) common end of first end and the first end of the 7th NMOS tube (MN7) as the Zero-cross comparator module the 7th
End is connected with the first end of the logic module output；
The first end of second PMOS tube (MP2) respectively with the second end of the 4th PMOS tube (MP4) and described
The second end of six PMOS tube (MP6) is connected；The control terminal of 5th PMOS tube (MP5) and the 5th PMOS tube (MP5)
First end is connected, and common end is connected with the first end of the third NMOS tube (MN3), and the as the Zero-cross comparator module
Five ends are connected with the first end of negative sense imbalance handover module；
The control terminal of 7th PMOS tube (MP7) is connected with the first end of the 6th PMOS tube (MP6), and with it is described
The first end of 6th NMOS tube (MN6) is connected；The control terminal of 7th NMOS tube (MN7), the 6th NMOS tube (MN6)
Control terminal, the control terminal of the third NMOS tube (MN3), the control terminal of second NMOS tube (MN2) are connected, as the mistake
6th end of zero balancing module is connected with the second end of negative sense imbalance handover module；
The control terminal of second NMOS tube (MN2) is connected with the first end of second NMOS tube (MN2), and described second
The first end of NMOS tube (MN2) is connected with the second end of the current source (I)；The second end of second NMOS tube (MN2), institute
State the second end of third NMOS tube (MN3), the second end of the 6th NMOS tube (MN6) and the 7th NMOS tube (MN7)
Second end ground connection；
Third end and the start delay of the control terminal of second PMOS tube (MP2) as the Zero-cross comparator module
The second end of module is connected；Fourth end and institute of the control terminal of 4th PMOS tube (MP4) as the Zero-cross comparator module
The third end for stating start delay module is connected.
Further, the negative sense imbalance handover module includes：4th NMOS tube (MN4) and the 5th NMOS tube (MN5),
In：
First end and the zero passage of the first end of 4th NMOS tube (MN4) as negative sense imbalance handover module
5th end of comparison module is connected, and the control terminal of the 4th NMOS tube (MN4) lacks of proper care the of handover module as the negative sense
Three ends input FPWM；The second end of 4th NMOS tube (MN4) is connected with the first end of the 5th NMOS tube (MN5), institute
State second end and the Zero-cross comparator module of the control terminal of the 5th NMOS tube (MN5) as negative sense imbalance handover module
6th end is connected；The second end of 5th NMOS tube (MN5) and ground connection.
Further, the logic module output includes：First phase inverter (INV1), the second phase inverter (INV2), first
NAND gate (NAND1), the first nor gate (NOR1), the second nor gate (NOR2), wherein：
First end and the zero passage ratio of the input terminal of first phase inverter (INV1) as the logic module output
The 7th end compared with module is connected；The output end of first phase inverter (INV1) and the first of first NAND gate (NAND1)
Input terminal is connected；Second end and institute of second input terminal of first NAND gate (NAND1) as the logic module output
The 4th end for stating start-up study module is connected；The output end of first NAND gate (NAND1) and first nor gate
(NOR1) first input end is connected；
Second input terminal of second nor gate (NOR2) is connected with the first end of the start-up study module, and described
The first input end of two nor gates (NOR2) is connected with the output end of first nor gate (NOR1), first nor gate
(NOR1) the second input terminal is connected with the output end of second nor gate (NOR2)；
The output end of first nor gate (NOR1) is connected with the input terminal of second phase inverter (INV2), and described
Fourth end of the output end of two phase inverters (INV2) as the logic module output.
Further, the start-up study module includes：First delay unit, the second delay unit, third phase inverter
(INV3) and the 4th phase inverter (INV4), wherein：
The first end of first delay unit exports mould as the first end of the start-up study module with the logic
The third end of block is connected；The second end of first delay unit respectively with the first end of second delay unit and described
The input terminals of three phase inverters (INV3) is connected, and the second end of first delay unit as the start-up study module the
Two ends are connected with the third end of the Zero-cross comparator module；The output end of the third phase inverter (INV3) prolongs as the startup
When module third end be connected with the 4th end of the Zero-cross comparator module；
The output end of second delay unit is connected with the input terminal of the 4th phase inverter (INV4), and the described 4th is anti-
Second end of the output end of phase device (INV4) as the 4th end and the logic module output of the start-up study module
It is connected.
Further, first delay unit and/or second delay unit include：5th phase inverter (INV5),
Hex inverter (INV6), the 7th phase inverter (INV7), resistance (RA), the first capacitance (CA), first with door (AND1) and switch
It manages (MPA), wherein：
The input terminal of the hex inverter (INV6) is as first delay unit and/or second delay unit
First end；The output end of the hex inverter (INV6) respectively with the input terminal of the 7th phase inverter (INV7), described
The control terminal of switching tube (MPA) and described first it is connected with the second input terminal of door (AND1)；
The output end of 7th phase inverter (INV7) and the resistance (RA) one end be connected, the resistance (RA) it is another
One end respectively with the input terminal of the 5th phase inverter (INV5), the first capacitance (CA) one end and the switching tube
(MPA) first end is connected；The second end of the switching tube (MPA) is connected with power end (VDD), the first capacitance (CA)
The other end is grounded；
The output of 5th phase inverter (INV5) is connected with described first with the first input end of door (AND1), and described
One second end with the output end of door (AND1) as first delay unit and/or second delay unit.
Further, first delay unit and/or second delay unit include：8th phase inverter (INV8),
9th phase inverter (INV9), the tenth phase inverter (INV10), the 11st phase inverter (INV11), the 12nd phase inverter (INV12),
Eight PMOS tube (MP8), the 9th PMOS tube (MP9), the tenth PMOS tube (MP10), the 8th NMOS tube (MN8), the 9th NMOS tube
(MN9), the tenth NMOS tube (MN10) and the second capacitance (CB), wherein：
The input terminal of 8th phase inverter (INV8) is as first delay unit and/or second delay unit
First end；The output end of 8th phase inverter (INV8) is connected with the input terminal of the 9th phase inverter (INV9), described
The output end of 9th phase inverter (INV9) respectively with the control terminal of the 8th NMOS tube (MN8) and the tenth phase inverter
(INV10) input terminal is connected；
The output end of tenth phase inverter (INV10) is connected with the control terminal of the tenth NMOS tube (MN10), described
The first end of 8th NMOS tube (MN8) is connected with the first end of the 8th PMOS tube (MP8), the 8th PMOS tube (MP8)
First end be connected with the control terminal of the 8th PMOS tube (MP8), the second end of the 8th PMOS tube (MP8), described
The second end of nine PMOS tube (MP9) and the second end of the tenth PMOS tube (MP10) are connected with power end (VDD), and the described tenth
The control terminal of PMOS tube (MP10) is connected with the output end of the 11st phase inverter (INV11)；
The second end of 8th NMOS tube (MN8) is connected with the first end of the 9th NMOS tube (MN9), and the described 9th
The control terminal of NMOS tube (MN9) is connected with the output end of the 11st phase inverter (INV11)；9th NMOS tube (MN9)
Second end and the tenth NMOS tube (MN9) second end ground connection；
The control terminal of 8th PMOS tube (MP8) is connected with the control terminal of the 9th PMOS tube (MP9), and the described 9th
The first end of PMOS tube (MP9) and the first end of the tenth PMOS tube (MP10) and the first of the tenth NMOS tube (MN10)
End is connected；The first end of tenth NMOS tube (MN10) respectively with the input terminal of the 11st phase inverter (INV11) and institute
State the second capacitance (CB) one end be connected, the output end of the 11st phase inverter (INV11) and the 12nd phase inverter
(INV12) input terminal is connected, the second capacitance (CB) the other end ground connection；12nd phase inverter (INV12) it is defeated
Second end of the outlet as first delay unit and/or second delay unit.
A kind of power management chip, including：Tri-state Zero-cross comparator circuit described above.
It can be seen via above technical scheme that compared with prior art, the invention discloses a kind of tri-state Zero-cross comparator electricity
Road and power management chip, are suitable for switching power circuit, which includes：Zero-cross comparator module, logic
Output module, start-up study module, negative sense imbalance handover module and underloading detection module, wherein Zero-cross comparator module is used for
Compare the voltage of output end VOUT and the ends SW, generates logic level and overturn and control the shutdown of master power switch pipe；Start-up study
Module is used in DRVP signals be low, when Zero-cross comparator module is opened, generates and suitably starts sequential, to avoid the voltage at the ends SW
Disturbance is generated during establishing accidentally to be turned over；Logic module output is used to the voltage that Zero-cross comparator module exports being converted to number
Word logic control signal；Negative current imbalance handover module is used for when load current is extremely low, by the overturning of Zero-cross comparator module
Point is set as negative current, plays a protective role.The tri-state Zero-cross comparator circuit provided through the invention can prevent zero passage detection
Signal false triggering during switch power supply power tube moment switches, and forward current offset can be simultaneously provided according to model selection
Two kinds of protection trigger mechanisms are deviated with negative current, avoid master power switch pipe from being burned out, to protection power source managing chip.
Description of the drawings
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technology description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is a kind of BOOST electrical block diagrams provided in the prior art；
Fig. 2 is a kind of Zero-cross comparator circuit theory schematic diagram provided in the prior art；
Fig. 3 is another tri-state Zero-cross comparator electrical block diagram provided in an embodiment of the present invention；
Fig. 4 is a kind of realization circuit original of the first delay cell provided in an embodiment of the present invention and/or the second delay cell
Reason figure；
Fig. 5 be power tube drive signal DRVP provided in an embodiment of the present invention, the first delay cell output signal DRVP_
The waveform diagram of DLY1 and the output signal DRVP_DLY2 of the second delay cell；
Fig. 6 is that the first delay cell provided in an embodiment of the present invention and/or the another of the second delay cell realize circuit
Schematic diagram.
Specific implementation mode
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation describes, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
As shown in figure 3, to solve problem of the prior art, the present invention proposes a kind of tri-state zero passage detection comparison circuit,
Suitable for switching power circuit, include mainly：Zero-cross comparator module 31, start-up study module 33, is born logic module output 32
To imbalance handover module 34 and underloading detection module 35.
The principle of the present invention schematic block diagram is as shown in figure 3, above-mentioned Zero-cross comparator module 31 includes first end VOUT, second end
SW, third end DRVP_DLY1, the 4th end DRVP_DLY1N, the 5th end, the 6th end and the 7th end；Above-mentioned start-up study module 33
Including first end DRVP, second end DRVP_DLY1, third end DRVP_DLY1N and the 4th end DRVP_DLY2N；Above-mentioned logic is defeated
It includes first end, second end DRVP_DLY2N, third end DRVP and the 4th end BOOST_NCD to go out module 32；Above-mentioned negative sense imbalance
Handover module 34 includes first end, second end and third end FPWM；Above-mentioned underloading detection module 35 includes first end iLWith second
Hold FPWM；.
Output end VOUTs of the first end VOUT of above-mentioned Zero-cross comparator module 31 as above-mentioned tri-state Zero-cross comparator circuit, on
State SW ends of the second end SW of Zero-cross comparator module 31 as above-mentioned tri-state Zero-cross comparator circuit；Above-mentioned Zero-cross comparator module 31
Third end DRVP_DLY1 is connected with the second end DRVP_DLY1 of above-mentioned start-up study module 33, above-mentioned Zero-cross comparator module 31
4th end DRVP_DLY1N is connected with the third end DRVP_DLY1N of above-mentioned start-up study module 33, above-mentioned Zero-cross comparator module 31
The lack of proper care first end of handover module 34 of the 5th end and above-mentioned negative sense be connected, the 6th end of above-mentioned Zero-cross comparator module 31 with it is above-mentioned
The second end of negative sense imbalance handover module 34 is connected, the 7th end and the logic module output 32 of the Zero-cross comparator module 31
First end be connected, the third end FPWM of above-mentioned negative sense imbalance handover module 34 lacks of proper care the FPWM of handover module as above-mentioned negative sense
Input terminal；The 4th end DRVP_ of the second end DRVP_DLY2N of above-mentioned logic module output 32 and above-mentioned start-up study module 33
DLY2N is connected, and the third end DRVP of above-mentioned logic module output 32 is connected with the first end DRVP of above-mentioned start-up study module 33,
Output end BOOST_NCDs of the 4th end BOOST_NCD of above-mentioned logic module output 32 as above-mentioned tri-state Zero-cross comparator circuit.
Above-mentioned underloading detection module loses for detecting inductive current, output end and the above-mentioned negative sense of above-mentioned underloading detection module
It adjusts the third end of handover module to be connected, is underloading and needs to be operated in when above-mentioned underloading detection module detects above-mentioned circuit current
When under PWM mode, the output high level of above-mentioned underloading detection module, otherwise, the output low level of above-mentioned underloading detection module；On
Voltage of the Zero-cross comparator module 31 for more above-mentioned output end VOUT and the above-mentioned ends SW is stated, logic level is generated and overturns and control
The shutdown of master power switch pipe MP1；Above-mentioned start-up study module 33 is used in DRVP signals be low, above-mentioned Zero-cross comparator module 31
When unlatching, suitable startup sequential is generated, is accidentally turned over caused by foundation in the process to avoid the voltage disturbance at the above-mentioned ends SW；On
Logic module output 32 is stated for the voltage that above-mentioned Zero-cross comparator module 31 exports to be converted to digital logic control signals；It is above-mentioned
Negative current lacks of proper care handover module 34 for when load current is extremely low, the overturning point of above-mentioned Zero-cross comparator module 31 to be set as negative
To electric current, play a protective role.
Fig. 3 is the specific implementation circuit diagram of the present invention, wherein the effect of the second PMOS tube MP2 is that setting is suitable positive
Offset current, the deviation to Zero-cross comparator overturning point there are certain allowance to prevent the drifts such as technique, temperature from bringing；2nd PMOS
Pipe MP2 selects the device with master power switch pipe MP1 same types in Fig. 1, to reach equiva lent impedance matching.
As shown in Figure 3, it is preferred that above-mentioned Zero-cross comparator module 31 includes：Current source I, the second PMOS tube MP2, the 4th
PMOS tube MP4, the 5th PMOS tube MP5, the 6th PMOS tube MP6, the 7th PMOS tube MP7, the second NMOS tube MN2, third NMOS tube
MN3, the 6th NMOS tube MN6, the 7th NMOS tube MN7, wherein：
The of the first end of above-mentioned current source I, the first end of above-mentioned 4th PMOS tube MP4 and above-mentioned 5th PMOS tube MP5
The common end at two ends, above-mentioned 7th PMOS tube MP7 first end VOUT of the second end as above-mentioned Zero-cross comparator module 31；It is above-mentioned
Second end SW of the second end of second PMOS tube MP2 as above-mentioned Zero-cross comparator module 31；The first of above-mentioned 7th PMOS tube MP7
Seventh end and above-mentioned logic of the common end of the first end of end and above-mentioned 7th NMOS tube MN7 as above-mentioned Zero-cross comparator module 31
The first end of output module 32 is connected；
The first end of the above-mentioned second PMOS tube MP2 second end and the above-mentioned 6th with above-mentioned 4th PMOS tube MP4 respectively
The second end of PMOS tube MP6 is connected；The first end phase of the control terminal and above-mentioned 5th PMOS tube MP5 of above-mentioned 5th PMOS tube MP5
Even, common end is connected with the first end of above-mentioned third NMOS tube MN3, as above-mentioned Zero-cross comparator module 31 the 5th end with it is upper
The first end for stating negative sense imbalance handover module 34 is connected；
The control terminal of above-mentioned 7th PMOS tube MP7 is connected with the first end of above-mentioned 6th PMOS tube MP6, and with the above-mentioned 6th
The first end of NMOS tube MN6 is connected；The control terminal of above-mentioned 7th NMOS tube MN7, the control terminal of above-mentioned 6th NMOS tube MN6, on
The control terminal for stating third NMOS tube MN3 is connected with the control terminal of above-mentioned second NMOS tube MN2, as above-mentioned Zero-cross comparator module 31
The lack of proper care second end of handover module 34 of the 6th end and above-mentioned negative sense be connected；
The control terminal of above-mentioned second NMOS tube MN2 is connected with the first end of above-mentioned second NMOS tube MN2, above-mentioned 2nd NMOS
The first end of pipe MN2 is connected with the second end of above-mentioned current source I；The second end of above-mentioned second NMOS tube MN2, above-mentioned 3rd NMOS
The second end of the second end of pipe MN3, the second end of above-mentioned 6th NMOS tube MN6 and above-mentioned 7th NMOS tube MN7 is grounded；
The control terminal of above-mentioned second PMOS tube MP2 as above-mentioned Zero-cross comparator module 31 third end DRVP_DLY1N with it is upper
The second end DRVP_DLY1N for stating start delay module 33 is connected；The control terminal of above-mentioned 4th PMOS tube MP4 is as above-mentioned zero passage
4th end DRVP_DLY2N of comparison module 31 is connected with the third end DRVP_DLY2N of above-mentioned start delay module 33.
It should be noted that above-mentioned second PMOS tube MP2, above-mentioned 4th PMOS tube MP4, above-mentioned 5th PMOS tube MP5, on
State the 6th PMOS tube MP6, above-mentioned 7th PMOS tube MP7, above-mentioned second NMOS tube MN2, above-mentioned third NMOS tube MN3, above-mentioned
The six NMOS tube MN6 and first end of above-mentioned 7th NMOS tube MN7 is source electrode, second end is drain electrode, control terminal is grid.
As shown in Figure 3, it is preferred that above-mentioned negative sense imbalance handover module 34 includes：4th NMOS tube MN4 and the 5th NMOS tube
MN5, wherein：
First end and above-mentioned zero passage of the first end of above-mentioned 4th NMOS tube MN4 as above-mentioned negative sense imbalance handover module 34
5th end of comparison module 31 is connected, and the control terminal of above-mentioned 4th NMOS tube MN4 is as above-mentioned negative sense imbalance handover module 34
Third end inputs FPWM；The second end of above-mentioned 4th NMOS tube MN4 is connected with the first end of above-mentioned 5th NMOS tube MN5, above-mentioned
Second end and above-mentioned Zero-cross comparator module 31 of the control terminal of 5th NMOS tube MN5 as above-mentioned negative sense imbalance handover module 34
6th end is connected；The second end of above-mentioned 5th NMOS tube MN5 and ground connection.
It should be noted that the first end of above-mentioned 4th NMOS tube MN4 and above-mentioned 5th NMOS tube MN5 is source electrode, second
End is drain electrode, control terminal is grid.
As shown in Figure 3, it is preferred that above-mentioned logic module output 32 includes：First phase inverter INV1, the second phase inverter
INV2, the first NAND gate NAND1, the first nor gate NOR1, the second nor gate NOR2, wherein：
First end and above-mentioned zero passage ratio of the input terminal of above-mentioned first phase inverter INV1 as above-mentioned logic module output 32
The 7th end compared with module 31 is connected；The first of the output end of above-mentioned first phase inverter INV1 and above-mentioned first NAND gate NAND1 is defeated
Enter end to be connected；Second end DRVP_ of the second input terminal of above-mentioned first NAND gate NAND1 as above-mentioned logic module output 32
DLY2N is connected with the 4th end DRVP_DLY2N of above-mentioned start-up study module 33；The output end of above-mentioned first NAND gate NAND1 with
The first input end of above-mentioned first nor gate NOR1 is connected；The second input terminal DRVP of above-mentioned second nor gate NOR2 is opened with above-mentioned
The first end DRVP of dynamic time delay module 33 is connected, first input end and above-mentioned first nor gate of above-mentioned second nor gate NOR2
The output end of NOR1 is connected, the output end phase of the second input terminal of above-mentioned first nor gate NOR1 and above-mentioned second nor gate NOR2
Even；The output end of above-mentioned first nor gate NOR1 is connected with the input terminal of above-mentioned second phase inverter INV2, above-mentioned second phase inverter
Fourth end BOOST_NCD of the output end of INV2 as above-mentioned logic module output 32.
As shown in Figure 3, it is preferred that above-mentioned start-up study module 33 includes：First delay unit, the second delay unit,
Three phase inverter INV3 and the 4th phase inverter INV4, wherein：
First end DRVP and above-mentioned logic of the first end of above-mentioned first delay unit as above-mentioned start-up study module 33
The third end DRVP of output module 32 is connected；The second end of above-mentioned first delay unit respectively with above-mentioned second delay unit
One end is connected with the input terminal of above-mentioned third phase inverter INV3, and the second end of above-mentioned first delay unit is prolonged as above-mentioned startup
When module 33 second end DRVP_DLY1 be connected with the third end DRVP_DLY1 of above-mentioned Zero-cross comparator module 31；Above-mentioned third is anti-
Third end DRVP_DLY1N and above-mentioned Zero-cross comparator module 31 of the output end of phase device INV3 as above-mentioned start-up study module 33
The 4th end DRVP_DLY1N be connected；
The output end of above-mentioned second delay unit is connected with the input terminal of above-mentioned 4th phase inverter INV4, above-mentioned 4th reverse phase
Fourth end DRVP_DLY2N and above-mentioned logic module output of the output end of device INV4 as above-mentioned start-up study module 33
32 second end DRVP_DLY2N is connected.
As shown in figure 3, third NMOS tube MN3, the 5th NMOS tube MN5, the 6th NMOS tube MN6, the 7th NMOS tube MN7 are the
The mirror image pipe of two NMOS tube MN2, to match the electric current I of the second NMOS tube MN2MN2, suitable transistor spaciousness ratio is set so that
IMN3=IMN6=IMN7, IMN5=kIMN6(k>1), the first delay unit and the second delay unit, feasible circuit is by Fig. 4
It provides,
As shown in Figure 4, it is preferred that above-mentioned first delay unit and/or above-mentioned second delay unit include：5th phase inverter
INV5, hex inverter INV6, the 7th phase inverter INV7, resistance RA, the first capacitance CA, first with door AND1 and switching tube
MPA, wherein：
The input terminal of above-mentioned hex inverter INV6 is as above-mentioned first delay unit and/or above-mentioned second delay unit
First end S_IN；The output end of above-mentioned hex inverter INV6 respectively with the input terminal of above-mentioned 7th phase inverter INV7, above-mentioned open
The control terminal and above-mentioned first for closing pipe MPA are connected with the second input terminal of door AND1；The output of above-mentioned 7th phase inverter INV7
End and above-mentioned resistance RAOne end be connected, above-mentioned resistance RAThe other end respectively with the input terminal of above-mentioned 5th phase inverter INV5, on
State the first capacitance CAOne end and above-mentioned switching tube MPA first end be connected；The second end and power end of above-mentioned switching tube MPA
VDD is connected, above-mentioned first capacitance CAThe other end ground connection；The output of above-mentioned 5th phase inverter INV5 and above-mentioned first and door AND1
First input end be connected, above-mentioned first prolongs with the output end of door AND1 as above-mentioned first delay unit and/or above-mentioned second
The second end S_OUT of Shi Danyuan.
It should be noted that the first end of above-mentioned switching tube MPA is source electrode, second end is drain electrode, control terminal is grid.
In figure 3, as inductive current iLFor be lightly loaded and need work in a PWM mode when, FPWM is high level, otherwise,
FPWM is low level.When FPWM is low level, the 4th NMOS tube MN4 shutdowns then have I at this timeMP5=IMP6；When DRVP is electric from height
When flat overturning is low level, then DRVP_DLY1 is high level, and DRVP_DLYN is low level, then the 4th PMOS tube MP4 is closed first
Disconnected, Zero-cross comparator module 31 can detect the voltage at the ends VOUT and the ends SW and be compared at this time, but SW terminal voltages are not also steady at this time
Fixed to establish, then it is high level to have DRVP_DLY2, i.e., by two-stage delay unit come to DRVP signals into line delay, and by patrolling
The output that output module 32 shields BOOST_NCD signals is collected, prevents it from occurring accidentally to overturn, when the time delay for passing through the second delay unit
Afterwards, DRVP_DLY2 is low level, and DRVP_DLY2N is high level, at this time shielding of the signal removal to BOOST_NCD signals,
The output of Zero-cross comparator module 31 can be with normal transmission to the ports BOOST_NCD, in this state, if VOUT>VSW-IMN6*
RON_P2, wherein RON_P2For the equivalent conduction impedance of the second PMOS tube MP2, then BOOST_NCD is high level and is locked as the shape
State, the signal can make DRVP be high level, and power switch tube MP1 is turned off, and resetting DRVP again after the next period arrives is
Low level, Zero-cross comparator module 31, which reopens, starts sequential and to VOUTEnd and VSWEnd is detected compared with.
When inductive current very little, FPWM is high level, and the 4th NMOS tube MN4 is opened, then has I at this timeMP5=IMN5+IMN3
=(1+k) IMN5, IMP6=IMN6, so there is IMP5>IMP6.When the overturning of DRVP signals is low level, then third PMOS tube MP4 is first
It is first turned off, Zero-cross comparator module 31 can detect V at this timeOUTWith VSWVoltage and be compared, but V at this timeSWVoltage is not stablized also
It establishes, it is high level to have DRVP_DLY1, i.e., exports mould into line delay, and by logic to DRVP signals by delay unit
Block 32 shields the output of BOOST_NCD signals, prevents it from occurring accidentally to overturn, is delayed when passing through the second delay unit, DRVP_
DLY2 is low level, and DRVP_DLY2N is high level, at this time shielding of the signal removal to BOOST_NCD signals, Zero-cross comparator
The output of module 31 can be with normal transmission to the ports BOOST_NCD, in this state, if havingIts2In, WN6/LN6For the width of the 6th NMOS tube MN6
Spacious ratio, unElectron mobility, C for N-type pipeOXFor grid oxygen capacitance.Then BOOST_NCD is high level and is locked as the state, should
Signal can make DRVP be high level, power switch tube MP1 shutdowns, until it is low electricity to reset DRVP after the arrival of next period again
Flat, Zero-cross comparator module 31, which reopens, to be started sequential and is detected compared with to the ends VOUT and the ends VSW.
Fig. 4 is a kind of feasible circuit diagram of the first delay unit and/or the second delay unit in the present invention.Scheming
In 4, S_IN is signal input part, and S_OUT is time delayed signal output end, when S_IN from high level turn over for low level when, A0 nodes
It is turned over from low level as high level, switching tube MPA turns off the pull-up of A1 nodes, and A1 nodes gradually pass through the 7th phase inverter INV7
Electric discharge is turned over as low level, then A2 nodes overturning is high level, to make S_OUT generate time delayed signal；When S_IN is turned over from low level
For high level when, A0 nodes are turned over from high level as low level, and A1 nodes are pulled to high level immediately, and A2 nodes become low electricity
It is flat, it is high level to make S_OUT overturn quickly, has delay to generate S_IN and be turned over from high level for low level, from low level
Overturning is the no-delay effect of high level, according to the effect of the first delay unit and the second delay unit, power tube drive signal
The waveform of the output signal DRVP_DLY2 of DRVP, the output signal DRVP_DLY1 of the first delay cell and the second delay cell are such as
Shown in Fig. 5, T_dly1 is the delay time of the first delay unit in Fig. 5, and T_dly2 is the delay time of the second delay unit.
Fig. 6 is the feasible circuit diagram of another kind of the first delay unit and/or the second delay unit in the present invention.Such as
Shown in Fig. 6, above-mentioned first delay unit and/or above-mentioned second delay unit include：8th phase inverter INV8, the 9th phase inverter
INV9, the tenth phase inverter INV10, the 11st phase inverter INV11, the 12nd phase inverter INV12, the 8th PMOS tube MP8, the 9th
PMOS tube MP9, the tenth PMOS tube MP10, the 8th NMOS tube MN8, the 9th NMOS tube MN9, the tenth NMOS tube MN10 and the second capacitance
CB, wherein：
The input terminal of above-mentioned 8th phase inverter INV8 is as above-mentioned first delay unit and/or above-mentioned second delay unit
First end；The output end of above-mentioned 8th phase inverter INV8 is connected with the input terminal of above-mentioned 9th phase inverter INV9, and the above-mentioned 9th is anti-
The output end of the phase device INV9 input terminal with the control terminal and above-mentioned tenth phase inverter INV10 of above-mentioned 8th NMOS tube MN8 respectively
It is connected；The output end of above-mentioned tenth phase inverter INV10 is connected with the control terminal of above-mentioned tenth NMOS tube MN10, above-mentioned 8th NMOS
The first end of pipe MN8 is connected with the first end of above-mentioned 8th PMOS tube MP8, the first end of above-mentioned 8th PMOS tube MP8 with it is above-mentioned
The control terminal of 8th PMOS tube MP8 is connected, the second end of above-mentioned 8th PMOS tube MP8, the second end of above-mentioned 9th PMOS tube MP9
Be connected with power end VDD with the second end of above-mentioned tenth PMOS tube MP10, the control terminal of above-mentioned tenth PMOS tube MP10 with it is above-mentioned
The output end of 11st phase inverter INV11 is connected.
The second end of above-mentioned 8th NMOS tube MN8 is connected with the first end of above-mentioned 9th NMOS tube MN9, above-mentioned 9th NMOS
The control terminal of pipe MN9 is connected with the output end of above-mentioned 11st phase inverter INV11；The second end of above-mentioned 9th NMOS tube MN9 and
The second end of above-mentioned tenth NMOS tube MN9 is grounded；The control terminal of above-mentioned 8th PMOS tube MP8 is with above-mentioned 9th PMOS tube MP9's
Control terminal is connected, the first end and the above-mentioned tenth of the first end and above-mentioned tenth PMOS tube MP10 of above-mentioned 9th PMOS tube MP9
The first end of NMOS tube MN10 is connected；The first end of above-mentioned tenth NMOS tube MN10 respectively with above-mentioned 11st phase inverter INV11
Input terminal and above-mentioned second capacitance CBOne end be connected, the output end and the above-mentioned 12nd of above-mentioned 11st phase inverter INV11
The input terminal of phase inverter INV12 is connected, above-mentioned second capacitance CBThe other end ground connection；Above-mentioned 12nd phase inverter INV12's is defeated
Second end of the outlet as above-mentioned first delay unit and/or above-mentioned second delay unit.
It should be noted that above-mentioned 8th PMOS tube MP8, the 9th PMOS tube MP9, the tenth PMOS tube MP10, the 8th NMOS
Pipe MN8, the 9th NMOS tube MN9 and the first end of the tenth NMOS tube MN10 is source electrode, second end is drain electrode, control terminal is grid.
Above-mentioned tri-state Zero-cross comparator circuit provided in an embodiment of the present invention has strong antijamming capability, state controllable, reliable
The characteristics such as property height, and can be widely applied in power management chip.
On the basis of a kind of tri-state Zero-cross comparator circuit suitable for switching power circuit disclosed by the embodiments of the present invention,
The embodiment of the invention also discloses a kind of power management chips, including：Above-mentioned tri-state Zero-cross comparator circuit.
In conclusion an embodiment of the present invention provides a kind of tri-state Zero-cross comparator circuit and power management chip, it is suitable for
Switching power circuit, the tri-state Zero-cross comparator circuit include：Zero-cross comparator module, start-up study module, is born logic module output
To imbalance handover module and underloading detection module, wherein Zero-cross comparator module is used to compare the electricity of output end VOUT and the ends SW
Pressure generates logic level and overturns and control the shutdown of master power switch pipe；Start-up study module is used in DRVP signals be low, mistake
When zero balancing module is opened, generation is suitable to start sequential, generated during establishing to avoid the voltage disturbance at the ends SW
Accidentally turn over；Logic module output is used to the voltage that Zero-cross comparator module exports being converted to digital logic control signals；Negative current
Handover module of lacking of proper care is used for when load current is extremely low, and the overturning point of Zero-cross comparator module is set as negative current, plays protection
Effect.The tri-state Zero-cross comparator circuit provided through the invention can prevent zero passage detection signal in switch power supply power tube moment
False triggering during switching, and two kinds of protections of forward current offset and negative current offset can be simultaneously provided according to model selection and touched
Hair mechanism avoids master power switch pipe from being burned out, to protection power source managing chip.
It should be noted that each embodiment in this specification is described in a progressive manner, each embodiment weight
Point explanation is all difference from other examples, and the same or similar parts between the embodiments can be referred to each other.
Circuit proposed by the invention is exemplarily described above in association with attached drawing, the explanation of above example is
It is used to help understand core of the invention thought.For those of ordinary skill in the art, according to the thought of the present invention, specific
There will be changes in embodiment and application range.In conclusion the content of the present specification should not be construed as to the present invention's
Limitation.
The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention.
Various modifications to these embodiments will be apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, of the invention
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest range caused.
Claims (8)
1. a kind of tri-state Zero-cross comparator circuit, which is characterized in that be suitable for switching power circuit, the tri-state Zero-cross comparator circuit
Including：Zero-cross comparator module, logic module output, start-up study module, negative sense imbalance handover module and underloading detection module,
Wherein：
The Zero-cross comparator module includes first end, second end, third end, the 4th end, the 5th end, the 6th end and the 7th end；Institute
It includes first end, second end, third end and the 4th end to state start-up study module；The logic module output includes first end,
Two ends, third end and the 4th end；The negative sense imbalance handover module includes first end, second end and third end；The underloading inspection
It includes first end and second end to survey module；
Output end VOUT of the first end of the Zero-cross comparator module as the tri-state Zero-cross comparator circuit, the Zero-cross comparator
SW end of the second end of module as the tri-state Zero-cross comparator circuit；The third end of the Zero-cross comparator module and the startup
The second end of time delay module is connected, and the 4th end of the Zero-cross comparator module is connected with the third end of the start-up study module,
5th end of the Zero-cross comparator module is connected with the first end of negative sense imbalance handover module, the Zero-cross comparator module
6th end is connected with the second end of negative sense imbalance handover module, and the 7th end of the Zero-cross comparator module and the logic are defeated
The first end for going out module is connected, and lack of proper care the FPWM of handover module as the negative sense for the third end of negative sense imbalance handover module
Input terminal；
The second end of the logic module output is connected with the 4th end of the start-up study module, the logic module output
Third end is connected with the first end of the start-up study module, and the 4th end of the logic module output is as the tri-state zero passage
The output end of comparison circuit；
The underloading detection module is cut for detecting inductive current, output end and the negative sense imbalance of the underloading detection module
The third end for changing the mold block is connected, and is underloading and needs to be operated in PWM moulds when the underloading detection module detects the circuit current
When under formula, the output high level of the underloading detection module, otherwise, the output low level of the underloading detection module；
The Zero-cross comparator module is used for the voltage of the output end VOUT and the ends SW, generates logic level overturning simultaneously
Control the shutdown of master power switch pipe；
The start-up study module is used in DRVP signals be low, when the Zero-cross comparator module is opened, generates suitable start
Sequential is accidentally turned over to avoid the voltage disturbance at the ends SW caused by foundation in the process；
The logic module output is used to the voltage that the Zero-cross comparator module exports being converted to digital logic control signals；
The negative current imbalance handover module is used for when load current is extremely low, and the overturning point of the Zero-cross comparator module is set
For negative current, play a protective role.
2. circuit according to claim 1, which is characterized in that the Zero-cross comparator module includes：Current source (I), second
PMOS tube (MP2), the 4th PMOS tube (MP4), the 5th PMOS tube (MP5), the 6th PMOS tube (MP6), the 7th PMOS tube (MP7),
Second NMOS tube (MN2), third NMOS tube (MN3), the 6th NMOS tube (MN6), the 7th NMOS tube (MN7), wherein：
The first end of the current source (I), the first end of the 4th PMOS tube (MP4) and the 5th PMOS tube (MP5)
The common end of second end, the 7th PMOS tube (MP7) first end of the second end as the Zero-cross comparator module；Described
Second end of the second end of two PMOS tube (MP2) as the Zero-cross comparator module；The first end of 7th PMOS tube (MP7)
It is defeated as the 7th end of the Zero-cross comparator module and the logic with the common end of the first end of the 7th NMOS tube (MN7)
The first end for going out module is connected；
The first end of second PMOS tube (MP2) second end and the described 6th with the 4th PMOS tube (MP4) respectively
The second end of PMOS tube (MP6) is connected；The of the control terminal of 5th PMOS tube (MP5) and the 5th PMOS tube (MP5)
One end is connected, and common end is connected with the first end of the third NMOS tube (MN3), and the as the Zero-cross comparator module the 5th
The first end with negative sense imbalance handover module is held to be connected；
The control terminal of 7th PMOS tube (MP7) is connected with the first end of the 6th PMOS tube (MP6), and with the described 6th
The first end of NMOS tube (MN6) is connected；The control of the control terminal, the 6th NMOS tube (MN6) of 7th NMOS tube (MN7)
End, the control terminal of the third NMOS tube (MN3), the control terminal of second NMOS tube (MN2) are connected, as the zero passage ratio
The 6th end compared with module is connected with the second end of negative sense imbalance handover module；
The control terminal of second NMOS tube (MN2) is connected with the first end of second NMOS tube (MN2), the 2nd NMOS
The first end of pipe (MN2) is connected with the second end of the current source (I)；The second end of second NMOS tube (MN2), described
The second end of three NMOS tubes (MN3), the second end of the 6th NMOS tube (MN6) and the 7th NMOS tube (MN7)
Two ends are grounded；
Third end and the start delay module of the control terminal of second PMOS tube (MP2) as the Zero-cross comparator module
Second end be connected；The control terminal of 4th PMOS tube (MP4) is opened as the 4th end of the Zero-cross comparator module with described
The third end of dynamic Postponement module is connected.
3. circuit according to claim 1, which is characterized in that negative sense imbalance handover module includes：4th NMOS tube
(MN4) and the 5th NMOS tube (MN5), wherein：
First end and the Zero-cross comparator of the first end of 4th NMOS tube (MN4) as negative sense imbalance handover module
5th end of module is connected, and the control terminal of the 4th NMOS tube (MN4) is lacked of proper care the third end of handover module as the negative sense
Input FPWM；The second end of 4th NMOS tube (MN4) is connected with the first end of the 5th NMOS tube (MN5), and described
Second end and the six of the Zero-cross comparator module of the control terminal of five NMOS tubes (MN5) as negative sense imbalance handover module
End is connected；The second end of 5th NMOS tube (MN5) and ground connection.
4. circuit according to claim 1, which is characterized in that the logic module output includes：First phase inverter
(INV1), the second phase inverter (INV2), the first NAND gate (NAND1), the first nor gate (NOR1), the second nor gate (NOR2),
Wherein：
First end and the Zero-cross comparator mould of the input terminal of first phase inverter (INV1) as the logic module output
7th end of block is connected；First input of the output end of first phase inverter (INV1) and first NAND gate (NAND1)
End is connected；Second input terminal of first NAND gate (NAND1) is opened as the second end of the logic module output with described
4th end of dynamic time delay module is connected；The output end of first NAND gate (NAND1) and first nor gate (NOR1)
First input end is connected；
Second input terminal of second nor gate (NOR2) is connected with the first end of the start-up study module, described second or
The first input end of NOT gate (NOR2) is connected with the output end of first nor gate (NOR1), first nor gate (NOR1)
The second input terminal be connected with the output end of second nor gate (NOR2)；
The output end of first nor gate (NOR1) is connected with the input terminal of second phase inverter (INV2), and described second is anti-
Fourth end of the output end of phase device (INV2) as the logic module output.
5. circuit according to claim 1, which is characterized in that the start-up study module includes：First delay unit, the
Two delay units, third phase inverter (INV3) and the 4th phase inverter (INV4), wherein：
First end and the logic module output of the first end of first delay unit as the start-up study module
Third end is connected；The second end of first delay unit is anti-with the first end of second delay unit and the third respectively
The input terminal of phase device (INV3) is connected, and second end of the second end of first delay unit as the start-up study module
It is connected with the third end of the Zero-cross comparator module；The output end of the third phase inverter (INV3) is as the start-up study mould
The third end of block is connected with the 4th end of the Zero-cross comparator module；
The output end of second delay unit is connected with the input terminal of the 4th phase inverter (INV4), the 4th phase inverter
(INV4) output end is connected as the 4th end of the start-up study module with the second end of the logic module output.
6. circuit according to claim 5, which is characterized in that first delay unit and/or second delay are single
Member includes：5th phase inverter (INV5), hex inverter (INV6), the 7th phase inverter (INV7), resistance (RA), the first capacitance
(CA), first with door (AND1) and switching tube (MPA), wherein：
The input terminal of the hex inverter (INV6) as first delay unit and/or second delay unit
One end；The output end of the hex inverter (INV6) input terminal, the switch with the 7th phase inverter (INV7) respectively
The control terminal and described first for managing (MPA) are connected with the second input terminal of door (AND1)；
The output end of 7th phase inverter (INV7) and the resistance (RA) one end be connected, the resistance (RA) the other end
Respectively with the input terminal of the 5th phase inverter (INV5), the first capacitance (CA) one end and the switching tube (MPA)
First end be connected；The second end of the switching tube (MPA) is connected with power end (VDD), the first capacitance (CA) it is another
End ground connection；
The output of 5th phase inverter (INV5) is connected with described first with the first input end of door (AND1), described first with
Second end of the output end of door (AND1) as first delay unit and/or second delay unit.
7. circuit according to claim 5, which is characterized in that first delay unit and/or second delay are single
Member includes：8th phase inverter (INV8), the 9th phase inverter (INV9), the tenth phase inverter (INV10), the 11st phase inverter
(INV11), the 12nd phase inverter (INV12), the 8th PMOS tube (MP8), the 9th PMOS tube (MP9), the tenth PMOS tube (MP10),
8th NMOS tube (MN8), the 9th NMOS tube (MN9), the tenth NMOS tube (MN10) and the second capacitance (CB), wherein：
The input terminal of 8th phase inverter (INV8) as first delay unit and/or second delay unit
One end；The output end of 8th phase inverter (INV8) is connected with the input terminal of the 9th phase inverter (INV9), and the described 9th
The output end of phase inverter (INV9) respectively with the control terminal of the 8th NMOS tube (MN8) and the tenth phase inverter (INV10)
Input terminal be connected；
The output end of tenth phase inverter (INV10) is connected with the control terminal of the tenth NMOS tube (MN10), and the described 8th
The first end of NMOS tube (MN8) is connected with the first end of the 8th PMOS tube (MP8), and the of the 8th PMOS tube (MP8)
One end is connected with the control terminal of the 8th PMOS tube (MP8), the second end of the 8th PMOS tube (MP8), the described 9th
The second end of PMOS tube (MP9) and the second end of the tenth PMOS tube (MP10) are connected with power end (VDD), and the described tenth
The control terminal of PMOS tube (MP10) is connected with the output end of the 11st phase inverter (INV11)；
The second end of 8th NMOS tube (MN8) is connected with the first end of the 9th NMOS tube (MN9), the 9th NMOS
The control terminal of pipe (MN9) is connected with the output end of the 11st phase inverter (INV11)；The of 9th NMOS tube (MN9)
The second end of two ends and the tenth NMOS tube (MN9) is grounded；
The control terminal of 8th PMOS tube (MP8) is connected with the control terminal of the 9th PMOS tube (MP9), the 9th PMOS
Manage the first end phase of the first end of (MP9) and the first end and the tenth NMOS tube (MN10) of the tenth PMOS tube (MP10)
Even；The first end of tenth NMOS tube (MN10) respectively with the input terminal of the 11st phase inverter (INV11) and described
Two capacitance (CB) one end be connected, the output end of the 11st phase inverter (INV11) and the 12nd phase inverter (INV12)
Input terminal be connected, the second capacitance (CB) the other end ground connection；The output end conduct of 12nd phase inverter (INV12)
The second end of first delay unit and/or second delay unit.
8. a kind of power management chip, which is characterized in that including：Tri-state zero passage described in the claims 1-7 any one
Comparison circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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| CN114337619A (en) * | 2022-01-12 | 2022-04-12 | 电子科技大学 | Reverse flow comparator for eliminating error turnover |
| CN114337619B (en) * | 2022-01-12 | 2023-04-28 | 电子科技大学 | Reverse flow comparator capable of eliminating false overturn |
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