CN114337619A - Reverse flow comparator for eliminating error turnover - Google Patents

Reverse flow comparator for eliminating error turnover Download PDF

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Publication number
CN114337619A
CN114337619A CN202210034300.6A CN202210034300A CN114337619A CN 114337619 A CN114337619 A CN 114337619A CN 202210034300 A CN202210034300 A CN 202210034300A CN 114337619 A CN114337619 A CN 114337619A
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nmos transistor
input
gate
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drain
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CN114337619B (en
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罗萍
杨楠
宋浩
陈嘉豪
王浩
樊捷
何致远
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University of Electronic Science and Technology of China
Guangdong Electronic Information Engineering Research Institute of UESTC
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Guangdong Electronic Information Engineering Research Institute of UESTC
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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Abstract

The invention discloses a reflux comparator for eliminating false inversion, belonging to the technical field of integrated circuits. The device comprises an advance turning point setting module, a current zero-crossing comparison module and a logic module. The turning point setting module provides bias voltage for the current zero-crossing comparison module when the power supply is established. The current zero-crossing comparison module utilizes offset voltage of the offset geminate transistor to lead the output to be overturned in advance when certain offset exists between the source end voltage input SW of the input common-gate transistor and the ground level so as to compensate the response delay of the system; an enabling tube is added to eliminate the phenomenon of mistaken overturning of the output. And the logic module generates an enabling control signal of the early turning point setting module and the current zero-crossing comparison module and an output signal of the reverse flow comparator through logic gate combination. The invention provides a reflux comparator for eliminating false inversion based on small bias current, which has a simple structure and solves the problems that the output response is slow and false inversion is easy to occur in the conventional reflux comparator under the small bias current.

Description

Reverse flow comparator for eliminating error turnover
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a reverse flow comparator for eliminating false inversion with small bias current.
Background
Synchronous rectifier switching converters often require a reflux comparator to determine when to switch upper and lower tubes. In the Buck switching converter shown in fig. 1, the upper tube MP and the lower tube MN of the power switching tube are alternately turned on in a switching period, and when MP is turned on, a current I flowing through an inductorLRising, when MN is on, the inductive current ILAnd (4) descending. The point at which the drain of the upper tube MP is connected with the drain of the lower tube MN is SW, and the voltage V isSWAnd the inductive current ILAs shown in fig. 2, after the inductor current is decreased to 0 and reverse, the efficiency of the converter is reduced, so that it is necessary to avoid the occurrence of reverse flow. Reflux comparators require accurate detection of the reflux point while also requiring a faster response. Under the condition of a small bias current, the reflux comparator outputs a slow response and is easy to have the phenomenon of error overturning. And the improved reverse flow comparator increases the complexity of the circuit and the working current in order to eliminate the false upset phenomenon and improve the response speed.
Disclosure of Invention
Aiming at the defects that the reverse flow comparison circuit is slow in response or easy to generate false inversion, the invention provides a reverse flow comparison circuit which is simple in structure and based on smaller bias current and is used for eliminating the false inversion.
The technical scheme of the invention is as follows:
the utility model provides a palirrhea comparison circuit of mistake upset of elimination of less bias current, includes trip point setting module, current zero crossing comparison module, logic module in advance:
the early turning point setting module is used for providing bias voltage for the current zero-crossing comparison module when a power supply is established and adjusting an output turning point;
the current zero-crossing comparison module adopts a common-grid amplification structure, and utilizes the offset of an input stage to enable the turning point to be a smaller negative pressure: vSW＝-VOSSo as to compensate the response delay of the system; and the phenomenon of output error overturning is eliminated by adding the enabling tube.
The logic module generates a control signal of the switching tube and shapes the output into a standard digital logic signal through a series of NAND gates, NOR gates and inverters.
Specifically, the current zero-crossing comparison module comprises a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a first resistor R1 and a second resistor R2; the logic module provides a third enabling signal for the early trip point setting module and provides a fourth enabling signal for the current zero-crossing comparison module; the source electrode of the first PMOS tube MP1 is connected with the power supply, the grid electrode thereof is connected with an external first enable signal, and the drain electrode thereof is connected with the drain electrode of the second PMOS tube MP 2; the source electrode of the second PMOS pipe MP2 is connected with the power supply, and the grid electrode and the drain electrode are interconnected; the source electrode of the third PMOS tube MP3 is connected with the power supply, and the grid electrode of the third PMOS tube MP3 is connected with the drain electrode of the first PMOS tube MP 1; the drain electrode of the first NMOS transistor MN1 is connected with the source electrode of the second NMOS transistor MN2, the grid electrode of the first NMOS transistor is connected with an external second enabling signal, and the source electrode of the first NMOS transistor is grounded; the drain of the second NMOS transistor MN2 is connected to the drain of the second PMOS transistor MP2, and the gate of the second NMOS transistor MN2 is connected to the first bias voltage VB 1; the drain of the third NMOS transistor MN3 is connected to the drain of the third PMOS transistor MP3, and the gate of the third NMOS transistor MN3 is connected to the second bias voltage; the drain of the fourth NMOS transistor MN4 is connected to the source of the second NMOS transistor MN2, the gate of the fourth NMOS transistor MN4 is connected to the fourth enable signal, and the source is grounded to VSS through the first resistor R1; the drain of the fifth NMOS transistor MN4 is connected to the source of the third NMOS transistor MN3, the gate of the fifth NMOS transistor MN5 is connected to the fourth enable signal, and the source thereof passes through the second resistor R2 and then becomes the input point, i.e., SW; the drain of the sixth NMOS transistor MN6 is connected to the drain of the third PMOS transistor MP3, the gate of the sixth NMOS transistor NN6 is connected to the external second enable signal, and the source thereof is grounded.
When the gate of the sixth NMOS transistor MN6 is pulled low, the offset voltage of the gate voltage of the second NMOS transistor MN2 and the gate voltage of the third NMOS transistor MN3 exists, so that when the SW potential rises from a negative value to a value slightly lower than VSS, the drain output of the third NMOS transistor MN3 is inverted, and the advanced inversion can compensate the system delay. When the gate of the sixth NMOS transistor MN6 is pulled high, the node V can be pulled high1Pulling down is carried out, so that when the grid of the first NMOS transistor MN1 is pulled up, the voltage of the drain end of the fourth NMOS transistor MN4 is reduced, the drain-source current of the second NMOS transistor MN2 is increased, the current flowing through a current mirror formed by the second PMOS transistor MP2 and the third NMOS transistor MN3 is increased, and the node V is caused1Rising to generate false overturning phenomenon.
Specifically, the logic module comprises a first two-input NOR gate NOR1, a second two-input NOR gate NOR2, a first inverter INV1, a second inverter INV2, a third inverter INV3, a first two-input NAND gate NAND1, a first capacitor C1, and a third resistor R3; the input of the first inverter INV1 is an external first enable signal, the output of the first inverter INV1 is connected to one input terminal of the first two-input NOR gate NOR1, the output of the first inverter INV1 is also a third enable signal, the other end of the first two-input NOR gate NOR1 is connected to an external second enable signal, and the output of the first two-input NOR gate NOR1 is connected to the input of the second inverter INV2 and is also a fourth enable signal; the output of the second inverter INV2 is connected through a third resistor R3 and then connected with the input of the third inverter INV3, the first capacitor C1 and the third resistor R3 are connected in series, the capacitor end of the series branch is connected with the ground VSS, the output of the third inverter INV3 is connected with one input end of a first two-input NAND gate NAND1, the other end of the first two-input NAND gate 1 is connected with the drain voltage of a third PMOS transistor MP3, the output of the first two-input NAND gate NAND1 is connected with one input end of a second two-input NOR gate NOR2, the other input end of the second two-input NOR gate NOR2 is connected with an external second enable signal, and the output of the second two-input NOR gate NOR2 is the output V of the reflux comparison circuitO。
The invention has the beneficial effects that: the invention provides a reflux comparator for eliminating false inversion based on small bias current, which has a simple structure and solves the problems that the output response is slow and false inversion is easy to occur in the conventional reflux comparator under the small bias current.
Drawings
Fig. 1 is a block diagram of a Buck-type switching converter.
Fig. 2 is a voltage-inductor current relationship diagram of the SW point of the Buck-type switching converter.
Fig. 3 is a block diagram of a general structure of a reflux comparator for eliminating false flip according to the present invention.
Fig. 4 is a schematic diagram of the output of the early rollover point setting module in an example.
Fig. 5 is a circuit configuration diagram of a current zero crossing comparison module in an example.
Fig. 6 is a circuit configuration diagram of a logic block in an example.
Fig. 7 is a graph of the output voltage-input voltage relationship of a reflux comparator for eliminating false inversion according to the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made with reference to the accompanying drawings.
In a buck switching converter as in fig. 1, the voltage V at the relevant SW pointSWAnd the inductive current ILAs shown in fig. 2, the efficiency of the converter is reduced due to the reverse of the inductor current, so that the occurrence of reverse current needs to be avoided, i.e. a reverse current comparator is required to detect and generate the flag signal.
The general structural block diagram of the reflux comparator for eliminating false inversion provided by the invention is shown in fig. 3, and comprises an early inversion point setting module, a current zero-crossing comparison module and a logic module. The turning point setting module provides bias voltage for the current zero-crossing comparison module when the power supply is established. And the current zero-crossing comparison module utilizes offset voltage of the offset geminate transistor to ensure that the output is turned over in advance when certain offset exists between the voltage input SW of the input common-gate transistor and the ground level so as to compensate the system delay. And the logic module generates a switch control signal and a final output signal through logic gate combination. The reflux comparator provided by the invention can be manufactured into an integrated circuit by adopting a standard CMOS (complementary metal oxide semiconductor) process. The circuit structure and connection relationship of the modules are described below, respectively.
EN1 is an enable signal when the Buck circuit works, and is active high. EN2 is an enabling signal related to the grid drive of a down tube NMOS tube in a Buck circuit, and is active low. Input bias current I of forward turning point setting moduleBWhen the enable signal EN3 generated by the logic module is low and effective, the bias voltage V is provided for the current zero-crossing comparison moduleB1、VB2V is shown in the schematic diagram of FIG. 4B1Is slightly larger than VB2. In the current zero-crossing comparison module, when an enable signal EN4 generated by the logic module is high and effective, SW is compared with the ground potential VSS to generate an output V1To the logic module, shaping to generate pulse output VO。
Fig. 5 shows an implementation form of the current zero-crossing comparison module, which includes a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a resistor R1, and a resistor R2. Wherein the gate of the second NMOS transistor MN2 is connected to VB1The source of the NMOS transistor is connected with the drain of a fourth NMOS transistor MN4 and the drain of a first NMOS transistor MN1, and the gate of a third NMOS transistor MN3 is connected with VB2And the source of the NMOS transistor is connected with the drain of the fifth NMOS transistor MN 5. The gate of the fourth NMOS transistor MN4 and the gate of the fifth NMOS transistor MN5 are connected to the node EN4 in the logic module, the source of the fourth NMOS transistor MN4 is connected to VSS through a resistor R1, and the source of the fifth NMOS transistor MN5 is connected to SW through a resistor R2. The gate of the first PMOS transistor MP1 is connected to the node EN1 in the logic block. The grid electrode of the second PMOS tube MP2 is connected with the drain electrode, the grid electrode of the third PMOS tube MP3, the drain electrode of the second NMOS tube MN2 and the drain electrode of the first PMOS tube MP1, and the source electrode of the first PMOS tube MP1 is connected with the source electrode of the second PMOS tube MP2 and the source electrode of the third PMOS tube MP3 to VDD. The drain of the third PMOS transistor MP3 is connected to the drain of the third NMOS transistor MN3, the drain of the sixth NMOS transistor MN6, and is connected to the node V in the logic module1. The gates of the first NMOS transistor MN1 and the sixth NMOS transistor MN6 are connected to a node EN2 in the logic module, and the sources of the first NMOS transistor MN1 and the sixth NMOS transistor MN6 are connected to VSS.
Control at the gate of the first PMOS transistor MP1When the signal EN1 is high, the comparator operates normally. When the grid of the sixth NMOS transistor MN6 is pulled down, the offset voltage of the grid voltage of the second NMOS transistor MN2 and the grid voltage of the third NMOS transistor MN3 exists, VB1Is slightly larger than VB2When the SW voltage rises from a negative value to a value slightly lower than VSS, the drain output of the third NMOS transistor MN3 is inverted, where the early inversion can compensate the system delay. When the gate of the sixth NMOS transistor MN6 is pulled high, the node V can be pulled high1Pulling down is carried out, so that when the grid of the first NMOS transistor MN1 is pulled up, the voltage of the drain end of the fourth NMOS transistor MN4 is reduced, the drain-source current of the second NMOS transistor MN2 is increased, the current flowing through a current mirror formed by the second PMOS transistor MP2 and the third NMOS transistor MN3 is increased, and the node V is caused1Rising to generate false overturning phenomenon.
Fig. 6 shows an implementation form of the logic module, which includes a first two-input NOR gate NOR1, a second two-input NOR gate NOR2, a first inverter INV1, a second inverter INV2, a third inverter INV3, a first two-input NAND gate NAND1, a first capacitor C1, and a resistor R3. The input of the first inverter INV1 is EN1, the output of the first inverter INV1 is connected to one end input of the first two-input NOR gate NOR1, i.e. the node EN3, the other end input of the first two-input NOR gate NOR1 is connected to EN2, the output of the first two-input NOR gate NOR1 is connected to the input of the second inverter INV2, i.e. the node EN4, the output of the second inverter INV2 is connected to the positive terminal of the resistor R3, and the negative terminal of the resistor R3 is connected to VSS through the capacitor C1. The negative terminal of the resistor R3 is connected to the input of the third inverter INV3, the output of the third inverter INV3 is connected to one input of the first two-input NAND gate NAND1, the other input of the first two-input NAND gate NAND1 is EN2, the output of the first two-input NAND gate NAND1 is connected to one input of the second two-input NOR gate NOR2, the other input of the second two-input NOR gate NOR2 is connected to EN2, and the output of the second two-input NOR gate NOR2 is the output V of the reverse current comparison circuitO。
The invention provides a reverse flow comparator for eliminating false inversion, which is characterized in that an enable signal EN1 is high, an enable signal EN2 is low, and an input voltage V isSW＝-VOSThe output toggles early, and the subsequent enable signal EN2When the flip-up occurs, the output will not be flipped over, as shown in the schematic diagram of output-input of the reflux comparator in FIG. 7, VOIs a V1And outputting the pulse shaped by the logic module. Therefore, the invention can detect the reflux condition and overturn in advance under the normal working condition, and is suitable for the working occasions needing to detect the reflux and compensate the response delay of the subsequent system in the switch power supply system.

Claims (3)

1. A reflux comparator for eliminating false inversion is characterized by comprising an early inversion point setting module, a current zero-crossing comparison module and a logic module;
the early turning point setting module is used for providing bias voltage for the current zero-crossing comparison module when a power supply is established and adjusting an output turning point;
the current zero-crossing comparison module adopts a common-grid amplification structure, and utilizes the offset of the input stage to enable the turning point to be negative pressure so as to compensate the response delay of the system;
the logic module generates enabling signals of the advance turning point setting module and the current zero-crossing comparison module through a logic circuit device and shapes the output into a standard digital logic signal.
2. The reflux comparator for eliminating false upset of claim 1, wherein the current zero-crossing comparison module comprises a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a first resistor R1 and a second resistor R2; the logic module provides a third enabling signal for the early trip point setting module and provides a fourth enabling signal for the current zero-crossing comparison module; the source electrode of the first PMOS tube MP1 is connected with the power supply, the grid electrode thereof is connected with an external first enable signal, and the drain electrode thereof is connected with the drain electrode of the second PMOS tube MP 2; the source electrode of the second PMOS pipe MP2 is connected with the power supply, and the grid electrode and the drain electrode are interconnected; the source electrode of the third PMOS tube MP3 is connected with the power supply, and the grid electrode of the third PMOS tube MP3 is connected with the drain electrode of the first PMOS tube MP 1; the drain electrode of the first NMOS transistor MN1 is connected with the source electrode of the second NMOS transistor MN2, the grid electrode of the first NMOS transistor is connected with an external second enabling signal, and the source electrode of the first NMOS transistor is grounded; the drain of the second NMOS transistor MN2 is connected to the drain of the second PMOS transistor MP2, and the gate of the second NMOS transistor MN2 is connected to the first bias voltage VB 1; the drain of the third NMOS transistor MN3 is connected to the drain of the third PMOS transistor MP3, and the gate of the third NMOS transistor MN3 is connected to the second bias voltage; the drain of the fourth NMOS transistor MN4 is connected to the source of the second NMOS transistor MN2, the gate of the fourth NMOS transistor MN4 is connected to the fourth enable signal, and the source is grounded to VSS through the first resistor R1; the drain of the fifth NMOS transistor MN4 is connected to the source of the third NMOS transistor MN3, the gate of the fifth NMOS transistor MN5 is connected to the fourth enable signal, and the source thereof passes through the second resistor R2 and then becomes the input point, i.e., SW; the drain of the sixth NMOS transistor MN6 is connected to the drain of the third PMOS transistor MP3, the gate of the sixth NMOS transistor NN6 is connected to the external second enable signal, and the source thereof is grounded.
3. The reflux comparator for eliminating false upset as claimed in claim 2, wherein the logic module comprises a first two-input NOR gate NOR1, a second two-input NOR gate NOR2, a first inverter INV1, a second inverter INV2, a third inverter INV3, a first two-input NAND gate NAND1, a first capacitor C1, and a third resistor R3; the input of the first inverter INV1 is an external first enable signal, the output of the first inverter INV1 is connected to one input terminal of the first two-input NOR gate NOR1, the output of the first inverter INV1 is also a third enable signal, the other end of the first two-input NOR gate NOR1 is connected to an external second enable signal, and the output of the first two-input NOR gate NOR1 is connected to the input of the second inverter INV2 and is also a fourth enable signal; the output of the second inverter INV2 is connected through a third resistor R3 and then connected to the input of the third inverter INV3, the first capacitor C1 and the third resistor R3 are connected in series, the capacitor end of the series branch is connected to VSS, the output of the third inverter INV3 is connected to one input end of a first two-input NAND gate NAND1, the other end of the first two-input NAND gate 1 is connected to the drain voltage of the third PMOS transistor MP3, the output of the first two-input NAND gate NAND1 is connected to one input end of a second two-input NOR gate NOR2, the other input end of the second two-input NOR gate NOR2 is connected to an external second enable signal, and the output of the second two-input NOR gate NOR2 is the output of the reflux comparison circuit.
CN202210034300.6A 2022-01-12 2022-01-12 Reverse flow comparator capable of eliminating false overturn Active CN114337619B (en)

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Cited By (1)

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