CN113422594A - Dynamic comparator - Google Patents

Dynamic comparator Download PDF

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Publication number
CN113422594A
CN113422594A CN202110762073.4A CN202110762073A CN113422594A CN 113422594 A CN113422594 A CN 113422594A CN 202110762073 A CN202110762073 A CN 202110762073A CN 113422594 A CN113422594 A CN 113422594A
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transistors
preamplifier
comparator
drains
transistor
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CN113422594B (en
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包军林
郝丹阳
汤华莲
张丽
刘伟峰
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Shaanxi Huaxin Fukang Biotechnology Co.,Ltd.
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Xidian University
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
    • H03K5/2481—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors with at least one differential stage

Abstract

The invention discloses a dynamic comparator, which comprises a cascade preamplifier and a latch. According to the dynamic comparator, only one clock control signal is needed to complete resetting and comparison, the time sequence of the comparator is simplified, power consumption and area are saved, meanwhile, the preamplifier adopts a positive feedback mode, the output of the preamplifier amplifies input signals in an exponential mode, transmission delay is obviously reduced, and the design requirement of the high-speed high-precision comparator is met.

Description

Dynamic comparator
Technical Field
The invention relates to the technical field of electronic circuits, in particular to a dynamic comparator.
Background
The comparator is used as a key component module of a successive approximation register analog-to-digital converter (sar ADC), and each performance of the comparator has a very important influence on the ADC. With the rapid development of modern technologies, data to be processed is increasing, and the processing speed and resolution of the ADC are also increasing to match the application, which makes the internal comparator circuit have higher requirements on speed and precision.
In the working process of the sar adc, the comparator needs to compare the voltage on the capacitor array and output the comparison result to the digital logic module, so that the circuit outputs a correct digital code and feeds back the digital code to the control switch on the capacitor array, the comparator compares the changed voltage value, and the output result is used to control the next successive approximation until the whole decoding period is finished.
However, with the progress and development of deep submicron technology, the technology size is continuously reduced, and the device mismatch becomes more and more serious, which results in the increase of the offset voltage of the ADC input terminal, and reduces the precision of the comparator, making it not favorable for application in high precision occasions. Therefore, it is of great significance to provide a high-speed high-precision comparator.
Disclosure of Invention
The embodiment of the invention provides a dynamic comparator, which is used for solving the problems that the offset voltage of an input end of an ADC (analog to digital converter) is increased and the precision of the comparator is reduced due to device mismatch in the prior art.
In one aspect, an embodiment of the present invention provides a dynamic comparator, including: the preamplifier and the latch are cascaded;
the preamplifier is provided with transistors Mp1, Mp2, Mp3, Mp4, Mp5, Mn1, Mn2, Mn3, Mn4, Mn5 and Mn6, and the sources of the transistors Mp3, Mp4 and Mp5 are all connected with a power supply VDDThe drains of the transistors Mp3 and Mp5 are respectively connected with the N output end and the P output end of the preamplifier, and the gates of the transistors Mp3, Mp4 and Mp5 are all connected with a clock control signal;
the gates and the drains of the transistors Mn1 and Mn2 are connected with the drain of the transistor Mp4, and the sources of the transistors Mn1 and Mn2 are respectively connected with the N output end and the P output end of the preamplifier;
the sources of the transistors Mp1 and Mp2 are connected with the drain of the transistor Mp4, the drains of the transistors Mp1 and Mp2 are respectively connected with the N output end and the P output end of the preamplifier, and the gates of the transistors Mp1 and Mp2 are respectively connected with the input signals VIN and VIP;
the gates of the transistors Mn3 and Mn4 are respectively connected with the P output end and the N output end of the preamplifier, the drains of the transistors Mn3 and Mn4 are respectively connected with the N output end and the P output end of the preamplifier, and the sources of the transistors Mn3 and Mn4 are both grounded;
the drains of the transistors Mn5 and Mn6 are respectively connected with the N output end and the P output end of the preamplifier, the gates of the transistors Mn5 and Mn6 are both connected with a clock control signal, and the sources of the transistors Mn5 and Mn6 are both grounded.
In one possible implementation, the transistors Mp3 and Mp5 are smaller in size than the transistor Mp 4.
In a possible implementation mode, the latch is provided with transistors Mp6, Mp7, Mp8, Mp9, Mp10, Mp11, Mn7, Mn8, Mn9 and Mn10, and the sources of the transistors Mp6 and Mp7 are connected with a power supply VDDThe drains of the transistors are respectively connected with the drains of the transistors Mn9 and Mn10, the gates of the transistors Mp6 and Mp7 are respectively connected with the gates of the transistors Mn9 and Mn10, the sources of the transistors Mn9 and Mn10 are respectively connected with the drains of the transistors Mn7 and Mn8, the gates of the transistors Mn7 and Mn8 are respectively connected with the N input end and the P input end of the latch, and the sources of the transistors Mn7 and Mn8 are both grounded; the drains of the transistors Mp6 and Mp7 output comparison result signals VON and VOP, respectively; the sources of the transistors Mp8 and Mp9 are connected with a power supply VDDThe grid is respectively connected with the N input end and the P input end of the latch, and the drain is respectively connected with the drains of the transistors Mp6 and Mp 7; the sources of the transistors Mp10 and Mp11 are connected with a power supply VDDThe gates are connected to the N and P inputs of the latch, respectively, and the drains are connected to the sources of transistors Mn9 and Mn10, respectively.
In one possible implementation, the gate of the transistor Mp6 is connected to the drain of the transistor Mp7, and the drain of the transistor Mp6 is connected to the gate of the transistor Mp 7.
In one possible implementation, the drain of the transistor Mp6 and the drain of the transistor Mp7 are connected through a capacitor CLNAnd CLPAnd (4) grounding.
The dynamic comparator has the following advantages:
the adopted fast amplification comparator based on positive feedback obviously saves voltage margin and meets the requirement of low-voltage operation because only 3 transistors are stacked. The reset and the comparison can be completed by only one clock control signal, so that the time sequence of the comparator is simplified, and the power consumption and the area are saved. The transmission delay of the dynamic comparator mainly comes from the preamplifier, and the preamplifier adopted by the invention uses positive feedback, so that the output of the preamplifier amplifies an input signal in an exponential mode, the transmission delay is obviously reduced, and the design requirement of the high-speed high-precision comparator is met. Because the tail current source of the latch is formed by two NMOS tubes, the preamplifier and the latch almost have no static power consumption when the clock control signal CLK is at a high level.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a circuit diagram of a comparator in the prior art;
FIG. 2 is a circuit diagram of a dynamic comparator according to an embodiment of the present invention;
FIG. 3 is a waveform diagram illustrating the response of a dynamic comparator to a differential sine input according to an embodiment of the present invention;
FIG. 4 is a simulated waveform diagram of the dynamic comparator at 20 μ V input according to the embodiment of the present invention;
fig. 5 is a waveform diagram of a delay simulation of a dynamic comparator according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
A prior art dynamic comparator is shown in fig. 1, which is formed by a preamplifier and a latch in series. The preamplified regenerative latched comparator of fig. 1 is faster than the regenerative comparator due to the addition of the preamplifier, and the preamplifier lowers the comparator outputThe offset voltage at the input end improves the resolution of the comparator. The main principle is that when the input signal is small, the preamplifier amplifies the input signal to a value which can make the latch quickly respond, then the input voltage difference is quickly enlarged through positive feedback to quickly obtain the result, and the final end of two output ends outputs high level VDDAnd the other end outputs a low level GND. The pre-amplification regeneration latch comparator only has dynamic power consumption and no static power consumption, so the power consumption is low. However, the amplifier needs to use two clock control signals, which consumes time sequence resources, and the transmission delay between the preamplifier and the latch is also large, resulting in a low processing speed of the comparator.
Aiming at the problems in the prior art, the invention provides a dynamic comparator, wherein transistors Mn1, Mn2, Mp3 and Mp5 are added in a preamplifier, so that the preamplifier amplifies an input signal in a positive feedback mode, transmission delay is greatly reduced, and meanwhile, only one clock control signal is needed in the whole circuit, so that time sequence resources are saved.
Fig. 2 is a circuit diagram of a dynamic comparator according to an embodiment of the present invention. The invention provides a dynamic comparator, comprising: the preamplifier and the latch are cascaded;
the preamplifier is provided with transistors Mp1, Mp2, Mp3, Mp4, Mp5, Mn1, Mn2, Mn3, Mn4, Mn5 and Mn6, and the sources of the transistors Mp3, Mp4 and Mp5 are all connected with a power supply VDDThe drains of the transistors Mp3 and Mp5 are respectively connected with the N output end and the P output end of the preamplifier, and the gates of the transistors Mp3, Mp4 and Mp5 are all connected with a clock control signal;
the gates and the drains of the transistors Mn1 and Mn2 are connected with the drain of the transistor Mp4, and the sources of the transistors Mn1 and Mn2 are respectively connected with the N output end and the P output end of the preamplifier;
the sources of the transistors Mp1 and Mp2 are connected with the drain of the transistor Mp4, the drains of the transistors Mp1 and Mp2 are respectively connected with the N output end and the P output end of the preamplifier, and the gates of the transistors Mp1 and Mp2 are respectively connected with the input signals VIN and VIP;
the gates of the transistors Mn3 and Mn4 are respectively connected with the P output end and the N output end of the preamplifier, the drains of the transistors Mn3 and Mn4 are respectively connected with the N output end and the P output end of the preamplifier, and the sources of the transistors Mn3 and Mn4 are both grounded;
the drains of the transistors Mn5 and Mn6 are respectively connected with the N output end and the P output end of the preamplifier, the gates of the transistors Mn5 and Mn6 are both connected with a clock control signal, and the sources of the transistors Mn5 and Mn6 are both grounded.
Illustratively, the dynamic comparator of the invention forms an amplifying circuit in a positive feedback form by a plurality of transistors, and can rapidly amplify input VIN and VIP signals in an exponential form, thereby obviously reducing transmission delay. And by adding the transistors Mp3, Mp5, Mn1 and Mn2, the positive feedback establishment time of the preamplifier is shortened, and the processing speed of the dynamic comparator is further improved.
In one possible embodiment, the latch has transistors Mp6, Mp7, Mp8, Mp9, Mp10, Mp11, Mn7, Mn8, Mn9 and Mn10, and the sources of the transistors Mp6 and Mp7 are connected with a power supply VDDThe drains of the transistors are respectively connected with the drains of the transistors Mn9 and Mn10, the gates of the transistors Mp6 and Mp7 are respectively connected with the gates of the transistors Mn9 and Mn10, the sources of the transistors Mn9 and Mn10 are respectively connected with the drains of the transistors Mn7 and Mn8, the gates of the transistors Mn7 and Mn8 are respectively connected with the N input end and the P input end of the latch, and the sources of the transistors Mn7 and Mn8 are both grounded; the drains of the transistors Mp6 and Mp7 output comparison result signals VON and VOP, respectively; the sources of the transistors Mp8 and Mp9 are connected with a power supply VDDThe grid is respectively connected with the N input end and the P input end of the latch, and the drain is respectively connected with the drains of the transistors Mp6 and Mp 7; the sources of the transistors Mp10 and Mp11 are connected with a power supply VDDThe gates are connected to the N and P inputs of the latch, respectively, and the drains are connected to the sources of transistors Mn9 and Mn10, respectively.
In one possible embodiment, the gate of the transistor Mp6 is connected to the drain of the transistor Mp7, and the drain of the transistor Mp6 is connected to the gate of the transistor Mp 7.
In one possible embodiment, the drain of the transistor Mp6 and the drain of the transistor Mp7 are connected through a capacitor CLNAnd CLPAnd (4) grounding.
Illustratively, the work flow of the dynamic comparator is as follows:
when the clock control signal CLK is high, the comparator is in a reset state. At this time, the transistors Mp3, Mp4, and Mp5 are off, and thus there is no static power consumption. The transistors Mn5 and Mn6 are turned on to pull down the voltages Vfn and Vfp to low levels, respectively, the transistors Mn7 and Mn8 are turned off, and the transistors Mp8 and Mp9 are turned on to increase the output comparison result signals VOP and VON to the power supply voltage VDD. The transistors Mp10 and Mp11 turn on, pulling up the voltages V1 and V2, respectively, to the supply voltage VDDAvoiding the capacitor C in the comparison processLNAnd CLPIncomplete discharge causes mismatch, resulting in erroneous results.
When the clock control signal CLK is low, the comparator is in a comparison state. At this time, the transistors Mp3, Mp4, and Mp5 are turned on, and Mn5 and Mn6 are turned off. The transistors Mp3 and Mp5 are smaller than Mp4, and are used for accelerating the establishment of the voltage signals Vfp and Vfn and accelerating the conduction of the transistors Mn3 and Mn4, so that the preamplifier can quickly enter a positive feedback mode. The transistors Mn1 and Mn2 function the same as the transistors Mp3 and Mp 5. Setting input signal VIP>VIN, the current flowing through the transistor Mp1 is larger than the current flowing through the transistor Mp2, the voltage Vfp increases faster than Vfn, the voltage Vfn is rapidly pulled down to the low level GND after the transistor Mn4 is turned on, and the transistor Mn3 is turned off. The voltage Vfp reaches the threshold voltage of the transistor Mn7 first, the transistor Mn7 starts to conduct, the discharge speed of the comparison result signal VON through the transistors Mn7 and Mn9 is larger than the discharge speed of the comparison result signal VOP through the transistors Mn8 and Mn10, finally the transistor Mp7 is enabled to conduct before the transistor Mp6, and the comparison result signal VOP is raised to the power supply voltage VDDThe transistor Mp6 is always turned off, and the comparison result signal VON is pulled down to the low level GND to obtain the comparison result.
It should be noted that, although the increase of the transistors Mp3 and Mp5 can reduce the setup time of the positive feedback of the preamplifier, it increases the power consumption generated in the comparison stage, so that a compromise needs to be made between the overall power consumption and the processing speed of the comparator. The introduction of the transistors Mn1 and Mn2 can also reduce the setup time of the preamplifier positive feedback, but reduces the gain of the preamplifier, directly affects the precision of the comparator, and requires a compromise between precision and speed. Increasing the size of the transistors Mn7 and Mn8 in the tail current source of the latch of the comparator effectively reduces the setup time of the latch and thus reduces the comparison delay of the latch, but also increases the output load of the preamplifier and increases the comparison delay of the preamplifier, requiring a compromise between the comparison delay of the latch and the delay of the preamplifier. Increasing the size of the clock load transistors Mn5 and Mn6 can reduce the reset delay of the comparator, but increase the clock load, and require a clock control signal with larger driving capability, and at the same time increase the load size of the preamplifier, which affects the comparison delay of the comparator, so a compromise needs to be made between the reset delay of the comparator and the clock driving capability and the comparison speed.
Description of the simulation
Comparator function test conditions: supply voltage VDDThe voltage is 1.2V, the common mode voltage in the input signal is 600mV, the differential mode voltage is provided by a sinusoidal signal, the amplitude is 60mV, the frequency is 200MHz, and the clock control signal CLK adopts a pulse signal and has the frequency of 1.8 GHz.
Simulation results as shown in fig. 3, when CLK is high, the comparator is in a reset state, and the output terminal is kept at a high level of 1.2V. When the clock signal CLK changes to low level, the comparator is in comparison state, compares two signals of the input end to obtain the comparison result. As can be seen from the figure, when VIN > VIP, the output terminal VOP is at high level 1.2V, and VON switches back and forth between 0V and 1.2V with clock variation; when VIN < VIP, the output VOP switches back and forth between 1.2V and 0V, and VON is high level 1.2V, which conforms to the logic relationship. In fig. 3, the abscissa represents time in ns and the ordinate represents voltage, where CLK, VON and VOP are all in V and VIP and VIN are all in mV.
Comparator precision test conditions: supply voltage VDDThe voltage is 1.2V, the input end is connected with a common-mode voltage 600mV, and the amplitude of a differential-mode voltage is variable. The comparator works under a 1.8GHz clock, and a pulse signal is applied to the input end of the comparator so as to intuitively obtain the minimum signal amplitude value for enabling the comparator to work correctly. The simulation results are shown in FIG. 4 when the input differential mode voltage is 20 μ VIt can be seen that the comparator can achieve 20 μ V accuracy without taking input noise and input offset into account. In fig. 4, the abscissa represents time in ns and the ordinate represents voltage, where CLK, Vfn, Vfp, VON and VOP are all in V and VIP and VIN are all in mV.
Comparator delay test conditions: the input end is connected with common mode voltage 600mV, differential mode voltage 1mV, comparator clock 1.8GHz, the simulation result is shown in figure 5, and the measurable delay is 106 ps. In fig. 5, the abscissa represents time in ns and the ordinate represents voltage, where CLK, VON and VOP are all in V and VIP and VIN are all in mV.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims (5)

1. A dynamic comparator, comprising: a preamplifier and a latch, the preamplifier and the latch being cascaded;
the preamplifier is provided with transistors Mp1, Mp2, Mp3, Mp4, Mp5, Mn1, Mn2, Mn3, Mn4, Mn5 and Mn6, and the sources of the transistors Mp3, Mp4 and Mp5 are all connected with a power supply VDDThe drains of the transistors Mp3 and Mp5 are respectively connected with the N output end and the P output end of the preamplifier, and the gates of the transistors Mp3, Mp4 and Mp5 are all connected with a clock control signal;
the gates and the drains of the transistors Mn1 and Mn2 are connected with the drain of the transistor Mp4, and the sources of the transistors Mn1 and Mn2 are respectively connected with the N output end and the P output end of the preamplifier;
the sources of the transistors Mp1 and Mp2 are connected to the drain of the transistor Mp4, the drains of the transistors Mp1 and Mp2 are connected to the N output terminal and the P output terminal of the preamplifier, respectively, and the gates of the transistors Mp1 and Mp2 are connected to the input signals VIN and VIP, respectively;
the gates of the transistors Mn3 and Mn4 are respectively connected with the P output end and the N output end of the preamplifier, the drains of the transistors Mn3 and Mn4 are respectively connected with the N output end and the P output end of the preamplifier, and the sources of the transistors Mn3 and Mn4 are both grounded;
the drains of the transistors Mn5 and Mn6 are respectively connected with the N output end and the P output end of the preamplifier, the gates of the transistors Mn5 and Mn6 are both connected with a clock control signal, and the sources of the transistors Mn5 and Mn6 are both grounded.
2. The dynamic comparator according to claim 1, wherein the transistors Mp3 and Mp5 are smaller in size than the transistor Mp 4.
3. The dynamic comparator as claimed in claim 1, wherein the latch has transistors Mp6, Mp7, Mp8, Mp9, Mp10, Mp11, Mn7, Mn8, Mn9 and Mn10, and the sources of the transistors Mp6 and Mp7 are connected to the power supply VDDThe drains of the transistors are respectively connected with the drains of the transistors Mn9 and Mn10, the gates of the transistors Mp6 and Mp7 are respectively connected with the gates of the transistors Mn9 and Mn10, the sources of the transistors Mn9 and Mn10 are respectively connected with the drains of the transistors Mn7 and Mn8, the gates of the transistors Mn7 and Mn8 are respectively connected with the N input end and the P input end of the latch, and the sources of the transistors Mn7 and Mn8 are both grounded;
the drains of the transistors Mp6 and Mp7 output comparison result signals VON and VOP, respectively;
the sources of the transistors Mp8 and Mp9 are connected with a power supply VDDThe grid is respectively connected with the N input end and the P input end of the latch, and the drain is respectively connected with the drains of the transistors Mp6 and Mp 7;
the sources of the transistors Mp10 and Mp11 are connected with a power supply VDDWith gates connected to said latches respectivelyThe N input end and the P input end, and the drain electrode are respectively connected with the source electrodes of the transistors Mn9 and Mn 10.
4. The dynamic comparator according to claim 3, wherein the gate of the transistor Mp6 is connected to the drain of the transistor Mp7, and the drain of the transistor Mp6 is connected to the gate of the transistor Mp 7.
5. The dynamic comparator as claimed in claim 3, wherein the drain of the transistor Mp6 and the drain of the transistor Mp7 are connected via a capacitor CLNAnd CLPAnd (4) grounding.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116488622A (en) * 2023-04-03 2023-07-25 广东工业大学 Low-power consumption dynamic comparator

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006287305A (en) * 2005-03-31 2006-10-19 Matsushita Electric Ind Co Ltd Voltage comparator
CN101282117A (en) * 2007-04-05 2008-10-08 中国科学院微电子研究所 Dynamic comparer
US20110169681A1 (en) * 2008-12-02 2011-07-14 Panasonic Corporation Comparator and analog-to-digital converter
US20120119790A1 (en) * 2010-11-17 2012-05-17 Industrial Technology Research Institute Dynamic comparator based comparison system
US20120133395A1 (en) * 2010-11-30 2012-05-31 Ipgoal Microelectronics (Sichuan) Co., Ltd. High speed dynamic comparative latch
US8692582B1 (en) * 2012-01-06 2014-04-08 Altera Corporation Latched comparator circuitry
CN107944099A (en) * 2017-11-10 2018-04-20 东南大学 A kind of high-speed, high precision comparator circuit design
WO2018076599A1 (en) * 2016-10-31 2018-05-03 深圳市中兴微电子技术有限公司 Dynamic comparator, method for calibrating offset thereof, and computer storage medium
CN108540130A (en) * 2018-04-10 2018-09-14 中国科学院微电子研究所 A kind of dynamic comparer
US20190334514A1 (en) * 2015-09-25 2019-10-31 China Electronic Technology Corporation, 24Th Research Institute High-speed low-power-consumption dynamic comparator

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006287305A (en) * 2005-03-31 2006-10-19 Matsushita Electric Ind Co Ltd Voltage comparator
CN101282117A (en) * 2007-04-05 2008-10-08 中国科学院微电子研究所 Dynamic comparer
US20110169681A1 (en) * 2008-12-02 2011-07-14 Panasonic Corporation Comparator and analog-to-digital converter
US20120119790A1 (en) * 2010-11-17 2012-05-17 Industrial Technology Research Institute Dynamic comparator based comparison system
US20120133395A1 (en) * 2010-11-30 2012-05-31 Ipgoal Microelectronics (Sichuan) Co., Ltd. High speed dynamic comparative latch
US8692582B1 (en) * 2012-01-06 2014-04-08 Altera Corporation Latched comparator circuitry
US20190334514A1 (en) * 2015-09-25 2019-10-31 China Electronic Technology Corporation, 24Th Research Institute High-speed low-power-consumption dynamic comparator
WO2018076599A1 (en) * 2016-10-31 2018-05-03 深圳市中兴微电子技术有限公司 Dynamic comparator, method for calibrating offset thereof, and computer storage medium
CN107944099A (en) * 2017-11-10 2018-04-20 东南大学 A kind of high-speed, high precision comparator circuit design
CN108540130A (en) * 2018-04-10 2018-09-14 中国科学院微电子研究所 A kind of dynamic comparer

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
尹文倩: "高速高精度比较器的研究与设计", 《中国优秀硕士学位论文全文数据库信息科技辑》 *
朱智勇等: "一种高速高精度动态比较器", 《微电子学》 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116488622A (en) * 2023-04-03 2023-07-25 广东工业大学 Low-power consumption dynamic comparator
CN116488622B (en) * 2023-04-03 2024-02-02 广东工业大学 Low-power consumption dynamic comparator

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