CN108768363B - Tristate zero-crossing comparison circuit and power management chip - Google Patents

Tristate zero-crossing comparison circuit and power management chip Download PDF

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Publication number
CN108768363B
CN108768363B CN201810971655.1A CN201810971655A CN108768363B CN 108768363 B CN108768363 B CN 108768363B CN 201810971655 A CN201810971655 A CN 201810971655A CN 108768363 B CN108768363 B CN 108768363B
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module
zero
inverter
inv
tube
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CN108768363A (en
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董渊
王云松
黄建刚
吴传奎
程剑涛
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Shanghai Awinic Technology Co Ltd
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Shanghai Awinic Technology Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/296—Time-programme switches providing a choice of time-intervals for executing more than one switching action and automatically terminating their operation after the programme is completed
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/28—Modifications for introducing a time delay before switching
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/567—Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT

Abstract

The invention discloses a tri-state zero-crossing comparison circuit and a power management chip, comprising: the device comprises a zero-crossing comparison module, a logic output module, a starting delay module, a negative offset switching module and a light load detection module, wherein the zero-crossing comparison module is used for comparing the voltages of an output end VOUT and an SW end, generating logic level overturn and controlling the turn-off of a main power switch tube; the starting delay module is used for generating a proper starting time sequence when the DRVP signal is low and the zero-crossing comparison module is started so as to avoid false turn generated in the establishment process of voltage disturbance of the SW end; the logic output module is used for converting the voltage output by the zero-crossing comparison module into a digital logic control signal; and the negative current offset switching module is used for setting the turning point of the zero-crossing comparison module as negative current when the load current is extremely low, so as to play a role in protection. The invention can prevent the false triggering of the zero-crossing detection signal during the instant switching of the switching power supply power tube and avoid the burning of the main power switching tube.

Description

Tristate zero-crossing comparison circuit and power management chip
Technical Field
The invention relates to the technical field of analog integrated circuits, in particular to a tri-state zero-crossing comparison circuit and a power management chip, which are suitable for a switching power supply circuit.
Background
The switching power supply chip is a chip with extremely wide application in an analog integrated circuit, can reduce or boost input voltage according to the requirement of a load, generates stable output voltage and provides the stable output voltage for a load circuit of a later stage, and has the characteristics of high conversion efficiency, flexible control mode, wide input and output range and the like. Among the switching power supply chips, the BOOST type switching power supply chip has extremely important application and is characterized in that the on and off of the power tube can be controlled to make the output voltage higher than the input voltage.
As shown in fig. 1, the power transistor driving signal DRVP represents a square wave signal with a duty ratio D, when DRVP is at a high level, the main power switch transistor MP1 is turned off, the N-type power switch transistor MN1 is turned on, the SW terminal is pulled to the ground potential, and the power V of the input terminal VIN IN Generating a current to ground across inductor L1 causes inductor L1 to store energy, at which point power is supplied to output VOUT through capacitor C1; when DRVP is low level, the main power switch tube MP1 is turned on, the N-type power switch tube MN1 is turned off, and the current on the inductor L1 cannot be suddenly changed, so that the potential of the SW end is raised, V SW >V OUT The main power switch tube MP1 supplies power to the capacitor C1 and the output end VOUT, and the energy conservation law is adopted, so that when the circuit works stably, the energy conservation law is that: v (V) OUT ＝V IN and/D. In the BOOST circuit, if the load current is relatively small, the inductor current i is equal to the inductor current i during the on period of the main power switch tube MP1 L When gradually decreasing, the voltage V of the output terminal VOUT OUT And the voltage V at the SW terminal SW Gradually approach, when i L When negative, V OUT >V SW At this time, a reverse current flowing from the output terminal VOUT to the input terminal VIN is generated, and the power V of the input terminal VIN is supplied IN Causing damage. Therefore, the zero-crossing detection comparison circuit 1 needs to be added in the BOOST circuit, when the zero-crossing detection comparison circuit 1 detects that the current on the inductor L1 gradually approaches 0, the boost_ncd signal can be turned from low level to high level, and the power driving circuit 2 is controlled to make the power tube driving signal DRVP be high level, and the main power switching tube MP1 is turned off, so as to achieve the effect of protecting the power level.
As shown in fig. 2, which is a schematic diagram of a conventional zero-crossing detection comparison circuit, specifically, the zero-crossing detection comparison circuit 1 includes: zero-crossing comparison module 21 and logic output module 22, in BOOST electricIn the circuit, when DRVP is the driving signal of the main power switch tube MP1, DRVN is the reverse signal of DRVP, when DRVP is low level, the main power switch tube MP1 is turned on, the zero-crossing detection comparison circuit 1 starts to work, if V is detected SW >V OUT No reverse current is generated, and the zero-crossing detection comparison circuit 1 outputs a boost_ncd to maintain a low level; when V is SW <V OUT When the main power switch tube MP1 generates a negative reverse current from the output terminal VOUT to the SW terminal, the zero-crossing detection comparator circuit 1 outputs a high level, and controls the DRVP signal to turn off the main power switch tube MP1. However, the zero-crossing detection comparison circuit 1 has the following two drawbacks:
first, when DRVP goes low, the zero-crossing comparator will immediately enable comparison V OUT And V SW However, when the potential of the SW end is raised from a lower potential to a high potential, a certain time is required, and before the potential of the SW end is stabilized, a certain damping oscillation phenomenon exists, which causes the zero-crossing comparator to turn over erroneously, and an error power tube driving signal DRVP is generated;
second, at inductor current i L When the current is relatively large, in order to prevent offset caused by factors such as process, temperature drift and the like, a second switching tube MP2 of an offset unit is added at the SW end, so that a comparison point of a zero-crossing detection comparison circuit is positive inductance current, when the load current is relatively small in a forced PWM modulation mode, negative current can appear on an inductor during normal conduction of a main power switching tube MP1, if the existing zero-crossing detection comparator is enabled to turn over by mistake, a BOOST circuit can not work normally, therefore, the zero-crossing detection module is normally closed under extremely light load, but the scheme has systematic risk that when a strong source is suddenly added at the VOUT end or an abnormality such as overvoltage occurs, the main power switching tube MP1 can flow reverse heavy current, so that the main power switching tube MP1 is burnt out, and a power management chip is damaged.
Disclosure of Invention
In view of this, the present invention provides a tri-state zero-crossing comparison circuit and a power management chip, which are suitable for a switching power supply circuit to prevent a zero-crossing detection signal from being triggered by mistake during the instant switching of a switching power supply power tube, and can provide two protection triggering mechanisms of positive current offset and negative current offset according to mode selection.
In order to achieve the above purpose, the present invention provides the following technical solutions:
a tri-state zero-crossing comparison circuit suitable for use in a switching power supply circuit, the tri-state zero-crossing comparison circuit comprising: zero crossing comparison module, logic output module, start-up delay module, negative going maladjustment switching module and light load detection module, wherein:
the zero-crossing comparison module comprises a first end, a second end, a third end, a fourth end, a fifth end, a sixth end and a seventh end; the starting delay module comprises a first end, a second end, a third end and a fourth end; the logic output module comprises a first end, a second end, a third end and a fourth end; the negative offset switching module comprises a first end, a second end and a third end; the light load detection module comprises a first end and a second end;
the first end of the zero-crossing comparison module is used as an output end VOUT of the three-state zero-crossing comparison circuit, and the second end of the zero-crossing comparison module is used as an SW end of the three-state zero-crossing comparison circuit; the third end of the zero-crossing comparison module is connected with the second end of the starting delay module, the fourth end of the zero-crossing comparison module is connected with the third end of the starting delay module, the fifth end of the zero-crossing comparison module is connected with the first end of the negative-going offset switching module, the sixth end of the zero-crossing comparison module is connected with the second end of the negative-going offset switching module, the seventh end of the zero-crossing comparison module is connected with the first end of the logic output module, and the third end of the negative-going offset switching module is used as the FPWM input end of the negative-going offset switching module;
The second end of the logic output module is connected with the fourth end of the starting delay module, the third end of the logic output module is connected with the first end of the starting delay module, and the fourth end of the logic output module is used as the output end of the tri-state zero-crossing comparison circuit;
the light load detection module is used for detecting the inductance current, the output end of the light load detection module is connected with the third end of the negative offset switching module, when the light load detection module detects that the current is light load and needs to work in a PWM mode, the output of the light load detection module is high level, otherwise, the output of the light load detection module is low level;
the zero-crossing comparison module is used for comparing the voltages of the output end VOUT and the SW end, generating logic level overturn and controlling the turn-off of the main power switching tube;
the start delay module is used for generating a proper start time sequence when the DRVP signal is low and the zero-crossing comparison module is started so as to avoid false turn generated by voltage disturbance of the SW end in the establishment process;
the logic output module is used for converting the voltage output by the zero-crossing comparison module into a digital logic control signal;
The negative current offset switching module is used for setting the turning point of the zero-crossing comparison module as negative current when the load current is extremely low, so as to play a role in protection.
Further, the zero crossing comparison module includes: the current source (I), a second PMOS tube (MP 2), a fourth PMOS tube (MP 4), a fifth PMOS tube (MP 5), a sixth PMOS tube (MP 6), a seventh PMOS tube (MP 7), a second NMOS tube (MN 2), a third NMOS tube (MN 3), a sixth NMOS tube (MN 6) and a seventh NMOS tube (MN 7), wherein:
the first end of the current source (I), the common end of the first end of the fourth PMOS tube (MP 4) and the second end of the fifth PMOS tube (MP 5), and the second end of the seventh PMOS tube (MP 7) are used as the first end of the zero-crossing comparison module; the second end of the second PMOS tube (MP 2) is used as the second end of the zero-crossing comparison module; the common end of the first end of the seventh PMOS tube (MP 7) and the first end of the seventh NMOS tube (MN 7) is used as the seventh end of the zero-crossing comparison module and is connected with the first end of the logic output module;
the first end of the second PMOS tube (MP 2) is respectively connected with the second end of the fourth PMOS tube (MP 4) and the second end of the sixth PMOS tube (MP 6); the control end of the fifth PMOS tube (MP 5) is connected with the first end of the fifth PMOS tube (MP 5), the common end of the fifth PMOS tube is connected with the first end of the third NMOS tube (MN 3), and the fifth end serving as the zero-crossing comparison module is connected with the first end of the negative offset switching module;
The control end of the seventh PMOS tube (MP 7) is connected with the first end of the sixth PMOS tube (MP 6) and is connected with the first end of the sixth NMOS tube (MN 6); the control end of the seventh NMOS tube (MN 7), the control end of the sixth NMOS tube (MN 6), the control end of the third NMOS tube (MN 3) and the control end of the second NMOS tube (MN 2) are connected, and the sixth end serving as the zero-crossing comparison module is connected with the second end of the negative offset switching module;
the control end of the second NMOS tube (MN 2) is connected with the first end of the second NMOS tube (MN 2), and the first end of the second NMOS tube (MN 2) is connected with the second end of the current source (I); the second end of the second NMOS tube (MN 2), the second end of the third NMOS tube (MN 3), the second end of the sixth NMOS tube (MN 6) and the second end of the seventh NMOS tube (MN 7) are grounded;
the control end of the second PMOS tube (MP 2) is used as a third end of the zero-crossing comparison module and is connected with the second end of the start delay module; the control end of the fourth PMOS tube (MP 4) is used as the fourth end of the zero-crossing comparison module and is connected with the third end of the starting delay module.
Further, the negative going detuning switching module comprises: a fourth NMOS tube (MN 4) and a fifth NMOS tube (MN 5), wherein:
The first end of the fourth NMOS tube (MN 4) is used as the first end of the negative offset switching module and is connected with the fifth end of the zero-crossing comparison module, and the control end of the fourth NMOS tube (MN 4) is used as the third end input FPWM of the negative offset switching module; the second end of the fourth NMOS tube (MN 4) is connected with the first end of the fifth NMOS tube (MN 5), and the control end of the fifth NMOS tube (MN 5) is used as the second end of the negative offset switching module and is connected with the sixth end of the zero-crossing comparison module; the second end of the fifth NMOS tube (MN 5) is grounded.
Further, the logic output module includes: a first inverter (INV 1), a second inverter (INV 2), a first NAND gate (NAND 1), a first NOR gate (NOR 1), a second NOR gate (NOR 2), wherein:
an input end of the first inverter (INV 1) is used as a first end of the logic output module and is connected with a seventh end of the zero crossing comparison module; an output end of the first inverter (INV 1) is connected with a first input end of the first NAND gate (NAND 1); a second input end of the first NAND gate (NAND 1) is used as a second end of the logic output module and is connected with a fourth end of the start delay module; the output of the first NAND gate (NAND 1) is connected to a first input of the first NOR gate (NOR 1);
A second input end of the second NOR gate (NOR 2) is connected with a first end of the start delay module, a first input end of the second NOR gate (NOR 2) is connected with an output end of the first NOR gate (NOR 1), and a second input end of the first NOR gate (NOR 1) is connected with an output end of the second NOR gate (NOR 2);
the output end of the first NOR gate (NOR 1) is connected with the input end of the second inverter (INV 2), and the output end of the second inverter (INV 2) is used as the fourth end of the logic output module.
Further, the start delay module includes: a first delay unit, a second delay unit, a third inverter (INV 3), and a fourth inverter (INV 4), wherein:
the first end of the first delay unit is used as the first end of the starting delay module and is connected with the third end of the logic output module; the second end of the first delay unit is respectively connected with the first end of the second delay unit and the input end of the third inverter (INV 3), and the second end of the first delay unit is used as the second end of the starting delay module and is connected with the third end of the zero-crossing comparison module; the output end of the third inverter (INV 3) is used as a third end of the starting delay module and is connected with the fourth end of the zero-crossing comparison module;
The output end of the second delay unit is connected with the input end of the fourth inverter (INV 4), and the output end of the fourth inverter (INV 4) is used as the fourth end of the starting delay module and is connected with the second end of the logic output module.
Further, the first delay unit and/or the second delay unit include: a fifth inverter (INV 5), a sixth inverter (INV 6), a seventh inverter (INV 7), a resistor (R) A ) A first capacitor (C A ) A first AND gate (AND 1) AND a switching tube (MPA), wherein:
an input end of the sixth inverter (INV 6) is used as a first end of the first delay unit and/or the second delay unit; the output end of the sixth inverter (INV 6) is respectively connected with the input end of the seventh inverter (INV 7), the control end of the switching tube (MPA) AND the second input end of the first AND gate (AND 1);
the output end of the seventh inverter (INV 7) and the resistor (R A ) Is connected to one end of the resistor (R A ) Is connected with the other end of the fifth inverter (INV 5) and the first capacitor (C) A ) Is connected to a first end of the switching tube (MPA); the second end of the switch tube (MPA) is connected with the power supply end (VDD), the first capacitor (C A ) The other end of the first electrode is grounded;
the output of the fifth inverter (INV 5) is connected to the first input of the first AND gate (AND 1), AND the output of the first AND gate (AND 1) is used as the second end of the first delay unit AND/or the second delay unit.
Further, the first delay unit and/or the second delay unit include: eighth inverter (INV 8), ninth inverter (INV 9), tenth inverter (INV 10), eleventh inverter (INV 11), twelfth inverter (INV 12), eighth PMOS transistor (MP 8), ninth PMOS transistor (MP 9), tenth PMOS transistor (MP 10), eighth NMOS transistor (MN 8), ninth NMOS transistor (MN 9), tenth NMOS transistor (MN 10), and second capacitor (C) B ) Wherein:
an input end of the eighth inverter (INV 8) is used as a first end of the first delay unit and/or the second delay unit; the output end of the eighth inverter (INV 8) is connected with the input end of the ninth inverter (INV 9), and the output end of the ninth inverter (INV 9) is respectively connected with the control end of the eighth NMOS tube (MN 8) and the input end of the tenth inverter (INV 10);
the output end of the tenth inverter (INV 10) is connected with the control end of the tenth NMOS tube (MN 10), the first end of the eighth NMOS tube (MN 8) is connected with the first end of the eighth PMOS tube (MP 8), the first end of the eighth PMOS tube (MP 8) is connected with the control end of the eighth PMOS tube (MP 8), the second end of the ninth PMOS tube (MP 9) and the second end of the tenth PMOS tube (MP 10) are connected with the power supply end (VDD), and the control end of the tenth PMOS tube (MP 10) is connected with the output end of the eleventh inverter (INV 11);
The second end of the eighth NMOS tube (MN 8) is connected with the first end of the ninth NMOS tube (MN 9), and the control end of the ninth NMOS tube (MN 9) is connected with the output end of the eleventh inverter (INV 11); a second end of the ninth NMOS tube (MN 9) and a second end of the tenth NMOS tube (MN 9) are grounded;
the control end of the eighth PMOS tube (MP 8) is connected with the control end of the ninth PMOS tube (MP 9), and the first end of the ninth PMOS tube (MP 9) and the first end of the tenth PMOS tube (MP 10) are connected with the first end of the tenth NMOS tube (MN 10); a first end of the tenth NMOS tube (MN 10) is respectively connected with the input end of the eleventh inverter (INV 11) and the second capacitor (C) B ) Is connected to the output end of the eleventh inverter (INV 11) and the input end of the twelfth inverter (INV 12), the second capacitor (C B ) The other end of the first electrode is grounded; an output end of the twelfth inverter (INV 12) serves as a second end of the first delay unit and/or the second delay unit.
A power management chip, comprising: the three-state zero-crossing comparison circuit is described above.
Compared with the prior art, the invention discloses a tri-state zero-crossing comparison circuit and a power management chip, which are applicable to a switching power supply circuit, and the tri-state zero-crossing comparison circuit comprises: the device comprises a zero-crossing comparison module, a logic output module, a starting delay module, a negative offset switching module and a light load detection module, wherein the zero-crossing comparison module is used for comparing the voltages of an output end VOUT and an SW end, generating logic level overturn and controlling the turn-off of a main power switch tube; the starting delay module is used for generating a proper starting time sequence when the DRVP signal is low and the zero-crossing comparison module is started so as to avoid false turn generated in the establishment process of voltage disturbance of the SW end; the logic output module is used for converting the voltage output by the zero-crossing comparison module into a digital logic control signal; and the negative current offset switching module is used for setting the turning point of the zero-crossing comparison module as negative current when the load current is extremely low, so as to play a role in protection. The tri-state zero-crossing comparison circuit provided by the invention can prevent the zero-crossing detection signal from being triggered by mistake during the instant switching of the switching power supply power tube, and can simultaneously provide two protection triggering mechanisms of positive current offset and negative current offset according to mode selection, so that the main power switching tube is prevented from being burnt, and the power supply management chip is protected.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present invention, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a BOOST circuit in the prior art;
FIG. 2 is a schematic diagram of a zero-crossing comparison circuit provided in the prior art;
FIG. 3 is a schematic diagram of another tri-state zero-crossing comparison circuit according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of an implementation of a first delay unit and/or a second delay unit according to an embodiment of the present invention;
fig. 5 is a schematic waveform diagram of a power tube driving signal DRVP, an output signal drvp_dly1 of a first delay unit, and an output signal drvp_dly2 of a second delay unit according to an embodiment of the present invention;
fig. 6 is a schematic circuit diagram of another implementation of the first delay unit and/or the second delay unit according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
As shown in fig. 3, to solve the problems in the prior art, the present invention provides a tri-state zero-crossing detection comparison circuit, which is suitable for a switching power supply circuit, and mainly includes: the device comprises a zero crossing comparison module 31, a logic output module 32, a starting delay module 33, a negative going imbalance switching module 34 and a light load detection module 35.
As shown in fig. 3, the schematic block diagram of the present invention is shown in fig. 3, and the zero-crossing comparison module 31 includes a first end VOUT, a second end SW, a third end drvp_dly1, a fourth end drvp_dly1n, a fifth end, a sixth end and a seventh end; the start-up delay module 33 includes a first end DRVP, a second end drvp_dly1, a third end drvp_dly1n, and a fourth end drvp_dly2n; the logic output module 32 includes a first end, a second end drvp_dly2n, a third end DRVP, and a fourth end boost_ncd; the negative going detuning switching module 34 includes a first terminal, a second terminal and a third terminal FPWM; the light load detection module 35 includes a first end i L And a second terminal FPWM; .
The first end VOUT of the zero-cross comparison module 31 is used as the output end VOUT of the tri-state zero-cross comparison circuit, and the second end SW of the zero-cross comparison module 31 is used as the SW end of the tri-state zero-cross comparison circuit; the third terminal drvp_dly1 of the zero-crossing comparison module 31 is connected to the second terminal drvp_dly1 of the start-up delay module 33, the fourth terminal drvp_dly1N of the zero-crossing comparison module 31 is connected to the third terminal drvp_dly1N of the start-up delay module 33, the fifth terminal of the zero-crossing comparison module 31 is connected to the first terminal of the negative offset switching module 34, the sixth terminal of the zero-crossing comparison module 31 is connected to the second terminal of the negative offset switching module 34, the seventh terminal of the zero-crossing comparison module 31 is connected to the first terminal of the logic output module 32, and the third terminal FPWM of the negative offset switching module 34 is used as the FPWM input terminal of the negative offset switching module; the second terminal drvp_dly2n of the logic output module 32 is connected to the fourth terminal drvp_dly2n of the start-up delay module 33, the third terminal DRVP of the logic output module 32 is connected to the first terminal DRVP of the start-up delay module 33, and the fourth terminal boost_ncd of the logic output module 32 is used as the output terminal boost_ncd of the tri-state zero-cross comparison circuit.
The light load detection module is used for detecting the inductance current, the output end of the light load detection module is connected with the third end of the negative offset switching module, when the light load detection module detects that the current is light load and needs to work in a PWM mode, the output of the light load detection module is high level, otherwise, the output of the light load detection module is low level; the zero-crossing comparison module 31 is configured to compare the voltages of the output terminal VOUT and the SW terminal, generate a logic level flip, and control the turn-off of the main power switching tube MP 1; the start-up delay module 33 is configured to generate a proper start-up time sequence when the DRVP signal is low and the zero-crossing comparison module 31 is turned on, so as to avoid false turn-over generated by the voltage disturbance of the SW end in the building process; the logic output module 32 is configured to convert the voltage output by the zero-crossing comparison module 31 into a digital logic control signal; the negative current offset switching module 34 is configured to set the turning point of the zero-crossing comparison module 31 as a negative current when the load current is extremely low, so as to play a role in protection.
FIG. 3 is a circuit diagram of a specific implementation of the present invention, in which the second PMOS tube MP2 is used to set a proper forward offset current, and a certain margin is left for the zero-crossing comparison turning point to prevent deviation caused by drift of process, temperature, etc.; the second PMOS transistor MP2 is the same type of device as the main power switching transistor MP1 in fig. 1, so as to achieve equivalent impedance matching.
As shown in fig. 3, the zero-crossing comparison module 31 preferably includes: the current source I, the second PMOS tube MP2, the fourth PMOS tube MP4, the fifth PMOS tube MP5, the sixth PMOS tube MP6, the seventh PMOS tube MP7, the second NMOS tube MN2, the third NMOS tube MN3, the sixth NMOS tube MN6 and the seventh NMOS tube MN7, wherein:
the first end of the current source I, the common end of the first end of the fourth PMOS MP4 and the second end of the fifth PMOS MP5, and the second end of the seventh PMOS MP7 are used as the first end VOUT of the zero-cross comparison module 31; the second end of the second PMOS MP2 is used as the second end SW of the zero-crossing comparison module 31; the common end of the first end of the seventh PMOS MP7 and the first end of the seventh NMOS MN7 is connected to the first end of the logic output module 32 as the seventh end of the zero-crossing comparison module 31;
the first end of the second PMOS tube MP2 is respectively connected with the second end of the fourth PMOS tube MP4 and the second end of the sixth PMOS tube MP 6; the control end of the fifth PMOS MP5 is connected to the first end of the fifth PMOS MP5, the common end thereof is connected to the first end of the third NMOS MN3, and the fifth end serving as the zero-crossing comparison module 31 is connected to the first end of the negative offset switching module 34;
The control end of the seventh PMOS MP7 is connected to the first end of the sixth PMOS MP6, and is connected to the first end of the sixth NMOS MN 6; the control end of the seventh NMOS MN7, the control end of the sixth NMOS MN6, the control end of the third NMOS MN3, and the control end of the second NMOS MN2 are connected, and the sixth end of the zero-crossing comparison module 31 is connected to the second end of the negative offset switching module 34;
the control end of the second NMOS tube MN2 is connected with the first end of the second NMOS tube MN2, and the first end of the second NMOS tube MN2 is connected with the second end of the current source I; the second end of the second NMOS transistor MN2, the second end of the third NMOS transistor MN3, the second end of the sixth NMOS transistor MN6, and the second end of the seventh NMOS transistor MN7 are grounded;
the control end of the second PMOS MP2 is connected to the second end drvp_dly1n of the start delay module 33 as the third end drvp_dly1n of the zero-crossing comparison module 31; the control end of the fourth PMOS MP4 is connected to the third end drvp_dly2n of the start delay module 33 as the fourth end drvp_dly2n of the zero-crossing comparison module 31.
The first ends of the second PMOS transistor MP2, the fourth PMOS transistor MP4, the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, the seventh PMOS transistor MP7, the second NMOS transistor MN2, the third NMOS transistor MN3, the sixth NMOS transistor MN6, and the seventh NMOS transistor MN7 are sources, the second ends are drains, and the control ends are gates.
As shown in fig. 3, the negative going detuning switching module 34 preferably includes: a fourth NMOS transistor MN4 and a fifth NMOS transistor MN5, wherein:
the first end of the fourth NMOS MN4 is connected to the fifth end of the zero-crossing comparison module 31 as the first end of the negative offset switching module 34, and the control end of the fourth NMOS MN4 is input FPWM as the third end of the negative offset switching module 34; the second end of the fourth NMOS MN4 is connected to the first end of the fifth NMOS MN5, and the control end of the fifth NMOS MN5 is connected to the sixth end of the zero-crossing comparison module 31 as the second end of the negative offset switching module 34; the second end of the fifth NMOS transistor MN5 is grounded.
Note that, the first ends of the fourth NMOS transistor MN4 and the fifth NMOS transistor MN5 are sources, the second ends are drains, and the control ends are gates.
As shown in fig. 3, the logic output module 32 preferably includes: a first inverter INV1, a second inverter INV2, a first NAND gate NAND1, a first NOR gate NOR1, a second NOR gate NOR2, wherein:
an input end of the first inverter INV1 is connected to a seventh end of the zero-crossing comparison module 31 as a first end of the logic output module 32; an output end of the first inverter INV1 is connected to a first input end of the first NAND gate NAND 1; a second input terminal of the first NAND gate NAND1 is connected to a fourth terminal drvp_dly2N of the start-up delay module 33 as a second terminal drvp_dly2N of the logic output module 32; the output end of the first NAND gate NAND1 is connected with the first input end of the first NOR gate NOR 1; a second input terminal DRVP of the second NOR gate NOR2 is connected to the first terminal DRVP of the start-up delay module 33, a first input terminal of the second NOR gate NOR2 is connected to the output terminal of the first NOR gate NOR1, and a second input terminal of the first NOR gate NOR1 is connected to the output terminal of the second NOR gate NOR 2; an output terminal of the first NOR gate NOR1 is connected to an input terminal of the second inverter INV2, and an output terminal of the second inverter INV2 serves as a fourth terminal boost_ncd of the logic output module 32.
As shown in fig. 3, the start-up delay module 33 preferably includes: a first delay unit, a second delay unit, a third inverter INV3, and a fourth inverter INV4, wherein:
a first end of the first delay unit is connected to a third end DRVP of the logic output module 32 as a first end DRVP of the start delay module 33; the second end of the first delay unit is connected to the first end of the second delay unit and the input end of the third inverter INV3, respectively, and the second end of the first delay unit is connected to the third end drvp_dly1 of the zero-crossing comparison module 31 as the second end drvp_dly1 of the start delay module 33; an output end of the third inverter INV3 is connected to the fourth end drvp_dly1n of the zero-crossing comparison module 31 as the third end drvp_dly1n of the start-up delay module 33;
an output end of the second delay unit is connected to an input end of the fourth inverter INV4, and an output end of the fourth inverter INV4 serving as the fourth end drvp_dly2N of the start delay module 33 is connected to the second end drvp_dly2N of the logic output module 32.
As shown in fig. 3, the third NMOS transistor MN3, the fifth NMOS transistor MN5, the sixth NMOS transistor MN6, and the seventh NMOS transistor MN7 are mirror image transistors of the second NMOS transistor MN2 to match the current I of the second NMOS transistor MN2 MN2 Setting a suitable transistor aspect ratio such that I MN3 ＝I MN6 ＝I MN7 ，I MN5 ＝kI MN6 (k>1) A first delay unit and a second delay unit, the specific possible circuits of which are given by figure 4,
as shown in fig. 4, preferably, the first delay unit and/or the second delay unit include: fifth inverter INV5, sixth inverter INV6, seventh inverter INV7, resistor R A First capacitor C A A first AND gate AND1 AND a switching tube MPA, wherein:
an input end of the sixth inverter INV6 is used as a first end s_in of the first delay unit and/or the second delay unit; an output terminal of the sixth inverter INV6 is connected to an input terminal of the seventh inverter INV7, a control terminal of the switching tube MPA, AND a second input terminal of the first AND gate AND1, respectively; an output end of the seventh inverter INV7 and the resistor R A Is connected to one end of the resistor R A The other end of the first capacitor C is connected with the input end of the fifth inverter INV5 A Is connected to the first end of the switching tube MPA; a second terminal of the switch tube MPA is connected with the power supply terminal VDD, and a first capacitor C A The other end of the first electrode is grounded; an output of the fifth inverter INV5 is connected to a first input terminal of the first AND gate AND1, AND an output terminal of the first AND gate AND1 serves as the second terminal s_out of the first delay unit AND/or the second delay unit.
The first end of the switch tube MPA is a source electrode, the second end is a drain electrode, and the control end is a gate electrode.
In fig. 3, when the inductor current i L When the load is light and the operation in the PWM mode is required, the FPWM is high, otherwise, the FPWM is low. When FPWM is low, the fourth NMOS transistor MN4 is turned off, at which time I is present MP5 ＝I MP6 The method comprises the steps of carrying out a first treatment on the surface of the When DRVP is turned from high level to low level, drvp_dly1 is high level, drvp_dlyn is low level, then the fourth PMOS MP4 is turned off first, the zero-cross comparison module 31 detects the voltages of VOUT and SW and compares them, but when the voltage of SW is not stably established, drvp_dly2 is high level, i.e. the DRVP signal is delayed by the two-stage delay unit, and the output of the boost_ncd signal is shielded by the logic output module 32 to prevent the drvp_dly2 from being turned over by mistake, when the delay of the second delay unit is passed, drvp_dly2 is low level, drvp_dly2n is high level, the signal clears the shield of the boost_ncd signal, the output of the zero-cross comparison module 31 can be normally transmitted to the boost_ncd port, in this state, if V OUT >V SW -I MN6 *R ON_P2 Wherein R is ON_P2 For the equivalent on-resistance of the second PMOS MP2, the boost_ncd is high and locked in this state, the signal will make DRVP high, the power switch MP1 is turned off, and the DRVP is reset to low until the next period comes, and the zero-crossing comparison module 31 restarts the start-up timing and outputs V OUT Terminal and V SW The end performs detection and comparison.
When the inductance current is small, FPWM is high, the fourth NMOS transistor MN4 is turned on, and I is present MP5 ＝I MN5 +I MN3 ＝(1+k)I MN5 ，I MP6 ＝I MN6 Therefore there is I MP5 >I MP6 . When the DRVP signal is turned to low level, the third PMOS MP4 is turned off first, and the zero-cross comparison module 31 detects V OUT And V is equal to SW Is compared with the voltage of V at the moment SW The voltage is not stably established, and has drvp_dly1 as high level, i.e. the delay unit delays the DRVP signal, and the logic output module 32 shields the output of the boost_ncd signal to prevent the signal from being turned over by mistake, when the delay of the second delay unit is passed, drvp_dly2 is low level, drvp_dly2n is high level, at this time, the signal clears the shield of the boost_ncd signal, the output of the zero-crossing comparison module 31 can normally transmit to the boost_ncd port, in this state, if there isWhich is a kind of 2 In (W) N6 /L N6 Is the spaciousness ratio, u of the sixth NMOS transistor MN6 n Electron mobility, C, for N-type tube OX Is a gate oxide capacitance. The boost_ncd is high and locked in this state, the signal will make DRVP high, the power switch MP1 is turned off, and the DRVP is reset to low until the next period arrives, and the zero-crossing comparison module 31 restarts the start-up timing and detects and compares the VOUT side and the VSW side.
Fig. 4 is a schematic circuit diagram of one possible first delay cell and/or second delay cell of the present invention. IN fig. 4, s_in is a signal input terminal, s_out is a delay signal output terminal, when s_in is turned from high level to low level, the A0 node is turned from low level to high level, the switch tube MPA turns off the pull-up of the A1 node, the A1 node is gradually discharged through the seventh inverter INV7 and turned to low level, and the A2 node is turned to high level, so that s_out generates a delay signal; when the s_in is turned from low to high, the A0 node is turned from high to low, the A1 node is immediately pulled up to high, and the A2 node is turned to low, so that the s_out is turned to high quickly, thereby generating an effect that the s_in is turned from high to low with delay, and the s_in is turned from low to high without delay, according to the actions of the first delay unit and the second delay unit, waveforms of the power tube driving signal DRVP, the output signal drvp_dly1 of the first delay unit, and the output signal drvp_dly2 of the second delay unit are as shown IN fig. 5, t_dly1 is the delay time of the first delay unit, and t_dly2 is the delay time of the second delay unit IN fig. 5.
Fig. 6 is a schematic diagram of another possible circuit of the first delay unit and/or the second delay unit according to the present invention. As shown in fig. 6, the first delay unit and/or the second delay unit include: eighth inverter INV8, ninth inverter INV9, tenth inverter INV10, eleventh inverter INV11, twelfth inverter INV12, eighth PMOS transistor MP8, ninth PMOS transistor MP9, tenth PMOS transistor MP10, eighth NMOS transistor MN8, ninth NMOS transistor MN9, tenth NMOS transistor MN10, and second capacitor C B Wherein:
an input end of the eighth inverter INV8 is used as a first end of the first delay unit and/or the second delay unit; an output end of the eighth inverter INV8 is connected to an input end of the ninth inverter INV9, and an output end of the ninth inverter INV9 is connected to a control end of the eighth NMOS transistor MN8 and an input end of the tenth inverter INV10, respectively; the output end of the tenth inverter INV10 is connected to the control end of the tenth NMOS transistor MN10, the first end of the eighth NMOS transistor MN8 is connected to the first end of the eighth PMOS transistor MP8, the first end of the eighth PMOS transistor MP8 is connected to the control end of the eighth PMOS transistor MP8, the second end of the ninth PMOS transistor MP9, and the second end of the tenth PMOS transistor MP10 are connected to the power supply end VDD, and the control end of the tenth PMOS transistor MP10 is connected to the output end of the eleventh inverter INV 11.
The second end of the eighth NMOS transistor MN8 is connected to the first end of the ninth NMOS transistor MN9, and the control end of the ninth NMOS transistor MN9 is connected to the output end of the eleventh inverter INV 11; the second end of the ninth NMOS transistor MN9 and the second end of the tenth NMOS transistor MN9 are grounded; the control end of the eighth PMOS transistor MP8 is connected to the control end of the ninth PMOS transistor MP9, and the first end of the ninth PMOS transistor MP9 and the first end of the tenth PMOS transistor MP10 are connected to the first end of the tenth NMOS transistor MN 10; a first end of the tenth NMOS transistor MN10 is connected with the input end of the eleventh inverter INV11 and the second capacitor C B An output end of the eleventh inverter INV11 is connected to an input end of the twelfth inverter INV12, the second capacitor C B The other end of the first electrode is grounded; an output end of the twelfth inverter INV12 is used as a second end of the first delay unit and/or the second delay unit.
It should be noted that, the first ends of the eighth PMOS transistor MP8, the ninth PMOS transistor MP9, the tenth PMOS transistor MP10, the eighth NMOS transistor MN8, the ninth NMOS transistor MN9, and the tenth NMOS transistor MN10 are sources, the second ends are drains, and the control ends are gates.
The tri-state zero-crossing comparison circuit provided by the embodiment of the invention has the characteristics of strong anti-interference capability, controllable state, high reliability and the like, and can be widely applied to a power management chip.
On the basis of the tri-state zero-crossing comparison circuit suitable for the switching power supply circuit, the embodiment of the invention also discloses a power supply management chip, which comprises: the three-state zero-crossing comparison circuit.
In summary, the embodiment of the present invention provides a tri-state zero-crossing comparison circuit and a power management chip, which are suitable for a switching power supply circuit, and the tri-state zero-crossing comparison circuit includes: the device comprises a zero-crossing comparison module, a logic output module, a starting delay module, a negative offset switching module and a light load detection module, wherein the zero-crossing comparison module is used for comparing the voltages of an output end VOUT and an SW end, generating logic level overturn and controlling the turn-off of a main power switch tube; the starting delay module is used for generating a proper starting time sequence when the DRVP signal is low and the zero-crossing comparison module is started so as to avoid false turn generated in the establishment process of voltage disturbance of the SW end; the logic output module is used for converting the voltage output by the zero-crossing comparison module into a digital logic control signal; and the negative current offset switching module is used for setting the turning point of the zero-crossing comparison module as negative current when the load current is extremely low, so as to play a role in protection. The tri-state zero-crossing comparison circuit provided by the invention can prevent the zero-crossing detection signal from being triggered by mistake during the instant switching of the switching power supply power tube, and can simultaneously provide two protection triggering mechanisms of positive current offset and negative current offset according to mode selection, so that the main power switching tube is prevented from being burnt, and the power supply management chip is protected.
It should be noted that, in the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described as different from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
The circuit according to the present invention has been described above by way of example with reference to the accompanying drawings, and the description of the above embodiments is only for aiding in the understanding of the core idea of the present invention. Variations in the detailed description and the application scope will occur to those skilled in the art upon consideration of the teachings of the present invention. In view of the foregoing, this description should not be construed as limiting the invention.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (7)

1. A tri-state zero-crossing comparison circuit adapted for use in a switching power supply circuit, the tri-state zero-crossing comparison circuit comprising: zero crossing comparison module, logic output module, start-up delay module, negative going maladjustment switching module and light load detection module, wherein:
the zero-crossing comparison module comprises a first end, a second end, a third end, a fourth end, a fifth end, a sixth end and a seventh end; the starting delay module comprises a first end, a second end, a third end and a fourth end; the logic output module comprises a first end, a second end, a third end and a fourth end; the negative offset switching module comprises a first end, a second end and a third end; the light load detection module comprises a first end and a second end;
the first end of the zero-crossing comparison module is used as an output end VOUT of the three-state zero-crossing comparison circuit, and the second end of the zero-crossing comparison module is used as an SW end of the three-state zero-crossing comparison circuit; the third end of the zero-crossing comparison module is connected with the second end of the starting delay module, the fourth end of the zero-crossing comparison module is connected with the third end of the starting delay module, the fifth end of the zero-crossing comparison module is connected with the first end of the negative-going offset switching module, the sixth end of the zero-crossing comparison module is connected with the second end of the negative-going offset switching module, the seventh end of the zero-crossing comparison module is connected with the first end of the logic output module, and the third end of the negative-going offset switching module is used as the FPWM input end of the negative-going offset switching module;
The second end of the logic output module is connected with the fourth end of the starting delay module, the third end of the logic output module is connected with the first end of the starting delay module, and the fourth end of the logic output module is used as the output end of the tri-state zero-crossing comparison circuit;
the light load detection module is used for detecting the inductance current, the output end of the light load detection module is connected with the third end of the negative offset switching module, when the light load detection module detects that the inductance current is light load and needs to work in a PWM mode, the output of the light load detection module is high level, otherwise, the output of the light load detection module is low level;
the zero-crossing comparison module is used for comparing the voltages of the output end VOUT and the SW end, generating logic level overturn and controlling the turn-off of the main power switching tube;
the start delay module is used for generating a proper start time sequence when the DRVP signal is low and the zero-crossing comparison module is started so as to avoid false turn generated by voltage disturbance of the SW end in the establishment process;
the logic output module is used for converting the voltage output by the zero-crossing comparison module into a digital logic control signal;
The negative offset switching module is used for setting the turning point of the zero-crossing comparison module as negative current when the load current is extremely low, so as to play a role in protection;
the negative going detuning switching module comprises: a fourth NMOS tube (MN 4) and a fifth NMOS tube (MN 5), wherein:
the first end of the fourth NMOS tube (MN 4) is used as the first end of the negative offset switching module and is connected with the fifth end of the zero-crossing comparison module, and the control end of the fourth NMOS tube (MN 4) is used as the third end input FPWM of the negative offset switching module; the second end of the fourth NMOS tube (MN 4) is connected with the first end of the fifth NMOS tube (MN 5), and the control end of the fifth NMOS tube (MN 5) is used as the second end of the negative offset switching module and is connected with the sixth end of the zero-crossing comparison module; the second end of the fifth NMOS tube (MN 5) is grounded.
2. The circuit of claim 1, wherein the zero crossing comparison module comprises: the current source (I), a second PMOS tube (MP 2), a fourth PMOS tube (MP 4), a fifth PMOS tube (MP 5), a sixth PMOS tube (MP 6), a seventh PMOS tube (MP 7), a second NMOS tube (MN 2), a third NMOS tube (MN 3), a sixth NMOS tube (MN 6) and a seventh NMOS tube (MN 7), wherein:
The first end of the current source (I), the common end of the first end of the fourth PMOS tube (MP 4) and the second end of the fifth PMOS tube (MP 5), and the second end of the seventh PMOS tube (MP 7) are used as the first end of the zero-crossing comparison module; the second end of the second PMOS tube (MP 2) is used as the second end of the zero-crossing comparison module; the common end of the first end of the seventh PMOS tube (MP 7) and the first end of the seventh NMOS tube (MN 7) is used as the seventh end of the zero-crossing comparison module and is connected with the first end of the logic output module;
the first end of the second PMOS tube (MP 2) is respectively connected with the second end of the fourth PMOS tube (MP 4) and the second end of the sixth PMOS tube (MP 6); the control end of the fifth PMOS tube (MP 5) is connected with the first end of the fifth PMOS tube (MP 5), the common end of the fifth PMOS tube is connected with the first end of the third NMOS tube (MN 3), the fifth end serving as the zero-crossing comparison module is connected with the first end of the negative offset switching module, and the control end of the fifth PMOS tube (MP 5) is connected with the control end of the sixth PMOS tube (MP 6);
the control end of the seventh PMOS tube (MP 7) is connected with the first end of the sixth PMOS tube (MP 6) and is connected with the first end of the sixth NMOS tube (MN 6); the control end of the seventh NMOS tube (MN 7), the control end of the sixth NMOS tube (MN 6), the control end of the third NMOS tube (MN 3) and the control end of the second NMOS tube (MN 2) are connected, and the sixth end serving as the zero-crossing comparison module is connected with the second end of the negative offset switching module;
The control end of the second NMOS tube (MN 2) is connected with the first end of the second NMOS tube (MN 2), and the first end of the second NMOS tube (MN 2) is connected with the second end of the current source (I); the second end of the second NMOS tube (MN 2), the second end of the third NMOS tube (MN 3), the second end of the sixth NMOS tube (MN 6) and the second end of the seventh NMOS tube (MN 7) are grounded;
the control end of the second PMOS tube (MP 2) is used as a third end of the zero-crossing comparison module and is connected with the second end of the starting delay module; the control end of the fourth PMOS tube (MP 4) is used as the fourth end of the zero-crossing comparison module and is connected with the third end of the starting delay module.
3. The circuit of claim 1, wherein the logic output module comprises: a first inverter (INV 1), a second inverter (INV 2), a first NAND gate (NAND 1), a first NOR gate (NOR 1), a second NOR gate (NOR 2), wherein:
an input end of the first inverter (INV 1) is used as a first end of the logic output module and is connected with a seventh end of the zero crossing comparison module; an output end of the first inverter (INV 1) is connected with a first input end of the first NAND gate (NAND 1); a second input end of the first NAND gate (NAND 1) is used as a second end of the logic output module and is connected with a fourth end of the start delay module; the output of the first NAND gate (NAND 1) is connected to a first input of the first NOR gate (NOR 1);
A second input end of the second NOR gate (NOR 2) is connected with a first end of the start delay module, a first input end of the second NOR gate (NOR 2) is connected with an output end of the first NOR gate (NOR 1), and a second input end of the first NOR gate (NOR 1) is connected with an output end of the second NOR gate (NOR 2);
the output end of the first NOR gate (NOR 1) is connected with the input end of the second inverter (INV 2), and the output end of the second inverter (INV 2) is used as the fourth end of the logic output module.
4. The circuit of claim 1, wherein the start-up delay module comprises: a first delay unit, a second delay unit, a third inverter (INV 3), and a fourth inverter (INV 4), wherein:
the first end of the first delay unit is used as the first end of the starting delay module and is connected with the third end of the logic output module; the second end of the first delay unit is respectively connected with the first end of the second delay unit and the input end of the third inverter (INV 3), and the second end of the first delay unit is used as the second end of the starting delay module and is connected with the third end of the zero-crossing comparison module; the output end of the third inverter (INV 3) is used as a third end of the starting delay module and is connected with the fourth end of the zero-crossing comparison module;
The output end of the second delay unit is connected with the input end of the fourth inverter (INV 4), and the output end of the fourth inverter (INV 4) is used as the fourth end of the starting delay module and is connected with the second end of the logic output module.
5. The circuit according to claim 4, wherein the first delay unit and/or the second delay unit comprises: a fifth inverter (INV 5), a sixth inverter (INV 6), a seventh inverter (INV 7), a resistor (R) A ) A first capacitor (C A ) A first AND gate (AND 1) AND a switching tube (MPA), wherein:
an input end of the sixth inverter (INV 6) is used as a first end of the first delay unit and/or the second delay unit; the output end of the sixth inverter (INV 6) is respectively connected with the input end of the seventh inverter (INV 7), the control end of the switching tube (MPA) AND the second input end of the first AND gate (AND 1);
the output end of the seventh inverter (INV 7) and the resistor (R A ) Is connected to one end of the resistor (R A ) Is connected with the other end of the fifth inverter (INV 5) and the first capacitor (C) A ) Is connected to a first end of the switching tube (MPA); the second end of the switch tube (MPA) is connected with the power supply end (VDD), the first capacitor (C A ) The other end of the first electrode is grounded;
the output of the fifth inverter (INV 5) is connected to the first input of the first AND gate (AND 1), AND the output of the first AND gate (AND 1) is used as the second end of the first delay unit AND/or the second delay unit.
6. The circuit according to claim 4, wherein the first delay unit and/or the second delay unit comprises: eighth inverter (INV 8), ninth inverter (INV 9), tenth inverter (INV 10), eleventh inverter (INV 11), twelfth inverter (INV 12), eighth PMOS transistor (MP 8), ninth PMOS transistor (MP 9), tenth PMOS transistor (MP 10), eighth NMOS transistor (MN 8), ninth NMOS transistor (MN 9), tenth NMOS transistor (MN 10), and second capacitor (C) B ) Wherein:
an input end of the eighth inverter (INV 8) is used as a first end of the first delay unit and/or the second delay unit; the output end of the eighth inverter (INV 8) is connected with the input end of the ninth inverter (INV 9), and the output end of the ninth inverter (INV 9) is respectively connected with the control end of the eighth NMOS tube (MN 8) and the input end of the tenth inverter (INV 10);
the output end of the tenth inverter (INV 10) is connected with the control end of the tenth NMOS tube (MN 10), the first end of the eighth NMOS tube (MN 8) is connected with the first end of the eighth PMOS tube (MP 8), the first end of the eighth PMOS tube (MP 8) is connected with the control end of the eighth PMOS tube (MP 8), the second end of the ninth PMOS tube (MP 9) and the second end of the tenth PMOS tube (MP 10) are connected with the power supply end (VDD), and the control end of the tenth PMOS tube (MP 10) is connected with the output end of the eleventh inverter (INV 11);
The second end of the eighth NMOS tube (MN 8) is connected with the first end of the ninth NMOS tube (MN 9), and the control end of the ninth NMOS tube (MN 9) is connected with the output end of the eleventh inverter (INV 11); a second end of the ninth NMOS tube (MN 9) and a second end of the tenth NMOS tube (MN 10) are grounded;
the control end of the eighth PMOS tube (MP 8) is connected with the control end of the ninth PMOS tube (MP 9), and the first end of the ninth PMOS tube (MP 9) and the first end of the tenth PMOS tube (MP 10) are connected with the first end of the tenth NMOS tube (MN 10); a first end of the tenth NMOS tube (MN 10) is respectively connected with the input end of the eleventh inverter (INV 11) and the second capacitor (C) B ) Is connected to the output end of the eleventh inverter (INV 11) and the input end of the twelfth inverter (INV 12), the second capacitor (C B ) The other end of the first electrode is grounded; an output end of the twelfth inverter (INV 12) serves as a second end of the first delay unit and/or the second delay unit.
7. A power management chip, comprising: a tri-state zero-crossing comparison circuit as claimed in any one of claims 1 to 6.
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