TWI601385B - Delay circuits - Google Patents

Description

Delay circuit

The present invention relates to a delay circuit, and more particularly to a delay circuit that determines the delay time based on the rising and falling slopes of the delay control signal.

A delay circuit is a circuit that delays an input signal to an output signal after a certain period of time. Therefore, after a signal is input to the delay circuit, a delay of the specific time can be generated between the delayed signal outputted from the input signal and the input signal. Recently, as process technology has become more advanced, the operating speed of system circuits has become faster and faster, and circuits integrated in the same wafer have become more and more. Therefore, the clock synchronization between each circuit becomes quite important. Especially in high-speed systems, clock skew will be an important factor in determining system performance. Delay circuits are widely used to eliminate clock skew. In existing delay circuits, the target delay time is achieved by increasing the number of capacitors and resistive elements, or by increasing the number of inverters. However, an increase in components leads to an increase in the area of the overall circuit.

The present invention provides a delay circuit including a voltage generating circuit and a signal generating circuit. The voltage generating circuit receives the input signal and generates a first control voltage and a second control voltage. The signal generation circuit is controlled by the first control voltage and the second control voltage to generate an output signal. The first control voltage determines the loss The first delay time of the falling edge of the outgoing signal relative to the falling edge of the input signal. The second control voltage determines a second delay time of the rising edge of the output signal relative to the rising edge of the input signal.

The present invention further provides a delay circuit including a first P-type transistor, a first N-type transistor, a second P-type transistor, a second N-type transistor, and an inverter. The first P-type transistor has a gate coupled to the first low operating voltage, a source receiving the input signal, and a drain coupled to the first node. The first N-type transistor has a gate coupled to the first high operating voltage, a drain receiving the input signal, and a source coupled to the second node. The second P-type transistor has a gate coupled to the first node, a source coupled to the second high operating voltage, and a drain coupled to the third node. The second N-type transistor has a gate coupled to the second node, a drain coupled to the third node, and a source coupled to the second low operating voltage. The inverter is coupled to the third node and generates an output signal delayed by the input signal. The first P-type transistor is turned on simultaneously with the first N-type transistor.

1‧‧‧Delay circuit

10‧‧‧Voltage generation circuit

11‧‧‧Signal generation circuit

20, 22‧‧‧ PMOS transistor

21, 23‧‧‧ NMOS transistor

100‧‧‧Boost components

101‧‧‧Reducing components

110‧‧‧ PMOS transistor

111‧‧‧NMOS transistor

112‧‧‧ reverser

DT30‧‧‧Rise delay time

DT31‧‧‧Down delay time

IN‧‧‧ input signal

N10, N11, N12, N20‧‧‧ nodes

OUT‧‧‧ output signal

S12‧‧‧ Delay control signal

V11, V12‧‧‧ control voltage

VDD, VDD40, VSS, VSS40‧‧‧ Operating voltage

Figure 1 shows a delay circuit in accordance with an embodiment of the present invention.

Fig. 2 shows a delay circuit in accordance with another embodiment of the present invention.

Figure 3 shows the waveform of the main signal of the delay circuit according to the present invention.

Figure 4 shows a delay circuit in accordance with another embodiment of the present invention.

The above described objects, features and advantages of the present invention will become more apparent from the description of the appended claims.

Figure 1 is a diagram showing a delay circuit in accordance with an embodiment of the present invention. Referring to FIG. 1, the delay circuit 1 receives the input signal IN and generates an output signal OUT delayed by the input signal IN. In this embodiment, the input signal IN is a signal having at least one pulse wave. In other words, the level of the input signal IN is switched between a high level and a low level, and the level of the output signal OUT delayed by the input signal IN is also switched between a high level and a low level. The delay circuit 1 includes a voltage generating circuit 10 and a signal generating circuit 11. The signal generating circuit 11 includes a P-type metal-oxide-semiconductor (PMOS) transistor 110, an N-type metal-oxide-semiconductor (NMOS) transistor 111, and a reverse 112. The gate of the PMOS transistor 110 is coupled to the voltage generator 10 at the node N10, the source of which is coupled to the operating voltage VDD, and the drain of which is coupled to the node N12. The gate of the NMOS transistor 111 is coupled to the voltage generator 10 at the node N11, the drain of which is coupled to the node N12, and the source of which is coupled to the operating voltage VSS. In this embodiment, the operating voltage VDD is, for example, 1.8 volts (V); and the operating voltage VSS is lower than the operating voltage VDD, such as 0V or below 0V. The inverter 112 is coupled to the node N12 and generates an output signal OUT of the delay circuit 1.

The voltage generating circuit 10 receives the input signal IN of the delay circuit 1. The voltage generating circuit 10 generates control voltages V10 and V11, and supplies control voltages V10 and V11 to the nodes N10 and N11, respectively. When the level of the input signal IN is switched from the low level to the high level, the control voltage V10 generated by the voltage generating circuit 10 turns off the PMOS transistor 110. Simultaneously, when the level of the input signal IN is switched from the low level to the high level, the voltage generating circuit 10 generates the control voltage V11 to the node N11. In this embodiment, the voltage generating circuit 10 generates a high level of the control voltage V11 at this time, but cannot completely turn on the NMOS transistor 111. Therefore, the festival The level of the delay control signal S12 at the point N12 cannot be immediately lowered from the level of the operating voltage VDD to the level of the operating voltage VSS, but is gradually lowered to the level of the operating voltage VSS with a falling slope. In this embodiment, the above-described falling slope is dependent on the control voltage V11. In detail, the above-described falling slope is determined by the control voltage V11 generated by the voltage generating circuit 10 when the level of the input signal IN is switched from the low level to the high level. The inverter 112 is coupled to the node N12 to receive the delay control signal S12. According to the above, the level of the delay control signal S12 is gradually decreased. Therefore, when the level of the delay control signal S12 falls to a critical level, the inverter 112 switches the output signal OUT to a high level.

When the level of the input signal IN is switched from the high level to the low level, the control voltage V11 generated by the voltage generating circuit 10 turns off the NMOS transistor 111. Simultaneously, when the level of the input signal IN is switched from the high level to the low level, the voltage generating circuit 10 generates the control voltage V10 to the node N10. In this embodiment, the voltage generating circuit 10 generates a low level of the control voltage V10 at this time, but cannot completely turn on the PMOS transistor 110. Therefore, the level of the delay control signal S12 on the node N12 cannot be immediately raised from the level of the operating voltage VSS to the level of the operating voltage VDD, but gradually rises to the level of the operating voltage VDD with a rising slope. In this embodiment, the above-described rising slope is dependent on the control voltage V10. In detail, the above-described rising slope is determined by the control voltage V10 generated by the voltage generating circuit 10 when the level of the input signal IN is switched from the high level to the low level. The inverter 112 is coupled to the node N12 to receive the delay control signal S12. According to the above, the level of the delay control signal S12 is gradually increased. Therefore, when the level of the delay control signal S12 rises to a critical level, the inverter 112 switches the output signal OUT to a low level.

As can be seen from the above, the delay control signal S12 gradually decreases and rises as the input signal IN switches, so that the rising edge of the output signal OUT is delayed by the rising edge of the input signal IN, and the falling edge of the output signal OUT is also Delayed by the falling edge of the input signal IN. Further, the falling slope of the delay control signal S12 is dependent on the control voltage V11, and its rising slope is dependent on the control voltage V10. Therefore, the rising delay time of the rising edge of the output signal OUT with respect to the rising edge of the input signal IN is determined by the control voltage V11, and the falling delay time of the falling edge of the output signal OUT with respect to the falling edge of the input signal IN is Control voltage V10 is determined. Compared with the conventional delay circuit, the delay circuit 1 of the present invention does not need to increase the number of capacitors and resistance elements or increase the number of inverters to achieve the target delay time. According to the operation of the delay circuit 1 of the present invention, only the magnitudes of the control voltages V10 and V11 need to be changed to change the falling slope and the rising slope of the delay control signal S12, thereby changing the rising delay time and the falling delay time of the output signal OUT with respect to the input signal IN. . In an embodiment, the rise delay time is equal to the fall delay time.

Fig. 2 is a diagram showing a delay circuit according to another embodiment of the present invention. In the first and second figures, the same elements are denoted by the same reference numerals. A possible implementation of voltage generating circuit 10 and inverter 112 will be further described in the embodiment of FIG. Referring to FIG. 2, the voltage generating circuit 10 includes a boosting element 100 and a step-down element 101. The buck element 101 receives the operating voltage VDD. When the level of the input signal IN is switched from the low level to the high level, the step-down element 101 generates a control voltage V11 that is smaller than the operating voltage VDD to the node N11 for turning on the NMOS transistor 111. The boosting element 100 receives the operating voltage VSS. When the level of the input signal IN is switched from the high level to the low level, the boosting unit 100 generates a voltage greater than the operating voltage VSS. The control voltage V10 to the node N10 is used to turn on the PMOS transistor 110.

In one embodiment, boosting element 100 is implemented with PMOS transistor 20 and falling element 101 is implemented with NMOS transistor 21. The gate of the PMOS transistor 20 is coupled to the operating voltage VSS, the source thereof receives the input signal IN, and the drain thereof is coupled to the node N10. The gate of the NMOS transistor 21 is coupled to the voltage VDD, the drain thereof receives the input signal IN, and the source thereof is coupled to the node N11. According to the circuit architecture of the boosting element 100 and the step-down element 101, when the delay circuit 1 is powered, both the PMOS transistor 20 and the NMOS transistor 21 are in a normally-on state. In other words, the PMOS transistor 20 is turned on simultaneously with the NMOS transistor 21.

Referring to FIG. 2, the inverter 112 includes a PMOS transistor 22 and an NMOS transistor 23. The gate of the PMOS transistor 22 is coupled to the node N12, the source of which is coupled to the operating voltage VDD, and the drain of which is coupled to the node N20. The gate of the NMOS transistor 23 is coupled to the node N12, the drain of the node is coupled to the node N20, and the source thereof is coupled to the operating voltage VSS. The operation of the delay circuit in the embodiment of Fig. 2 will be explained below.

Referring to FIGS. 2 and 3, when the level of the input signal IN is switched from the level of the operating voltage VSS to the level of the operating voltage VDD, the control voltage V10 is equal to the operating voltage VDD, so that the PMOS transistor 110 is turned off. Simultaneously, when the level of the input signal IN is switched from the level of the operating voltage VSS to the level of the operating voltage VDD, the control voltage V11 is equal to the operating voltage VDD minus the threshold voltage V _{TH of the} NMOS transistor 21 (V11=VDD-V). _TH ). Since the voltage on the gate of the NMOS transistor 111 (ie, the control voltage V11) is smaller than the operating voltage VDD, the NMOS transistor 111 cannot be completely turned on. As a result, the level of the delay control signal S12 on the node N12 cannot be immediately lowered from the level of the operating voltage VDD to the level of the operating voltage VSS, but is gradually lowered to the level of the operating voltage VSS with a falling slope. . According to this embodiment, the above-described falling slope is determined by the control voltage V11 generated when the level of the input signal IN is switched from the level of the operating voltage VSS to the level of the operating voltage VDD. When the level of the delay control signal S12 falls to a critical level, the PMOS transistor 22 is turned on, so that the level of the output signal on the node N20 is switched from the level of the operating voltage VSS to the level of the operating voltage VDD.

Referring again to FIGS. 2 and 3, when the level of the input signal IN is switched from the level of the operating voltage VDD to the level of the operating voltage VSS, the control voltage V11 is equal to the operating voltage VSS, so that the NMOS transistor 111 is turned off. Simultaneously, when the level of the input signal IN is switched from the level of the operating voltage VDD to the level of the operating voltage VSS, the control voltage V10 is equal to the operating voltage VSS plus the threshold value V _{TH of the} PMOS transistor 20 (V10=VSS+V _TH ). Since the voltage on the gate of the PMOS transistor 110 (ie, the control voltage V10) is greater than the operating voltage VSS, the PMOS transistor 110 cannot be fully turned on. As a result, the level of the delay control signal S12 on the node N12 cannot immediately rise from the level of the operating voltage VSS to the level of the operating voltage VDD, but gradually rises to the level of the operating voltage VDD with a rising slope. . According to this embodiment, the above-described rising slope is determined by the control voltage V10 generated when the level of the input signal IN is switched from the level of the operating voltage VDD to the level of the operating voltage VSS. When the level of the delay control signal S12 rises to a critical level, the NMOS transistor 23 is turned on, so that the level OUT of the output signal on the node N20 is switched from the level of the operating voltage VDD to the level of the operating voltage VSS.

As can be seen from the above, the delay control signal S12 gradually decreases and rises as the input signal IN switches, so that the rising edge of the output signal OUT is delayed by the rising edge of the input signal IN, and the falling edge of the output signal OUT is also Delayed by the falling edge of the input signal IN. In addition, the delay of the delay control signal S12 The rate is dependent on the control voltage V11, and its rising slope is dependent on the control voltage V10. Therefore, the rising delay time DT30 (shown in FIG. 3) of the rising edge of the output signal OUT with respect to the rising edge of the input signal IN is determined by the control voltage V11, and the falling edge of the output signal OUT is decreased with respect to the input signal IN. The falling delay time DT31 of the edge (shown in Fig. 3) is determined by the control voltage V10. Compared with the conventional delay circuit, the delay circuit 1 of the present invention does not need to increase the number of capacitors and resistance elements or increase the number of inverters to achieve the target delay time. According to the operation of the delay circuit 1 of the present invention, it is only necessary to change the magnitudes of the control voltages V10 and V11 to change the falling slope and the rising slope of the delay control signal S12, thereby changing the rising delay time DT30 and the falling delay of the output signal OUT with respect to the input signal IN. Time DT31. In an embodiment, the rise delay time DT30 is equal to the fall delay time DT31.

In an embodiment, the boosting element 100 is coupled to the operating voltage different from the operating voltage VSS, and/or the bucking element 101 is coupled to the operating voltage different from the operating voltage VDD. Referring to FIG. 4, the gate of the PMOS transistor 20 in the boosting component 1005 can be coupled to the operating voltage VSS40, and the gate of the NMOS transistor 21 in the bucking component 101 can be coupled to the voltage VDD40. In this embodiment, the operating voltage VSS40 is greater than or equal to the operating voltage VSS, and the operating voltage VDD40 is less than or equal to the operating voltage VDD. The operation of the delay circuit of the embodiment of Fig. 4 is referred to the above description of the embodiment of Fig. 2, and the description thereof is omitted here.

The present invention has been disclosed in the above preferred embodiments, and is not intended to limit the scope of the present invention. Any one of ordinary skill in the art can make a few changes without departing from the spirit and scope of the invention. The scope of protection of the present invention is therefore defined by the scope of the appended claims.

1‧‧‧Delay circuit

10‧‧‧Voltage generation circuit

11‧‧‧Signal generation circuit

20, 22‧‧‧ PMOS transistor

21, 23‧‧‧ NMOS transistor

100‧‧‧Boost components

101‧‧‧Reducing components

110‧‧‧ PMOS transistor

111‧‧‧NMOS transistor

112‧‧‧ reverser

IN‧‧‧ input signal

N10, N11, N12, N20‧‧‧ nodes

OUT‧‧‧ output signal

S12‧‧‧ Delay control signal

V11, V12‧‧‧ control voltage

VDD, VSS‧‧‧ operating voltage

Claims (17)

A delay circuit includes: a voltage generating circuit that receives an input signal and generates a first control voltage and a second control voltage; and a signal generating circuit controlled by the first control voltage and the second control voltage And generating an output signal; wherein the first control voltage determines a first delay time of the falling edge of the output signal relative to a falling edge of the input signal, and the second control voltage determines a rising edge of the output signal relative to a second delay time of the rising edge of the input signal; wherein the voltage generating circuit comprises: a boosting component, receiving a first operating voltage, wherein the boosting when the input signal has a first level The component generates the first control voltage greater than the first operating voltage on a first node; and a buck component receives a second operating voltage, wherein the buck is applied when the input signal has a second level The component generates the second control voltage that is less than the second operating voltage on a second node; wherein the first level is lower than the second level, and the Operating voltage less than the second operating voltage. The delay circuit of claim 1, wherein the boosting element comprises a P-type transistor having a gate coupled to the first operating voltage, a source receiving the input signal, and a coupling The bungee of the first node; The buck device includes an N-type transistor having a gate coupled to the second operating voltage, a drain receiving the input signal, and a source coupled to the second node; wherein the first A control voltage is generated at the first node, and the second control voltage is generated at the second node; and wherein the first operating voltage is less than the second operating voltage. The delay circuit of claim 2, wherein the P-type transistor is simultaneously turned on with the N-type transistor. The delay circuit of claim 3, wherein the P-type transistor and the N-type transistor are in a normally-on state when the delay circuit is powered. The delay circuit of claim 1, wherein the signal generating circuit comprises: a P-type transistor having a gate receiving the first control voltage, a source coupled to a third operating voltage, and An anode coupled to a first node; and an N-type transistor having a gate receiving the second control voltage, a drain coupled to the first node, and a source coupled to a fourth operating voltage; Wherein the third operating voltage is greater than the fourth operating voltage; and wherein a delay control signal is generated at the first node. The delay circuit of claim 5, wherein a rising slope of the delay control signal when the level of the fourth operating voltage rises is dependent on the first control voltage; and wherein the delay control signal is The falling slope when the level of the third operating voltage drops is dependent on the second control voltage. The delay circuit of claim 5 includes an inverter that receives the delay control signal and generates the output signal based on the delay control signal. The delay circuit of claim 5, wherein the second operating voltage is less than or equal to the third operating voltage. The delay circuit of claim 5, wherein the first operating voltage is greater than or equal to the fourth operating voltage. The delay circuit of claim 1, wherein the first delay time is equal to the second delay time. A delay circuit includes: a first P-type transistor having a gate coupled to a first low operating voltage, a source receiving an input signal, and a drain coupled to a first node; a first N a type of transistor having a gate coupled to a first high operating voltage, a drain receiving the input signal, and a source coupled to a second node, wherein the first high operating voltage is greater than the first low operation a second P-type transistor having a gate coupled to the first node, a source coupled to a second high operating voltage, and a drain coupled to a third node; a second N-type a crystal having a gate coupled to the second node, a drain coupled to the third node, and a source coupled to a second low operating voltage, wherein the second high operating voltage is greater than the second low operating And an inverter coupled to the third node and generating an output signal delayed by the input signal; wherein the first P-type transistor is simultaneously turned on with the first N-type transistor. The delay circuit of claim 11, wherein the delay circuit When the power is supplied, the first P-type transistor and the first N-type transistor are in a normally-on state. The delay circuit of claim 11, wherein the voltage on the first node determines a first delay time of a falling edge of the output signal relative to a falling edge of the input signal, and the second node is The voltage determines a second delay time of the rising edge of the output signal relative to the rising edge of the input signal. The delay circuit of claim 13, wherein the first delay time is equal to the second delay time. The delay circuit of claim 11, wherein the first low operating voltage is greater than or equal to the second low operating voltage. The delay circuit of claim 11, wherein the first high operating voltage is less than or equal to the second high operating voltage. The delay circuit of claim 11, wherein the inverter comprises: a third P-type transistor having a gate coupled to the third node and a source coupled to the second high operating voltage a pole and a drain connected to a fourth node; and a third N-type transistor having a gate coupled to the third node, a drain coupled to the fourth node, and a second low coupled a source of operating voltage; wherein the output signal is generated at the fourth node.