JP2008306597A - Level shift circuit and method, and control circuit for charge pump circuit using same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve a quick response while suppressing an increase in circuit area. <P>SOLUTION: A level shift circuit 100 level-shifts an input signal Sin to generate an output signal Sout. A first level shifter 10 level-shifts the input signal Sin, and has a quicker response to a positive edge than a response to a negative edge. A second level shifter 20 level-shifts the input signal Sin, and has a quicker response to a negative edge than a response to a positive edge. An output unit 30 receives output signals S1 and S2 of the first and second level shifters 10 and 20, and generates the output signal Sout based on a high-speed transitioning edge of the output signal S1 of the first level shifter 10 and a high-speed transitioning edge of the output signal S2 of the second level shifter 20. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a level shift circuit that shifts the amplitude level of an input signal.

  In an electronic circuit, a plurality of circuit blocks having different power supply voltage levels may be provided. In order to transmit and receive digital signals that switch between a high level and a low level in a plurality of circuit blocks, a level shift circuit for absorbing a difference in power supply voltage level is provided.

  For example, in Patent Document 1, an input signal that swings with a ground voltage as a low level, a positive first voltage (3V) as a high level, and a swing that uses a ground voltage as a low level and a positive second voltage (5V) as a high level. A level shift circuit for converting to a signal is described.

JP 2003-143003 A

  Now, the first signal swinging with the ground voltage (GND) as the low level and the positive first voltage (Vdd) as the high level is the third voltage higher than the second voltage and the negative second voltage (Vss) as the low level. Consider a circuit that shifts the level to a second signal that swings with (VH) at a high level. In a level shift circuit that shifts a positive voltage to a negative voltage, an input signal given as a voltage is generally converted into a current, and the potential of an arbitrary node is changed using the converted current. FIG. 5 is a circuit diagram illustrating a configuration example of a level shifter that shifts a positive voltage to a negative voltage.

  The level shift circuit 64 of FIG. 5 includes a transistor M10 and a current source 60 of a P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) provided in series between the first voltage Vdd and the second voltage Vss, and a third voltage VH. And a second voltage Vss, a current source 62 and an N-channel MOSFET transistor M12 provided in series.

  When the input signal Sin is at a high level, the transistor M10 is off, so that the gate capacitance of the transistor M2 is discharged by the current IL1, and the transistor M2 is turned off. As a result, the output signal Sout becomes the third voltage VH, that is, the high level.

  When the input signal Sin is at a low level, the transistor M10 is turned on, the gate capacitance of the transistor M2 is charged by the difference current (Im1-IL1) between the current Im1 and the current IL1 flowing through the transistor M10, and the transistor M2 is turned on. As a result, the output signal Sout becomes the second voltage Vss, that is, the low level.

  The response speed of the level shift circuit 64 to the input signal Sin is determined by the change speed of the gate voltage of the transistor M12. That is, the response speed for the positive edge where the input signal transitions from the low level to the high level is determined by the current IL1, and the response speed for the negative edge is determined by the difference current (Im1-IL1). Therefore, there is a trade-off relationship between the response speeds of the positive edge and the negative edge.

  In order to increase both the response speed to the positive edge and the negative edge, it is necessary to increase Im1 after increasing IL1. Therefore, in the level shift circuit 64 of FIG. 5, in order to improve the response speed to the negative edge, it is necessary to set the size of the transistor M10 large. In general, the current capacity (drive capability) of a P-channel MOSFET is inferior to that of an N-channel MOSFET. In this case, there is a problem that the circuit area becomes very large.

  In addition, when the positive voltage is shifted to the negative voltage, the gate voltage of the transistor M10 is reduced only to the low level (ground voltage) of the input signal Sin. Therefore, the gate-source voltage of the transistor M10 is limited and cannot be fully turned on. Therefore, it is necessary to further increase the transistor size.

  The present invention has been made in view of these problems, and an object thereof is to provide a level shift circuit having high-speed response while suppressing an increase in circuit area.

  One embodiment of the present invention relates to a level shift circuit that generates an output signal by level-shifting an input signal. This level shift circuit is a first level shifter for level shifting an input signal, a first level shifter whose response to the positive edge of the input signal is faster than a response to the negative edge, and a second level shifter for level shifting the input signal. A second level shifter whose response to the negative edge of the input signal is faster than a response to the positive edge, an edge that receives the output signals of the first and second level shifters, and transitions at a high speed of the output signal of the first level shifter; An output unit that generates an output signal based on an edge of the output signal of the second level shifter that changes at high speed.

  According to this aspect, the positive edge of the input signal can be detected by the first level shifter, the negative edge of the input signal can be detected by the second level shifter, and the detected edges can be combined to generate an output signal. According to this circuit, the first and second level shifters need only be designed so that only one of the positive edge and the negative edge is responsive, so that the circuit area can be reduced.

One of the first and second level shifters may include a first level shift unit in which the response to one of the positive edge and the negative edge of the input signal is set higher than the response to the other. The other of the first and second level shifters may include an inverter that inverts an input signal and a second level shift unit that has a configuration equivalent to that of the first level shift unit and that shifts the output signal of the inverter. .
By using a level shift unit having an equivalent configuration, the responsiveness of the positive edge and the negative edge can be made uniform.

Each of the first and second level shift units is provided between a P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a source connected to the first fixed voltage terminal, and between the drain of the P-channel MOSFET and the second fixed voltage terminal. Current source. A signal to be level-shifted may be input to the gate of the P-channel MOSFET, and a signal corresponding to the voltage at the connection point between the P-channel MOSFET and the current source may be output.
According to this configuration, it is possible to generate a signal that quickly follows the positive edge of the signal that is the target of level shift.

  The input signal may swing with the ground voltage as a low level and the positive first voltage as a high level, and the output signal may swing with a negative second voltage as a low level and an arbitrary third voltage as a high level.

Another embodiment of the present invention relates to a control circuit for a charge pump circuit. The control circuit receives at least one switch transistor connected to the capacitor, a clock generator that generates a control signal for controlling on / off of the switch transistor, and receives the control signal as an input signal, and level-shifts the input signal to switch And the above-described level shift circuit that supplies the control terminal of the transistor.
According to this aspect, since the above-described level shift circuit is used, on / off of the switch transistor can be switched at high speed following the control signal, and the control circuit can be downsized.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other among methods, apparatuses, systems, etc. are also effective as an aspect of the present invention.

  According to the level shift circuit of the present invention, high-speed response can be realized while suppressing an increase in circuit area.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

  In this specification, “the state in which the member A and the member B are connected” means that the member A and the member B are physically directly connected, or the member A and the member B are in an electrically connected state. Including the case of being indirectly connected through other members that do not affect the above. Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as an electrical connection. The case where it is indirectly connected through another member that does not affect the state is also included.

  FIGS. 1A and 1B are circuit diagrams illustrating a configuration example of the level shift circuit 100 according to the embodiment. The level shift circuit 100 level-shifts the input signal Sin input to the input terminal 102 and outputs an output signal Sout from the output terminal 104.

  First, a level diagram of the input signal Sin and the output signal Sout will be described. In the present embodiment, the input signal Sin swings with the ground voltage GND as a low level and the positive first voltage Vdd as a high level. The output signal Sout swings with the negative second voltage Vss at a low level and an arbitrary third voltage VH higher than the second voltage Vss at a high level.

  The level shift circuit 100 includes a first level shifter 10, a second level shifter 20, and an output unit 30.

  The first level shifter 10 shifts the level of the input signal Sin in the negative direction so that the reference level (low level) of the input signal Sin matches the reference level (low level) of the output signal Sout. In the first level shifter 10, the response to the positive edge of the input signal Sin is set faster than the response to the negative edge. The output of the first level shifter 10 is referred to as a first intermediate signal S1.

  On the other hand, the second level shifter 20 is provided in parallel with the first level shifter 10, and the input signal Sin is set so that the reference level (low level) of the input signal Sin matches the reference level (low level) of the output signal Sout. Shift the level in the negative direction. The second level shifter 20 is set so that the response to the negative edge of the input signal Sin is faster than the response to the positive edge. The output of the second level shifter 20 is referred to as a second intermediate signal S2.

  That is, the first intermediate signal S1 follows the positive edge of the input signal Sin at high speed, and the second intermediate signal S2 follows the negative edge of the input signal Sin at high speed. The output unit 30 receives the first intermediate signal S1 and the second intermediate signal S2, and outputs the output signal Sout based on the edge of the first intermediate signal S1 that transitions at a high speed and the edge of the second intermediate signal S2 that transitions at a high speed. Is generated.

  According to the level shift circuit 100 of FIG. 1A, the positive edge of the input signal Sin is detected by the edge of the first intermediate signal S1 that transitions at high speed, and the input signal is detected by the edge of the second intermediate signal S2 that transitions at high speed. The negative edge of Sin can be detected, and the output signal Sout that follows both the positive edge and the negative edge of the input signal Sin at high speed can be generated by combining the two edges.

  In the level shift circuit 100 having the configuration of FIG. 1A, each of the first level shifter 10 and the second level shifter 20 only needs to have high-speed followability with respect to only one of the positive edge and the negative edge. Therefore, the circuit area of each level shifter can be reduced, and the entire area of the level shift circuit 100 can be reduced.

  Hereinafter, specific configuration examples of the level shift circuit 100 will be described, but the present invention includes various circuits based on the above principle and technical idea, and is not limited to a specific circuit.

  Each of the first level shifter 10 and the second level shifter 20 in FIG. 1A includes a first level shift unit 12 and a second level shift unit 22 having the same configuration. That is, the first level shift unit 12 and the second level shift unit 22 have high-speed follow-up with respect to either the positive edge or the negative edge of the input signal. An inverter 24 is provided in the previous stage of the second level shift unit 22.

  In the present embodiment, it is assumed that the first level shift unit 12 and the second level shift unit 22 have high-speed followability with respect to the positive edge of the input signal. That is, the first level shift unit 12 follows the positive edge of the input signal Sin at high speed.

  On the other hand, since the second level shift unit 22 follows the positive edge of the input signal * Sin (* indicates logic inversion) inverted by the inverter 24 at a high speed, it follows the negative edge of the input signal Sin at a high speed. To do. In the configuration of FIG. 1A, each of the first intermediate signal S1 and the second intermediate signal S2 is a signal obtained by level shifting the input signal Sin, and is a signal whose logic levels are inverted.

  FIG. 1B is a circuit diagram showing a configuration example of the first level shift unit 12 and the second level shift unit 22 (collectively referred to as level shift unit 14). The level shift unit 14 includes a transistor M1, a current source 26, and an inverter 25.

  The transistor M1 is a P-channel MOSFET, and its source is connected to the first fixed voltage terminal 27 to which the first voltage Vdd is applied. A signal to be level-shifted is input to the gate of the transistor M1. The current source 26 is provided between the drain of the transistor M1 and the second fixed voltage terminal 28 to which the second voltage Vss is applied. The current source 26 generates a current IL1. The level shift unit 14 outputs a signal OUT obtained by inverting the voltage at the connection point between the transistor M1 and the current source 26 by the inverter 25. By the inverter 25, the logical values of the input signal IN and the output signal OUT become the same.

  The operation of the level shift unit 14 will be described. The transistor M1 is turned on when the input signal IN is at a low level, that is, the ground voltage GND, and is turned off when the input signal IN is at a high level, that is, the first voltage Vdd. The current that flows when the transistor M1 is on is Im1.

  When the input signal IN transits from the low level to the high level and the transistor M1 is turned off, the current source 26 sucks the current IL1 from the input terminal of the inverter 25 (sink operation). As a result, the potential of the input terminal of the inverter 25 decreases, and the output signal OUT becomes high level. The level shift unit 14 increases the transition speed of the output signal OUT by setting the current IL1 as large as possible so as to have high-speed followability with respect to the positive edge of the input signal IN.

  When the input signal IN changes from the high level to the low level and the transistor M1 is turned on, the transistor M1 discharges the current Im1 to the input terminal of the inverter 25 (source operation). As a result, the potential of the input terminal of the inverter 25 rises and the output signal OUT becomes low level. The potential of the input terminal of the inverter 25 changes according to the difference current (Im1−IL1) between the current Im1 flowing through the transistor M1 and the current IL1. Since the level shift unit 14 only needs to respond to only one of the edges at high speed, the difference current (Im1−IL1) does not need to be increased so much and the size of the transistor M1 can be reduced.

  When the input signal IN transitions from the high level to the low level, the potential of the input terminal of the inverter 25 changes gently, and thus a delay τ is generated until the threshold voltage (slice level) of the inverter 25 is reached. Therefore, the negative edge of the output signal OUT appears later than the negative edge of the input signal IN by the delay τ.

  The output signal OUT of the level shift unit 14 in FIG. 1B is a signal obtained by level shifting the input signal IN. The output signal OUT of the level shift unit 14 responds at a high speed with a small negligible delay to the positive edge of the input signal IN, and responds at a relatively large delay to the negative edge of the input signal IN. .

  Returning to FIG. The positive edge of the first intermediate signal S1 transitions at high speed without delay corresponding to the positive edge of the input signal Sin. On the other hand, the positive edge of the second intermediate signal S2 transitions at high speed without delay corresponding to the negative edge of the input signal Sin.

  The output unit 30 generates one edge of the output signal Sout using the edge of the first intermediate signal S1 corresponding to the positive edge of the input signal Sin. Further, the edge detection unit 32 generates the other edge of the output signal Sout by using the edge of the second intermediate signal S2 corresponding to the negative edge of the input signal Sin.

  The output unit 30 includes an edge detection unit 32 and a frequency divider 38. The edge detector 32 detects positive edges of the first intermediate signal S1 and the second intermediate signal S2. Specifically, the edge detection unit 32 includes a NOR gate 34 and an inverter 36. The NOR gate 34 generates a negative logical sum of the first intermediate signal S1 and the second intermediate signal S2. Inverter 36 inverts the output of NOR gate 34. That is, the NOR gate 34 and the inverter 36 generate the edge detection signal Se that becomes a high level when both the first intermediate signal S1 and the second intermediate signal S2 are at a high level.

  The edge detection signal Se becomes a high level for each edge of the input signal Sin. That is, the frequency of the edge detection signal Se is twice that of the input signal Sin. The frequency divider 38 receives the edge detection signal Se and divides it by ½. As a result, the frequency divider 38 outputs an output signal Sout obtained by shifting the level of the input signal Sin.

  The operation of the level shift circuit 100 configured as described above will be described with reference to waveform diagrams. FIG. 2 is an operation waveform diagram of the level shift circuit 100 of FIG. The input signal Sin swings between the first voltage Vdd and the ground voltage GND. The first intermediate signal S1 follows the positive edge of the input signal Sin at high speed and transitions with a delay with respect to the negative edge. On the other hand, the second intermediate signal S2 follows the negative edge of the input signal Sin at high speed and transitions to the positive edge with a delay. 2 indicates the potential of the input terminal of the inverter 25 in FIG. 1B. The alternate long and short dashed lines in FIG. 2 indicate the first intermediate signal S1 and the second intermediate signal S2.

  The edge detection signal Se generated by the edge detection unit 32 becomes a high level at the timing of the positive edge of either the first intermediate signal S1 or the second intermediate signal S2. The frequency divider 38 performs a toggle operation that switches between a high level and a low level for each positive edge of the edge detection signal Se, and divides the edge detection signal Se by 1/2 to generate an output signal Sout.

  According to the level shift circuit 100 of FIG. 1A, the output signal Sout obtained by level shifting the input signal Sin in the negative direction can be generated, and both edges of the output signal Sout become steep. Further, by providing the first level shifter 10 and the second level shifter 20 with level shift units having the same configuration, there is an advantage that the responsiveness to the positive edge and the negative edge of the input signal Sin can be made uniform.

  Next, an application of the level shift circuit 100 according to the embodiment will be described. FIG. 3 is a block diagram showing a configuration of the charge pump circuit 2 including the level shift circuit 100 of FIG.

  The charge pump circuit 2 includes a flying capacitor C1, an output capacitor C2, and a control circuit 4. The charge pump circuit 2 is a voltage inversion type that converts the input voltage Vin into a negative voltage and outputs the negative voltage. The control circuit 4 includes a first switch SW1 to a fourth switch SW4, an oscillator 6, a clock generator 8, and level shift circuits 100a and 100b, and is integrated on a semiconductor substrate. The oscillator 6 generates a clock signal CK. The clock generator 8 receives the clock signal CK and generates a control signal for controlling on / off of the first switch SW1 to the fourth switch SW4.

  The charge pump circuit 2 includes an input terminal P1, capacitor terminals P2, P3, and an output terminal P4. An input voltage Vin is applied to the input terminal P1. A flying capacitor C1 is connected between the capacitor terminals P2 and P3. An output capacitor C2 is connected between the control circuit 4 and the ground terminal. The first switch SW1 is a P-channel MOSFET, and is provided between the input terminal P1 and the capacitor terminal P2. The second switch SW2 is an N-channel MOSFET and is provided between the ground terminal of the capacitor terminal P2. The third switch SW3 is a P-channel MOSFET, and is provided between the capacitor terminal P3 and the ground terminal. The fourth switch SW4 is an N-channel MOSFET, and is provided between the capacitor terminal P3 and the output terminal P4.

  The first set of switches including the first switch SW1 and the third switch SW3 and the second set of switches including the second switch SW2 and the fourth switch SW4 are repeatedly turned on and off in a complementary manner. When the first set of switches is turned on, the flying capacitor C1 is charged with the input voltage Vin. When the second set of switches is turned on, the output capacitor C2 is charged by the flying capacitor C1. By repeating the switching operation, a negative voltage (−Vin) is output as the output voltage Vout.

  The control signals Sc1 and Sc2 swing with the first voltage Vdd at a high level and the ground voltage GND at a low level. On the other hand, in order to switch on and off the third switch SW3 and the fourth switch SW4, it is necessary to make each gate voltage a negative voltage. The level shift circuits 100a and 100b receive the control signals Sc1 and Sc2, respectively shift the levels in the negative direction, and supply them to the gates of the third switch SW3 and the fourth switch SW4.

  According to the charge pump circuit 2 of FIG. 3, the third switch SW3 and the fourth switch SW4 are turned on and off while suppressing an increase in circuit area by using the level shift circuit 100 of FIG. It can be switched at high speed.

  The embodiments are exemplifications, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are within the scope of the present invention. . Examples are given below.

  In the embodiment, the output unit 30 is configured using the edge detection unit 32 and the frequency divider 38, but the present invention is not limited to this. The output unit 30 may be configured by a toggle circuit that transitions between a high level and a low level for each positive edge of the first intermediate signal S1 and the second intermediate signal S2. For example, one of the first intermediate signal S1 and the second intermediate signal S2 may be input to the set terminal of the flip-flop or latch circuit, and the other may be input to the reset terminal.

  The configuration of the level shift unit 14 is not limited to that of FIG. FIG. 4 is a circuit diagram showing a configuration of a level shift unit 14a according to a modification. The level shift unit 14a includes transistors M2 to M5 and a current source 40. The transistors M2 and M5 are P-channel MOSFETs, and the transistors M3 and M4 are N-channel MOSFETs. The current source 40, the transistor M2, and the transistor M3 are connected in series between the first fixed voltage terminal 27 to which the first voltage Vdd is applied and the second fixed voltage terminal 28 to which the second voltage Vss is applied. The current source 40 generates a current Im3. A signal IN to be level-shifted is input to the gate of the transistor M2. The transistors M5 and M4 are connected in series between the third fixed voltage terminal 29 to which the third voltage VH is applied and the second fixed voltage terminal 28. The transistor M4 forms a current mirror circuit together with the transistor M3. The transistor M5 has a bias voltage Vb applied to the base and functions as a current source that generates the current IL2.

  In the level shift unit 14a of FIG. 4, when the input signal IN at the input terminal 46 is at a high level, the transistor M2 is turned off, so that the current Im3 does not flow into the transistor M3 and the current Im4 does not flow through the transistor M4. Due to the discharge current IL2 from the transistor M5, the potential of the output terminal 48 rises and the output signal OUT becomes high level.

  When the input signal IN is at a low level, the transistor M2 is turned on, so that the current Im3 flows into the transistor M3 and the current Im4 flows through the transistor M4. The sink current corresponding to the difference between the current Im4 and the current IL2 (Im4-IL2) reduces the voltage at the output terminal 48, and the output signal OUT becomes low level.

  The level shift unit 14 in FIG. 1B responds to the positive edge of the input signal IN at high speed, but may be configured to respond to the negative edge at high speed. For example, in FIG. 1B, if the current IL1 is set small, the difference current (Im1−IL1) becomes large, so that it is possible to respond to the negative edge at high speed.

  In the embodiment, the case of level shifting from a positive voltage to a negative voltage has been described. However, the relationship between the voltage levels of the input signal Sin and the output signal Sout may be arbitrary, and a level shift unit suitable for each may be used. .

  The configuration of the charge pump circuit is not limited to that shown in FIG. 3, and a diode may be used instead of the switch transistor. Further, the charge pump circuit is not limited to the voltage inversion type, and may be a charge pump circuit having another boosting rate such as a double voltage.

  Also, the level shift circuit 100 according to the present embodiment can be suitably used for a control circuit of a switching regulator. That is, the gate voltage of the switching transistor connected to the coil or the transformer may be generated using the level shift circuit 100 according to the embodiment.

  In the embodiment, the setting of the logical values of the high level and the low level is an example, and can be freely changed by appropriately inverting it with an inverter or the like.

  Although the present invention has been described based on the embodiments, the embodiments merely illustrate the principle and application of the present invention, and the embodiments are intended to include the idea of the present invention defined in the claims. Many modifications and changes in arrangement are possible within the range not leaving.

1A and 1B are circuit diagrams illustrating a configuration example of a level shift circuit according to an embodiment. It is an operation | movement waveform diagram of the level shift circuit of Fig.1 (a). It is a block diagram which shows the structure of the charge pump circuit provided with the level shift circuit of Fig.1 (a). It is a circuit diagram which shows the structure of the level shift unit which concerns on a modification. It is a circuit diagram which shows the structural example of the level shifter which shifts a positive voltage to a negative voltage.

Explanation of symbols

2 ... charge pump circuit, 4 ... control circuit, 6 ... oscillator, 8 ... clock generator, C1 ... flying capacitor, C2 ... output capacitor, SW1 ... first switch, SW2 ... second switch, SW3 ... third switch, SW4 ... 4th switch, P1 ... input terminal, P2 ... capacitor terminal, P3 ... capacitor terminal, P4 ... output terminal, 10 ... first level shifter, 12 ... first level shift unit, 14 ... level shift unit, 20 ... second level shifter, 22 ... 2nd level shift unit, 24 ... Inverter, 25 ... Inverter, 30 ... Output part, 32 ... Edge detection part, 34 ... NOR gate, 36 ... Inverter, 38 ... Frequency divider, 100 ... Level shift circuit, 102 ... Input terminal 104 ... Output terminal M1 ... Transistor 26 ... Current source S1 ... First intermediate No., S2 ... second intermediate signal.

Claims (6)

A level shift circuit that generates an output signal by level shifting an input signal,
A first level shifter for level shifting the input signal, the first level shifter having a response to the positive edge of the input signal faster than a response to the negative edge;
A second level shifter for level-shifting the input signal, wherein the response of the input signal to the negative edge is faster than the response to the positive edge;
The first and second level shifter output signals are received, and the output signal is generated based on the high-speed transition edge of the first level shifter output signal and the high-speed transition edge of the second level shifter output signal. An output unit to
A level shift circuit comprising: One of the first and second level shifters includes a first level shift unit in which a response to one of a positive edge or a negative edge of an input signal is set higher than a response to the other,
The other of the first and second level shifters is
An inverter for inverting the input signal;
A second level shift unit having a configuration equivalent to that of the first level shift unit and level-shifting the output signal of the inverter;
The level shift circuit according to claim 1, comprising: The first and second level shift units are respectively
A P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a source connected to the first fixed voltage terminal;
A current source provided between the drain of the P-channel MOSFET and a second fixed voltage terminal;
And a signal corresponding to a voltage at a connection point between the P-channel MOSFET and the current source is output to the gate of the P-channel MOSFET. The level shift circuit described.   The input signal swings with a ground voltage as a low level and a positive first voltage as a high level, and the output signal swings with a negative second voltage as a low level and an arbitrary third voltage as a high level. 4. The level shift circuit according to claim 1, wherein A control circuit for a charge pump circuit,
At least one switch transistor connected to the capacitor;
A clock generator for generating a control signal for controlling on / off of the switch transistor;
The level shift circuit according to any one of claims 1 to 3, wherein the control signal is received as an input signal, the input signal is level-shifted and supplied to a control terminal of the switch transistor;
A control circuit comprising: A level shift method for generating an output signal by level shifting an input signal,
Level-shifting the input signal to generate a first intermediate signal that follows the positive edge of the input signal faster than the negative edge;
Level-shifting the input signal to generate a second intermediate signal that follows the negative edge of the input signal faster than the positive edge;
Generating the output signal based on a fast transition edge of the first intermediate signal and a fast transition edge of the second intermediate signal;
A level shift method comprising:

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