JP2003101405A - Level shifting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a level shifting circuit for stably outputting the signal of converted level even when the voltage level of a low voltage signal is lowered. SOLUTION: In the CMOS level shifting circuit, with which digital signals are inputted to the sources of N-channel transistors 15 and 16, a bias voltage Vref is inputted to the gates of the N-channel transistors 15 and 16 and the bias voltage Vref is set higher than the high level voltage of the digital signal and lower than a value, with which the threshold voltage of the N-channel transistors 15 and 16 is added to the high level voltage of the digital signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level shift circuit (level conversion circuit) which operates in a semiconductor integrated circuit device with a plurality of power supply voltages.

[0002]

2. Description of the Related Art A conventional level shift circuit will be described with reference to the drawings. FIG. 4 is a circuit diagram showing a conventional level shift circuit.

The level shift circuit 100 is a circuit incorporated in an LSI, which level-shifts a low-voltage signal input from an external input terminal IN into a high-voltage signal and outputs it from an external output terminal OUT. Here, the low voltage signal is a digital signal that sets the first power supply voltage Vddl to a high level and 0V to a low level. The level-shifted high voltage signal is a digital signal that sets the second power supply voltage Vddh to the high level and 0V to the low level. First power supply voltage Vddl and second power supply voltage Vddh
Uses an appropriate power supply voltage among the LSI internal power supply voltages.

In FIG. 4, reference numeral 21 is a low-voltage operating first inverter, and 22 is a low-voltage operating second inverter.
23 is a first P-channel transistor operating at high voltage,
Reference numeral 24 is a second P-channel transistor that operates at high voltage, and the substrate electrode of each is connected to the source.
Further, 25 is a first N-channel transistor operating at high voltage, and 26 is a second N-channel transistor operating at high voltage, and the substrate electrode thereof is connected to GND.

The operation of the conventional level shift circuit 100 will be described with reference to FIG. First, the external input terminal IN
A case where the low voltage signal given by the L level (0V) is described. The low voltage signal is inverted via the first inverter 21, and the connection point n5 is pulled up to the H level (Vddl), so that the first N-channel transistor 2
The H level (Vddl) is applied to the source of 5. At this time, the voltage applied to the gate of the first N-channel transistor 25 is at the H level (Vddl),
The first N-channel transistor 25 is turned off.

On the other hand, the signal branched at the connection point n5 is inverted via the second inverter 22, and the connection point n6 is pulled down to the L level (0 V), so that the signal is supplied to the source of the second N-channel transistor 26. Is given an L level (0V). At this time, the second N-channel transistor 26
Since the voltage of H level (Vddl) is applied to the gate of the second N-channel transistor 26, the second N-channel transistor 26 becomes conductive. Therefore, the connection point n8 is pulled down to the L level (0V).

In addition, the first P-channel transistor 23
The H level (Vddh) of the high voltage signal is applied to the source of the first P-channel transistor, and the gate (connection point n8) of the first P-channel transistor 23 is the L level (0V).
The P-channel transistor 23 is turned on. Therefore, the connection point n7 is pulled up to the H level (Vddh).

In addition, the second P-channel transistor 24
The H level (Vddh) of the high voltage signal is applied to the source of the, and the gate (connection point n7) of the second P-channel transistor 24 is at the H level (Vddh).
The second P-channel transistor 24 becomes non-conductive. As a result, the external output terminal OUT (connection point n8) is L
It stabilizes at the level (0V).

Next, the case where the low voltage signal applied from the external input terminal IN is at the H level (Vddl) will be described. The low voltage signal is inverted via the first inverter 21, and the connection point n5 is pulled down to L level (0V), so that the source of the first N-channel transistor 25 is given L level (0V). At this time, the gate of the first N-channel transistor 25 has an H level (Vdd
Since the voltage of 1) is applied, the first N-channel transistor 25 becomes conductive. Therefore, the connection point n
7 is pulled down to L level (0V).

In addition, the second P-channel transistor 24
Since the H level (Vddh) of the high voltage signal is applied to the source of the second and the gate (connection point n7) of the second P-channel transistor 24 is the L level (0V), the second
The P-channel transistor 24 is turned on. Therefore, the connection point n8 is pulled up to the H level (Vddh).

On the other hand, the signal branched at the connection point n5 is inverted via the second inverter 22, and the connection point n6 is pulled up to the H level (Vddl). H level (Vdd
l) is given. At this time, the voltage applied to the gate of the second N-channel transistor 26 is at the H level (Vddl), so that the second N-channel transistor 26 becomes non-conductive.

Further, the first P-channel transistor 23
The voltage of H level (Vddh) is applied to the source of, and the gate (connection point n8) of the first P-channel transistor 23 is at H level (Vddh).
The first P-channel transistor 23 becomes non-conductive. As a result, the external output terminal OUT (connection point n8) becomes H
It stabilizes at the level (Vddh).

Thus, the conventional level shift circuit 10
0 can level-convert the input low voltage signal and output it as a high voltage signal.

[0014]

In the level shift circuit 100 described above, when the withstand voltage of the transistor is reduced due to the demand for lower power consumption of electronic equipment and the miniaturization of processes, the LSI internal power supply voltage is reduced. Need to be lowered. However, when the first power supply voltage Vddl becomes lower than 1.5V, the propagation delay time from the input to the output of the level shift circuit 100 increases rapidly. This is the power supply voltage V
This is because when ddl decreases, the time for charging the gates of the first and second N-channel transistors 25 and 26 increases.

Further, when the power supply voltage Vddl drops to about 1.0 V, the first and second N-channel transistors 25 and 26 cannot operate. This is because the power supply voltage Vddl input to the gates of the first or second N-channel transistors 25 and 26 approaches the threshold voltages of the first and second N-channel transistors 25 and 26. . As described above, the conventional level shift circuit 100 has a problem that it does not function when the power supply voltage Vddl is too low.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a level shift circuit that outputs a signal whose level is stably converted even when the voltage level of a low voltage signal is lowered. To do.

[0017]

The level shift circuit of the present invention is a CMOS level shift circuit in which a digital signal is input to the source of an N-channel transistor, and a bias voltage is input to the gate of the N-channel transistor, The bias voltage is higher than the high level voltage of the digital signal and lower than a value obtained by adding the threshold voltage of the N-channel transistor to the high level voltage of the digital signal. As a result, the N-channel transistor can be operated even when the voltage of the digital signal is low, so that a level shift circuit capable of converting the level of the input signal and outputting it can be realized.

Preferably, the bias voltage is one of power supply voltages. As a result, the N-channel transistor can be operated using the existing power supply voltage without applying a new voltage.

Another level shift circuit of the present invention is
A CMOS level shift circuit comprising a first N-channel transistor, a second N-channel transistor, a first P-channel transistor and a second P-channel transistor, wherein the drain of the first N-channel transistor is The drain of the second P-channel transistor is connected to the drain of the first P-channel transistor and the gate of the second P-channel transistor, and the drain of the second N-channel transistor is connected to the drain of the second P-channel transistor and the first P-channel transistor. Connected to the gate and external output terminal. The source of the first N-channel transistor receives the inverted signal of the digital signal input from the external input terminal and having the first power supply voltage at the high level and the ground voltage at the low level, and the second N-channel. The digital signal is input to the source of the transistor. Furthermore, the gates of the first N-channel transistor and the second N-channel transistor are higher than a first power supply voltage, and the first N-channel transistor and the second N-channel are at the first power supply voltage. A bias voltage having a value lower than the value obtained by adding the threshold voltage of the transistor is input. On the other hand, the second power supply voltage is input to the respective sources of the first P-channel transistor and the second P-channel transistor.
This allows the first and second N-channel transistors to operate even when the first power supply voltage is low. Therefore, it is possible to realize a level shift circuit capable of converting the level of the input signal and outputting the level even when the first power supply voltage is low.

Preferably, a third power supply voltage higher than either the first power supply voltage or the second power supply voltage is used as the bias voltage. Therefore, even when the difference between the first power supply voltage and the second power supply voltage is small, the N-channel transistor can be operated using the existing power supply voltage without applying a new voltage.

Preferably, the bias voltage is
It is an output of the intermediate voltage generating circuit, and the intermediate voltage generating circuit is a source follower circuit having a third P-channel transistor whose gate is connected to the first power supply voltage. Thereby, the desired bias voltage can be generated without increasing the power supply voltage used.

Preferably, the voltage applied to the substrate electrode of the first N-channel transistor and the substrate electrode of the second N-channel transistor is equal to or lower than the ground voltage, and one or both of the voltages is It shall be lower than the ground voltage. As a result, the threshold voltage becomes low when each of the first N-channel transistor and the second N-channel transistor is conductive, so that the operating speed can be improved, and when not conductive, the threshold voltage is high. As a result, the leak current is reduced and low power consumption is realized.

Further, preferably, the voltage applied to the substrate electrode of the first N-channel transistor is the first N-channel transistor.
When the channel transistor is conducting, it is lower than the ground voltage, and when the first N-channel transistor is non-conducting, the voltage is the ground voltage, and the voltage applied to the substrate electrode of the second N-channel transistor is the same when the second N-channel transistor is conducting. Sometimes it is lower than the ground voltage and the second N
The structure is such that the ground voltage is applied when the channel transistor is not conducting. As a result, the threshold voltage when each of the first N-channel transistor and the second N-channel transistor is conductive is further lowered, and thus the operating speed is improved, and when the non-conductive state, the threshold voltage is increased. Is further increased, the leak current is reduced and the power consumption is reduced.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A level shift circuit according to a first embodiment of the present invention will be described with reference to the drawings. 1 is a circuit diagram showing a level shift circuit according to a first embodiment of the present invention.

The level shift circuit 10 is incorporated in an LSI, level shifts a low voltage signal input from the external input terminal IN to a high voltage signal, and outputs the external output terminal O.
It is a circuit formed by CMOS, which is output from the UT.
Here, the low voltage signal is a digital signal that sets the first power supply voltage Vddl to a high level and 0V to a low level. The level-shifted high voltage signal is a digital signal that sets the second power supply voltage Vddh to the high level and 0V to the low level. As the first power supply voltage Vddl and the second power supply voltage Vddh, appropriate ones are used among the LSI internal power supply voltages.

Reference numeral 11 is a low voltage first inverter, and 12
Is a second inverter operating at a low voltage. Reference numeral 13 is a high-voltage operating first P-channel transistor, and 14 is a high-voltage operating second P-channel transistor, each of which has a substrate electrode connected to a source. Further, 15 is a first N-channel transistor operating at high voltage, and 16 is a second N-channel transistor operating at high voltage, and the substrate electrodes thereof are respectively connected to GND.

The external input terminal IN is connected to the first inverter 11
Is connected to the input side of. The output side of the first inverter 11 is branched at a connection point n1 and one is connected to the source of the first N-channel transistor 15. The other side is connected to the input side of the second inverter 12. The output side of the second inverter 12 is connected to the source of the second N-channel transistor 16 via a connection point n2. First and second N-channel transistors 15,
An intermediate voltage Vref is applied to the gate of 16. The intermediate voltage Vref is Vddl <Vref <Vdd
It is a voltage value that satisfies the relation of l + Vtn. Where Vt
n is the threshold voltage of the first and second N-channel transistors.

The drain of the first N-channel transistor 15 is connected to the drain of the first P-channel transistor 13 and the gate of the second P-channel transistor 14 via a connection point n3. The drain of the second N-channel transistor 16 is connected to the drain of the second P-channel transistor 14, the gate of the first P-channel transistor 13 and the external output terminal OUT via a connection point n4. The sources of the first and second P-channel transistors 13 and 14 are connected to the second power supply voltage Vd.
dh is applied.

The operation of the level shift circuit 10 of the first embodiment configured as described above will be described. First,
A case where the low voltage signal applied from the external input terminal IN is at L level (0V) will be described. Low voltage signal is the first
Since it is inverted through the inverter 11 and the connection point n1 is pulled up to the H level (Vddl), the source of the first N-channel transistor 15 has the H level (Vddl).
Is given. At this time, since the intermediate voltage Vref is applied to the gate of the first N-channel transistor 15, the gate of the first N-channel transistor 15
The source-to-source voltage becomes Vref-Vddl, and Vref
The relationship of −Vddl <Vtn is established. Gate·
Since the source-to-source voltage is lower than the threshold voltage Vtn, the first N-channel transistor 15 becomes non-conductive.

On the other hand, the signal branched at the connection point n1 is inverted through the second inverter 12, and the connection point n2 is pulled down to the L level (0V), so that the signal is supplied to the source of the second N-channel transistor 16. Is given an L level (0V). At this time, the second N-channel transistor 16
Since the intermediate voltage Vref is applied to the gate of the second N-channel transistor 16, the gate-source voltage of the second N-channel transistor 16 becomes Vref-0V, and Vref-0V>
The relationship of Vtn is established. Since the gate-source voltage is higher than the threshold voltage Vtn, the second N-channel transistor 16 becomes conductive. for that reason,
The connection point n4 is pulled down to the L level (0V).

In addition, the first P-channel transistor 13
Since the H level (Vddh) of the high voltage signal is applied to the source of the first and the gate (connection point n4) of the first P-channel transistor 13 is the L level (0V), the first
The P-channel transistor 13 is turned on. Therefore, the connection point n3 is pulled up to the H level (Vddh).

In addition, the second P-channel transistor 14
The H level (Vddh) is applied to the source of, and the gate (connection point n3) of the second P-channel transistor 14 is at the H level (Vddh), so the second P-channel transistor 14 is in the non-conduction state. Becomes As a result, the external output terminal OUT (connection point n4) is at L level (0
It stabilizes at V).

Next, the case where the low voltage signal applied from the external input terminal IN is at the H level (Vddl) will be described. The low voltage signal is inverted via the first inverter 11 and the connection point n1 is pulled down to L level (0V), so that the source of the first N-channel transistor 15 is supplied with L level (0V). At this time, the intermediate voltage Vre is applied to the gate of the first N-channel transistor 15.
Since f is applied, the gate-source voltage of the first N-channel transistor 15 becomes Vref-0V, and the relationship of Vref-0V> Vtn is established.
Since the gate-source voltage is higher than the threshold voltage Vtn, the first N-channel transistor 15 becomes conductive. Therefore, the connection point n3 is pulled down to the L level (0V).

In addition, the second P-channel transistor 14
The H level (Vddh) of the high voltage signal is applied to the source of the second P-channel transistor, and the gate (connection point n3) of the second P-channel transistor 14 is the L level (0V).
The P-channel transistor 14 is turned on. Therefore, the connection point n4 is pulled up to the H level (Vddh).

On the other hand, the signal branched at the connection point n1 is inverted via the second inverter 12 and the connection point n2 is pulled up to the H level (Vddl), so that the source of the second N-channel transistor 16 is connected. H level (Vdd
l) is given. At this time, since the intermediate voltage Vref is applied to the gate of the second N-channel transistor 16, the gate-source voltage of the second N-channel transistor 16 becomes Vref-Vddl, which is Vr.
The relationship of ef-Vddl <Vtn is established. Since the gate-source voltage is lower than the threshold voltage Vtn, the second N-channel transistor 16 becomes non-conductive.

In addition, the first P-channel transistor 13
Since a voltage of H level (Vddh) is applied to the source of, and the gate (connection point n4) of the first P-channel transistor 13 is at H level (Vddh),
The first P-channel transistor 13 is turned off. As a result, the external output terminal OUT (connection point n4) is at H level.
It stabilizes at the level (Vddh).

As described above, according to the level shift circuit 10 of the first embodiment, Vddl <Vref <V is applied to the gates of the first and second N-channel transistors 15 and 16.
Intermediate voltage Vref satisfying the relationship of ddl + Vtn
Is applied, the first and second N-channel transistors 15 and 16 can be operated even when the first power supply voltage Vddl is low. Therefore, a level shift circuit capable of stably converting the level of the input signal can be realized.

The intermediate voltage Vref does not have to be supplied from the outside, and the third power supply voltage, which is one of the LSI internal power supply voltages, may be used. This third power supply voltage is the first
The first power supply voltage Vddl is higher than the power supply voltage Vddl.
It may be smaller than the value obtained by adding the threshold voltage Vtn to. Thereby, there is an effect that it is not necessary to newly apply a voltage from the outside. Also, the first power supply voltage V
When the difference between ddl and the second power supply voltage Vddh is small, the third power supply voltage is equal to the first power supply voltage Vddl and the second power supply voltage Vddl.
The value may be larger than either of the power supply voltage Vddh.

(Second Embodiment) A level shift circuit according to a second embodiment of the present invention will be described with reference to the drawings.
FIG. 2 is a circuit diagram showing a level shift circuit according to the second embodiment of the present invention. It should be noted that the same components as those in FIG. 1 are designated by the same reference numerals.

The level shift circuit 20 according to the second embodiment is
An intermediate voltage generating circuit 18 is added to the level shift circuit 10 of the first embodiment. Others are the same as the level shift circuit 10 of FIG.

The intermediate voltage generating circuit 18 is a source follower circuit and is composed of a third P-channel transistor 17 and a resistor R.

The source of the third P-channel transistor 17 is grounded. Third P-channel transistor 1
The first power supply voltage Vddl is applied to the gate of 7. Further, the second power supply voltage Vddh is applied to the drain of the third P-channel transistor 17 via the resistor R. Furthermore, the substrate electrode and the drain are connected. The drain of the third P-channel transistor 17 is connected to the gates of the first and second N-channel transistors 15 and 16 at the connection point nr.

The intermediate voltage generating circuit 18 outputs the intermediate voltage Vre.
This is a circuit for generating f from two power supply voltages Vddl and Vddh. The intermediate voltage Vref output from the intermediate voltage generation circuit 18 is input to the gates of the second N-channel transistors 15 and 16 via the connection point nr. Third
Threshold voltage of the P-channel transistor 17 of Vtp
Then, the output of the intermediate voltage generating circuit 18 is Vddl + |
It becomes Vtp |. If the transistor size of the third P-channel transistor 17 is set so that | Vtp | <Vtn, then Vddl <Vddl + | Vtp | <
The relationship of Vddl + Vtn is satisfied. With such a configuration, the intermediate voltage generating circuit 18 can be used in the first embodiment.
It is possible to output the intermediate voltage Vref described above.

As described above, according to the level shift circuit of the second embodiment, the intermediate voltage Vre is calculated from the two power supply voltages.
Since the intermediate voltage generating circuit 18 that can generate f is provided, the first and second N-channels can be generated even if the first power supply voltage Vddl is lowered without newly applying a voltage from the outside. The transistors 15 and 16 can be operated. Therefore, a level shift circuit capable of stably converting the level of the input signal can be realized.

(Third Embodiment) A level shift circuit according to a third embodiment of the present invention will be described with reference to the drawings.
FIG. 3 is a circuit diagram showing a level shift circuit according to the third embodiment of the present invention. The same reference numerals are given to the same parts as those in FIGS. 1 and 2.

The level shift circuit 30 according to the third embodiment is
The level shift circuit 10 according to the first embodiment is different from the intermediate voltage generation circuit 18 according to the second embodiment in that an intermediate voltage generation circuit 18a for supplying an intermediate voltage is added. The terminals ns1 and ns2 of the substrate electrodes of the second N-channel transistors 15 and 16 are G
It is connected to a potential lower than ND or GND. In other words, the substrate electrodes of the first and second N-channel transistors 15 and 16 of the level shift circuit 30 have G
Voltage below ND is applied.

By applying a voltage of GND or lower to the substrate electrodes of the first and second N-channel transistors 15 and 16, these first and second N-channel transistors 15 and 16 have a back bias effect (substrate Bias effect) occurs. That is, when the potential difference between the source and the substrate electrode of the N-channel transistor is large, the threshold voltage Vtn becomes large, and when the potential difference between the source and the substrate electrode is small, the threshold voltage Vtn becomes small.

When the substrate electrodes of the first and second N-channel transistors 15 and 16 are fixed to GND, and when the L level (0 V) is applied to the sources of the first and second N-channel transistors 15 and 16, The threshold voltage Vtn becomes smaller. At this time, since the first and second N-channel transistors 15 and 16 are in the conductive state, the operating speed can be improved.

Conversely, when the H level (Vddl) is applied to the sources of the first and second N-channel transistors 15 and 16, the threshold voltage Vtn increases.
At this time, since the first and second N-channel transistors 15 and 16 are in the non-conducting state, the leak current is reduced and the power consumption is reduced.

Further, by fixing the substrate electrodes of the first and second N-channel transistors 15 and 16 without fixing them and changing them to GND or a value smaller than GND, the performance is further improved. That is, when the first and second N-channel transistors 15 and 16 are conductive,
When the voltage applied to each substrate electrode is GND and the first and second N-channel transistors 15 and 16 are non-conducting, if the voltage applied to each substrate electrode is smaller than GND, the conducting state is achieved. The remarkable improvement in the operating speed of the device and the reduction of the power consumption in the non-conduction state. Therefore, in such a case, the level shift circuit has high characteristics.

The intermediate voltage generating circuit 18a is the same as the second embodiment.
Instead of the resistor R of the intermediate voltage generating circuit 18, the fourth P-channel transistor 19 is connected to the third P-channel transistor 17. The first power supply voltage Vddl is applied to the gate of the third P-channel transistor 17, the source is grounded, and the substrate electrode and the drain are connected. Also, the fourth P-channel transistor 1
The substrate electrode of 9 and the source are connected, and the second power supply voltage Vddh is applied. The gate of the fourth P-channel transistor 19 is connected to the drain, and
The drain of the third P-channel transistor 17 is connected to the substrate electrode. Third P-channel transistor 1
The drain of 7 is connected to the gates of the first and second N-channel transistors 15 and 16 at a connection point nr.

The intermediate voltage generating circuit 18a uses the fourth P-channel transistor 19 instead of the resistor R of the second embodiment, so that the intermediate voltage generating circuit 18a has the same intermediate voltage as the intermediate voltage generating circuit 18 described in the second embodiment. Connect Vref to connection point nr
Can be generated.

Therefore, since the intermediate voltage Vref can be generated from the two power supply voltages, even if the first power supply voltage Vddl is lowered, the first and second power supply voltages are reduced.
The N-channel transistors 15 and 16 can be operated.

[0054]

As described above, according to the level shift circuit of the present invention, in the CMOS level shift circuit in which the digital signal is input to the source of the N-channel transistor, the bias voltage is input to the gate of the N-channel transistor. The bias voltage is set to be higher than the high level voltage of the digital signal and lower than the value obtained by adding the threshold voltage of the N-channel transistor to the high level voltage of the digital signal. The channel transistor can be operated even when the voltage of the digital signal drops. As a result, a level shift circuit capable of converting the level of the input signal in a stable manner can be realized.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a level shift circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a level shift circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a level shift circuit according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram showing a conventional level shift circuit.

[Explanation of symbols]

10, 20, 30, 100 Level shift circuit 11, 21 First inverter circuit 12, 22 Second inverter circuit 13, 23 First P-channel transistor 14, 24 Second P-channel transistor 15, 25 First N-channel transistor 16, 26 Second N-channel transistor 17 Third P-channel transistor 19 Fourth P-channel transistor 18, 18a Intermediate voltage generation circuit n1, n2, n3, n4, n5, n6, n7, n8, n
r Connection point ns1, ns2 Terminal IN External input terminal OUT External output terminal

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Heiji Ikoma             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. (72) Inventor Naoki Nojiri             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. F term (reference) 5J056 AA00 AA32 BB18 CC00 CC21                       DD13 DD29 EE03 EE04 EE07                       FF06 FF08

Claims (7)

[Claims] 1. A CMOS level shift circuit in which a digital signal is input to a source of an N-channel transistor, a bias voltage is input to a gate of the N-channel transistor, and the bias voltage is a high level of the digital signal. CM which is higher than the voltage and lower than the value obtained by adding the threshold voltage of the N-channel transistor to the high level voltage of the digital signal.
OS level shift circuit. 2. The CMOS according to claim 1, wherein the bias voltage is one of power supply voltages.
Level shift circuit. 3. A CMOS comprising a first N-channel transistor, a second N-channel transistor, a first P-channel transistor and a second P-channel transistor.
In the level shift circuit, the drain of the first N-channel transistor is the first
Connected to the drain of the P-channel transistor and the gate of the second P-channel transistor, and the drain of the second N-channel transistor is connected to the second
Connected to the drain of the P-channel transistor, the gate of the first P-channel transistor and the external output terminal, and the source of the first N-channel transistor receives the high level of the first power supply voltage input from the external input terminal. An inverted signal of a digital signal whose ground voltage is at a low level is input, the digital signal is input to a source of the second N-channel transistor, the first N-channel transistor and the second N-channel transistor are input.
The gate of each of the channel transistors has a value higher than the first power supply voltage and lower than a value obtained by adding the threshold voltages of the first N-channel transistor and the second N-channel transistor to the first power supply voltage. A CMOS level shift circuit, wherein a bias voltage is input, and a second power supply voltage is input to respective sources of the first P-channel transistor and the second P-channel transistor. 4. The CMO according to claim 3, wherein a third power supply voltage higher than either the first power supply voltage or the second power supply voltage is used as the bias voltage.
S level shift circuit. 5. The bias voltage is an output of an intermediate voltage generation circuit, and the intermediate voltage generation circuit is a source follower circuit having a third P-channel transistor whose gate is connected to the first power supply voltage. The CMOS level shift circuit according to claim 3, wherein the CMOS level shift circuit is provided. 6. The voltage applied to the substrate electrode of the first N-channel transistor and the substrate electrode of the second N-channel transistor is equal to or lower than the ground voltage, and one or both of the voltages is higher than the ground voltage. 4. The CMOS level shift circuit according to claim 3, wherein 7. The voltage applied to the substrate electrode of the first N-channel transistor is lower than the ground voltage when the first N-channel transistor is on, and is the ground voltage when the first N-channel transistor is off. The voltage applied to the substrate electrode of the second N-channel transistor is lower than the ground voltage when the second N-channel transistor is on, and is the ground voltage when the second N-channel transistor is off. The CMOS level shift circuit according to claim 6.