CN105827232B - A kind of restoring circuit improving SSLC level shifting circuit Negative Bias Temperature Instability - Google Patents
A kind of restoring circuit improving SSLC level shifting circuit Negative Bias Temperature Instability Download PDFInfo
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- CN105827232B CN105827232B CN201610154912.3A CN201610154912A CN105827232B CN 105827232 B CN105827232 B CN 105827232B CN 201610154912 A CN201610154912 A CN 201610154912A CN 105827232 B CN105827232 B CN 105827232B
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- DYCJFJRCWPVDHY-LSCFUAHRSA-N NBMPR Chemical compound O[C@@H]1[C@H](O)[C@@H](CO)O[C@H]1N1C2=NC=NC(SCC=3C=CC(=CC=3)[N+]([O-])=O)=C2N=C1 DYCJFJRCWPVDHY-LSCFUAHRSA-N 0.000 claims abstract description 18
- 230000000694 effects Effects 0.000 claims abstract description 17
- 238000011084 recovery Methods 0.000 claims abstract description 12
- 238000006243 chemical reaction Methods 0.000 claims description 3
- 230000008859 change Effects 0.000 description 4
- 230000005611 electricity Effects 0.000 description 4
- 230000006872 improvement Effects 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910007266 Si2O Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000003487 electrochemical reaction Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000010327 methods by industry Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
- H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018557—Coupling arrangements; Impedance matching circuits
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- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
Abstract
The present invention is a kind of restoring circuit for improving SSLC level shifting circuit Negative Bias Temperature Instability, the circuit includes SSLC level shifting circuit and NBTI effect recovery unit, the SSLC level shifting circuit includes PMOS transistor MP1, MP2, MP3 and NMOS transistor MN1, MN2, MN3, the NBTI effect recovery unit includes PMOS transistor P1 and P2, NMOS transistor N1, phase inverter iv and restores enabled control terminal EN, and the P1 connects high level end V with the source electrode of P2DDHThe grid of the P1 is connected to the output end of phase inverter iv, the grid connection of the P2 restores enabled control terminal EN, the drain electrode of P1 is connected to the source level of MP1, the drain electrode of P2 is connected to the grid of MP1, the drain electrode of the N1 is connected to the output end of phase inverter iv, and the drain electrode of N1 is connected to the source level of MP1, and the source electrode of N1 is connected to low level end VS.The present invention can effectively inhibit negative sense drift and the leakage current of PMOS tube threshold voltage, improve the performance and reliability of level shifting circuit, improve quiescent dissipation.
Description
Technical field
The invention belongs to flash storage technical fields, are related to a kind of improvement SSLC level shifting circuit negative temperature bias
Instable restoring circuit.
Background technique
With the development of microelectric technique, portable electronic device especially in recent years, such as mobile phone, laptop
Fast development, the integrated level of semiconductor integrated circuit memory is higher and higher, and the requirement to transistor performance is also increasingly increased.
Therefore, the requirement of transistor reliability is also increased accordingly.In CMOS technology, minus gate voltage temperature instability (NBTI) meeting
The job stability of extreme influence PMOS.
NBTI(negative bias temperature instability) effect occur in the pmos devices, work as device
When the grid of part is under back bias voltage, the saturated drain current Idsat and mutual conductance Gm of device constantly reduce, threshold voltage is absolute
Value constantly increases.This NBTI effect for causing device performance to fail, can be with the increase and temperature of the bias voltage on grid
Raising and it is more significant.NBTI is mainly caused by the variation of silicon/oxide interface trapped charge and Oxide trapped charge
's.There is the dangling bonds of some Si in silicon/oxide interface of grid, such as Si3 ≡ Si and Si2O ≡ Si, generally
Think in process engineering, H can be combined with the dangling bonds of silicon and be formed SiH key, and referred to as hydrogen is passivated.But the meeting in device work
A high electric field is formed on grid, SiH key is easy for being interrupted at this time, forms H, H+ or H2.The dangling bonds of silicon are just in this way
A charge can be attracted, become positively charged interface trapped charge (Interface trapped charge).Institute's shape in this way
At unstable state we be referred to as interfacial state, this is a reversible electrochemical reaction, by the increasing of the bias voltage on grid
The raising influence for summing it up temperature is significant.The change rate and electric field strength of interface trapped charge are directly proportional, since electric field strength can be with
The raising of technology node and the reduction of oxidated layer thickness and increase (as shown in Figure 1), it can be considered that NBTI effect meeting
It is more significant with the raising of technology node.
Flash storage needs a positive high voltage to provide programming or erasing voltage in erasing and programming.Such case
Just need level shifting circuit that logic high is converted into required high voltage down.SSLC level shifting circuit is as shown in Figure 2.
Since in normal work, the source electrode of three PMOS transistors MP1, MP2 and MP3 can connect high voltage, when grid meets low level 0V,
There will be a very big pressure difference VPP between grid source, in this case, PMOS transistor will be subjected to more in normal work
Serious NBTI effect, directly affects the performance and used life of PMOS transistor, eventually leads to entire level shifting circuit not
It can work normally.
Summary of the invention
The object of the present invention is to overcome the problems of the prior art, and it is negative to provide a kind of improvement SSLC level shifting circuit
The instable restoring circuit of Bias Temperature, for alleviating the NBTI effect of PMOS transistor.
To realize above-mentioned technical purpose and the technique effect, the invention is realized by the following technical scheme:
A kind of restoring circuit improving SSLC level shifting circuit Negative Bias Temperature Instability, the circuit include SSLC electricity
Flat conversion circuit and NBTI effect recovery unit；
The SSLC level shifting circuit includes PMOS transistor MP1, MP2, MP3 and NMOS transistor MN1, MN2, MN3,
The MP1 is connected with the source electrode of MP3, and the grid of MP1 is separately connected the drain electrode of MP3 and MN3, and the drain electrode of MP1 is separately connected MP2
With the source electrode of MN1, the grid of the MP2 is connected with the grid of MN2, and the drain electrode of MP2 is separately connected drain electrode and the grid of MP3 of MN2
Pole；
The grid of the MN1 and the source electrode of drain electrode connection MP1, the source electrode of the MN2 connect low level end VSS, the grid of MN2
The source level of pole connection signal input terminal IN, the MN3 connect low level end VSS, the grid of MN3 is connected with the grid of MP3；
The NBTI effect recovery unit includes PMOS transistor P1 and P2, NMOS transistor N1, phase inverter iv and recovery
Enabled control terminal EN, the P1 connect high level end V with the source electrode of P2DDH, the grid of the P1 is connected to the output of phase inverter iv
The grid connection at end, the P2 restores enabled control terminal EN, and the drain electrode of P1 is connected to the source level of MP1, and the drain electrode of P2 is connected to MP1
Grid；
The drain electrode of the N1 is connected to the output end of phase inverter iv, and the drain electrode of N1 is connected to the source level of MP1, and the source electrode of N1 connects
It is connected to low level end VSS。
Further, the drain electrode of the P1 is separately connected drain electrode and the source electrode of MP3 of MN1, and the grid connection of the P2 is anti-
The input terminal of phase device iv, the drain electrode of P2 are connected to the grid of MP2.
Further, the common end of the drain interconnection of the drain electrode of grid, MP3, the drain electrode of MN3 and P2 of the MP1 is formed
The signal output end OUT of SSLC level shifting circuit.
Further, the common end of the drain interconnection of the grid of the MP2, the grid of MN2 and P2 turns as SSLC level
Change the signal input part IN of circuit.
Further, the grid of the MN1 is connected with drain electrode.
Further, the input terminal connection of the phase inverter iv restores enabled control terminal EN.
The beneficial effects of the present invention are:
1. restoring enabled control terminal EN input low level, then P2 when SSLC level shifting circuit works in reforestation practices
It is connected with N1, P1 shutdown, so that power input voltage separates, the grid of MP1 and MP2 are filled in the conducting of P2 for the shutdown of P1
Electricity effectively accelerates the NBTI effect resume speed of MP1, MP2 and MP3 in SSLC level shifting circuit, effectively to high level
It inhibits the negative sense of PMOS tube threshold voltage to drift about, improves the performance and reliability of level shifting circuit.
2. restoring enabled control terminal EN input low level, then P2 and N1 when level shifting circuit works in reforestation practices
Conducting, P1 shutdown, and the conducting of N1, it allows the gate-source capacitance of MP1 to store second-class charge and is released, so level shifting circuit
Upper and lower ends all connect low level VSS, that is to say, that the voltage swing of level shifting circuit upper and lower ends is 0, without voltage drop,
Leakage current effectively is inhibited, improves the quiescent dissipation of level shifting circuit.
Detailed description of the invention
Fig. 1 is the physical mechanism that NBTI effect generates；
Fig. 2 is SSLC level shifting circuit；
Fig. 3 is the restoring circuit of improvement SSLC level shifting circuit Negative Bias Temperature Instability of the invention.
Specific embodiment
It is below with reference to the accompanying drawings and in conjunction with the embodiments, next that the present invention will be described in detail.
Referring to shown in Fig. 2 and Fig. 3, a kind of recovery electricity improving SSLC level shifting circuit Negative Bias Temperature Instability
Road, the circuit include SSLC level shifting circuit and NBTI effect recovery unit；
The SSLC level shifting circuit includes PMOS transistor MP1, MP2, MP3 and NMOS transistor MN1, MN2, MN3,
The MP1 is connected with the source electrode of MP3, and the grid of MP1 is separately connected the drain electrode of MP3 and MN3, and the drain electrode of MP1 is separately connected MP2
With the source electrode of MN1, the grid of the MP2 is connected with the grid of MN2, and the drain electrode of MP2 is separately connected drain electrode and the grid of MP3 of MN2
Pole；
The grid of the MN1 and the source electrode of drain electrode connection MP1, the source electrode of the MN2 connect low level end VSS, the grid of MN2
The source level of pole connection signal input terminal IN, the MN3 connect low level end VSS, the grid of MN3 is connected with the grid of MP3；
The NBTI effect recovery unit includes PMOS transistor P1 and P2, NMOS transistor N1, phase inverter iv and recovery
Enabled control terminal EN, the P1 connect high level end V with the source electrode of P2DDH, the grid of the P1 is connected to the output of phase inverter iv
The grid connection at end, the P2 restores enabled control terminal EN, and the drain electrode of P1 is connected to the source level of MP1, and the drain electrode of P2 is connected to MP1
Grid；
The drain electrode of the N1 is connected to the output end of phase inverter iv, and the drain electrode of N1 is connected to the source level of MP1, and the source electrode of N1 connects
It is connected to low level end VSS。
The drain electrode of the P1 is separately connected drain electrode and the source electrode of MP3 of MN1, and the grid connection phase inverter iv's of the P2 is defeated
Enter end, the drain electrode of P2 is connected to the grid of MP2.
The common end of the drain interconnection of the drain electrode of grid, MP3 of the MP1, the drain electrode of MN3 and P2 forms SSLC level and turns
Change the signal output end OUT of circuit.
Letter of the common end of the drain interconnection of the grid of the MP2, the grid of MN2 and P2 as SSLC level shifting circuit
Number input terminal IN.
The grid of the MN1 is connected with drain electrode.
The input terminal connection of the phase inverter iv restores enabled control terminal EN.
The principle of the invention
When level shifting circuit is in reforestation practices, low level 0V is applied to the enabled control terminal EN of recovery, high threshold
PMOS transistor P2 is opened, and reverser iv exports high level signal end, so that NMOS transistor N1 is connected, SSLC level conversion electricity
The PMOS transistor P2 that PMOS transistor MP1 and MP2 in road pass through high threshold respectively is charged to high level signal end, meanwhile,
The source electrode of PMOS transistor MP1 and PMOS transistor MP3 are discharged VSS, level shifting circuit enter NBTI effect restore mould
Formula.
Reforestation practices effectively inhibit the negative sense of PMOS tube threshold voltage to drift about, improve the performance of level shifting circuit with
Reliability, meanwhile, in reforestation practices, the source electrode of PMOS transistor MP1 discharges into low level end by NMOS transistor N1
VSS, that is to say, that the voltage swing of level shifting circuit upper and lower ends is 0, without voltage drop, effectively inhibits leakage current, is improved
The quiescent dissipation of level shifting circuit.The performance of circuit is strengthened on the whole, and circuit structure is simple, has very high practical
Value and vast market prospect.
The foregoing is only a preferred embodiment of the present invention, is not intended to restrict the invention, for the skill of this field
For art personnel, the invention may be variously modified and varied.All within the spirits and principles of the present invention, made any to repair
Change, equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.
Claims (6)
1. a kind of restoring circuit for improving SSLC level shifting circuit Negative Bias Temperature Instability, which is characterized in that the circuit
Including SSLC level shifting circuit and NBTI effect recovery unit；
The SSLC level shifting circuit includes PMOS transistor MP1, MP2, MP3 and NMOS transistor MN1, MN2, MN3, described
MP1 is connected with the source electrode of MP3, and the grid of MP1 is separately connected the drain electrode of MP3 and MN3, the drain electrode of MP1 be separately connected MP2 and
The source electrode of MN1, the grid of the MP2 are connected with the grid of MN2, and the drain electrode of MP2 is separately connected drain electrode and the grid of MP3 of MN2；
The grid of the MN1 and the source electrode of drain electrode connection MP1, the source electrode of the MN2 connect low level end VSS, the grid company of MN2
Signal input part IN is met, the source level of the MN3 connects low level end VSS, the grid of MN3 is connected with the grid of MP3；
The NBTI effect recovery unit includes PMOS transistor P1 and P2, NMOS transistor N1, phase inverter iv and restores enabled
Control terminal EN, the P1 connect high level end V with the source electrode of P2DDH, the grid of the P1 is connected to the output end of phase inverter iv,
The grid connection of the P2 restores enabled control terminal EN, and the drain electrode of P1 is connected to the source level of MP1, and the drain electrode of P2 is connected to MP1's
Grid；
The drain electrode of the N1 is connected to the output end of phase inverter iv, and the drain electrode of N1 is connected to the source level of MP1, and the source electrode of N1 is connected to
Low level end VSS。
2. the restoring circuit according to claim 1 for improving SSLC level shifting circuit Negative Bias Temperature Instability,
It is characterized in that, the drain electrode of the P1 is separately connected drain electrode and the source electrode of MP3 of MN1, the grid connection phase inverter iv's of the P2
Input terminal, the drain electrode of P2 are connected to the grid of MP2.
3. the restoring circuit according to claim 1 for improving SSLC level shifting circuit Negative Bias Temperature Instability,
It is characterized in that, the common end of the drain interconnection of the drain electrode of grid, MP3 of the MP1, the drain electrode of MN3 and P2 forms SSLC level
The signal output end OUT of conversion circuit.
4. the restoring circuit according to claim 1 or 2 for improving SSLC level shifting circuit Negative Bias Temperature Instability,
It is characterized in that, the common end of the drain interconnection of the grid and P2 of the grid of the MP2, MN2 is as SSLC level shifting circuit
Signal input part IN.
5. the restoring circuit according to claim 3 for improving SSLC level shifting circuit Negative Bias Temperature Instability,
It is characterized in that, the grid of the MN1 is connected with drain electrode.
6. the restoring circuit according to claim 1 for improving SSLC level shifting circuit Negative Bias Temperature Instability,
It is characterized in that, the input terminal connection of the phase inverter iv restores enabled control terminal EN.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610154912.3A CN105827232B (en) | 2016-03-18 | 2016-03-18 | A kind of restoring circuit improving SSLC level shifting circuit Negative Bias Temperature Instability |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610154912.3A CN105827232B (en) | 2016-03-18 | 2016-03-18 | A kind of restoring circuit improving SSLC level shifting circuit Negative Bias Temperature Instability |
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| CN105827232A CN105827232A (en) | 2016-08-03 |
| CN105827232B true CN105827232B (en) | 2019-01-15 |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108347243B (en) * | 2017-01-25 | 2022-04-01 | 株式会社东海理化电机制作所 | Level shifter |
| CN107124177A (en) * | 2017-06-30 | 2017-09-01 | 深圳贝特莱电子科技股份有限公司 | A kind of capacitance coupling type level shifting circuit for fingerprint recognition driving chip |
| CN117013999A (en) * | 2023-06-09 | 2023-11-07 | 上海交通大学 | Circuit and device for accelerating recovery of integrated circuit aging |
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| US6788125B1 (en) * | 2003-05-28 | 2004-09-07 | Sun Microsystems, Inc. | Stable and accurate CMOS level shifter |
| CN102332907A (en) * | 2011-07-26 | 2012-01-25 | 华南理工大学 | Anti-NBTI (Negative-Bias Temperature Instability) effect reinforcing method based on CMOS (Complementary Metal-Oxide-Semiconductor Transistor) digital logic gate circuit |
| CN103187964A (en) * | 2011-12-31 | 2013-07-03 | 中芯国际集成电路制造(上海)有限公司 | Restoring circuit and restoring method for negative bias temperature instability |
| CN104579308A (en) * | 2014-12-23 | 2015-04-29 | 苏州宽温电子科技有限公司 | Restoring circuit for lowering negative bias temperature instability of level switching circuit |
| CN104579300A (en) * | 2014-12-23 | 2015-04-29 | 苏州宽温电子科技有限公司 | Restoring circuit for improving negative bias temperature instability of sensitive amplifier |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7995410B2 (en) * | 2009-06-26 | 2011-08-09 | Apple Inc. | Leakage and NBTI reduction technique for memory |
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2016
- 2016-03-18 CN CN201610154912.3A patent/CN105827232B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6788125B1 (en) * | 2003-05-28 | 2004-09-07 | Sun Microsystems, Inc. | Stable and accurate CMOS level shifter |
| CN102332907A (en) * | 2011-07-26 | 2012-01-25 | 华南理工大学 | Anti-NBTI (Negative-Bias Temperature Instability) effect reinforcing method based on CMOS (Complementary Metal-Oxide-Semiconductor Transistor) digital logic gate circuit |
| CN103187964A (en) * | 2011-12-31 | 2013-07-03 | 中芯国际集成电路制造(上海)有限公司 | Restoring circuit and restoring method for negative bias temperature instability |
| CN104579308A (en) * | 2014-12-23 | 2015-04-29 | 苏州宽温电子科技有限公司 | Restoring circuit for lowering negative bias temperature instability of level switching circuit |
| CN104579300A (en) * | 2014-12-23 | 2015-04-29 | 苏州宽温电子科技有限公司 | Restoring circuit for improving negative bias temperature instability of sensitive amplifier |
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Effective date of registration: 20231110 Address after: Room 606-4, Building 1, Jinji Lake Avenue, Suzhou Industrial Park, Suzhou, China (Jiangsu) Pilot Free Trade Zone, 215000, Jiangsu Province Patentee after: SUZHOU KUANWEN ELECTRONIC SCIENCE & TECHNOLOGY Co.,Ltd. Address before: 215000 No. 18 Suzhou River Road, Songling Town, Wujiang District, Suzhou, Jiangsu Patentee before: SUZHOU XINKUAN ELECTRONIC SCIENCE & TECHNOLOGY CO.,LTD. |