CN113114218A - Level conversion circuit with pseudo-differential amplification - Google Patents
Level conversion circuit with pseudo-differential amplification Download PDFInfo
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- CN113114218A CN113114218A CN202110430988.5A CN202110430988A CN113114218A CN 113114218 A CN113114218 A CN 113114218A CN 202110430988 A CN202110430988 A CN 202110430988A CN 113114218 A CN113114218 A CN 113114218A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
Abstract
The invention provides a level switching circuit with pseudo-differential amplification, which comprises: a first inverter module, a first end of which inputs a clock signal; a first differential amplifier module having a first end electrically connected to a second end of the first inverter module; a second differential amplifier module, wherein a first end of the second differential amplifier module is electrically connected with a third end of the first inverter module; and the first end of the level conversion module is electrically connected with the second end of the first differential amplifier module, and the second end of the level conversion module is electrically connected with the second end of the second differential amplifier module. The differential amplifier performs differential amplification on the input digital level and then performs level conversion, solves the problem that the circuit cannot work in a high-voltage domain, reduces the influence of quiescent current on the level conversion speed, and has the advantages of simple structure, low cost and wide application range.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a level conversion circuit with pseudo-differential amplification.
Background
The level conversion circuit is very common, the level conversion circuit is often used in a multi-voltage domain system, when the threshold value of a tube working in a high-voltage domain is close to the power supply voltage of a low-voltage domain, or under a high-speed clock, when the input clock is fast and the temperature is low, the threshold value of an NMOS tube is increased to be close to VDDL, the level overturning speed of the level conversion circuit is reduced, and even the level can not be normally overturned.
Disclosure of Invention
The invention provides a level conversion circuit with pseudo-differential amplification, and aims to solve the problem that a traditional level conversion circuit cannot normally operate when working in a high-voltage domain.
In order to achieve the above object, an embodiment of the present invention provides a level shift circuit with pseudo differential amplification, including:
a first inverter module, a first end of which inputs a clock signal;
a first differential amplifier module having a first end electrically connected to a second end of the first inverter module;
a second differential amplifier module, wherein a first end of the second differential amplifier module is electrically connected with a third end of the first inverter module;
a first end of the level conversion module is electrically connected with a second end of the first differential amplifier module, and a second end of the level conversion module is electrically connected with a second end of the second differential amplifier module;
and the second inverter module is electrically connected with the third end of the level conversion module.
Wherein the first inverter module comprises:
the first end of the first phase inverter is electrically connected with a power supply end, the second end of the first phase inverter is electrically connected with a grounding end, and a clock signal is input into the input end of the first phase inverter;
the first end of the second phase inverter is electrically connected with a power supply end, the second end of the second phase inverter is electrically connected with a grounding end, and the input end of the second phase inverter is electrically connected with the output end of the first phase inverter.
Wherein the first differential amplifier module comprises:
the source end of the first PMOS tube is electrically connected with a power supply end, and the gate end of the first PMOS tube is electrically connected with the drain end of the first PMOS tube;
the drain end of the first NMOS tube is electrically connected with the drain end of the first PMOS tube, the gate end of the first NMOS tube is electrically connected with the output end of the second phase inverter, and the source end of the first NMOS tube is electrically connected with the grounding end;
the source end of the second PMOS tube is electrically connected with the source end of the first PMOS tube, and the gate end of the second PMOS tube is electrically connected with the gate end of the first PMOS tube;
and the drain end of the second NMOS tube is electrically connected with the drain end of the second PMOS tube, the gate end of the second NMOS tube is electrically connected with the input end of the second phase inverter, and the source end of the second NMOS tube is electrically connected with the source end of the first NMOS tube.
Wherein the second differential amplifier module comprises:
the source end of the third PMOS tube is electrically connected with a power supply end, and the gate end of the third PMOS tube is electrically connected with the drain end of the third PMOS tube;
the drain end of the third NMOS tube is electrically connected with the drain end of the third PMOS tube, the gate end of the third NMOS tube is electrically connected with the input end of the second phase inverter, and the source end of the third NMOS tube is electrically connected with the grounding end;
a source terminal of the fourth PMOS tube is electrically connected with a source terminal of the third PMOS tube, and a gate terminal of the fourth PMOS tube is electrically connected with a gate terminal of the third PMOS tube;
and the drain end of the fourth NMOS tube is electrically connected with the drain end of the fourth PMOS tube, the gate end of the fourth NMOS tube is electrically connected with the output end of the second phase inverter, and the source end of the fourth NMOS tube is electrically connected with the source end of the third NMOS tube.
Wherein the level conversion module comprises:
a source end of the fifth PMOS tube is electrically connected with a power supply end;
the drain end of the fifth NMOS tube is electrically connected with the drain end of the fifth PMOS tube, the gate end of the fifth NMOS tube is electrically connected with the drain end of the second NMOS tube, and the source end of the fifth NMOS tube is electrically connected with the grounding end;
a source terminal of the sixth PMOS tube is electrically connected with a source terminal of the fifth PMOS tube, a gate terminal of the sixth PMOS tube is electrically connected with a drain terminal of the fifth PMOS tube, and a drain terminal of the sixth PMOS tube is electrically connected with a gate terminal of the fifth PMOS tube;
and the drain end of the sixth NMOS tube is electrically connected with the drain end of the sixth NMOS tube, the gate end of the sixth NMOS tube is electrically connected with the drain end of the fourth NMOS tube, and the source end of the sixth NMOS tube is electrically connected with the source end of the fifth NMOS tube.
Wherein the second inverter module comprises:
and a first end of the third phase inverter is electrically connected with a power supply end, a second end of the third phase inverter is electrically connected with a grounding end, and an input end of the third phase inverter is electrically connected with a drain end of the sixth NMOS transistor.
A seventh PMOS transistor is further disposed between the first PMOS transistor and the power supply terminal, a source terminal of the seventh PMOS transistor is electrically connected to the power supply terminal, a gate terminal of the seventh PMOS transistor is electrically connected to a gate terminal of the third PMOS transistor, and a drain terminal of the seventh PMOS transistor is electrically connected to the source terminal of the first PMOS transistor.
An eighth PMOS tube is further arranged between the third PMOS tube and the power supply end, the source end of the eighth PMOS tube is electrically connected with the power supply end, the gate end of the eighth PMOS tube is electrically connected with the gate end of the first PMOS tube, and the drain end of the eighth PMOS tube is electrically connected with the source end of the third PMOS tube.
The scheme of the invention has the following beneficial effects:
the level shift circuit with pseudo-differential amplification according to the embodiment of the invention performs differential amplification on the input digital level through the differential amplifier and then performs level shift, solves the problem that the circuit cannot work in a high voltage domain, reduces the influence of quiescent current on the level shift speed, and has the advantages of simple structure, low cost and wide application range.
Drawings
FIG. 1 is a block diagram of the present invention;
FIG. 2 is a specific circuit diagram of the first embodiment of the present invention;
FIG. 3 is a specific circuit diagram of a second embodiment of the present invention;
FIG. 4 is a diagram illustrating a comparison of output waveforms according to the present invention.
[ description of reference ]
1-a first inverter module; 2-a first differential amplifier module; 3-a second differential amplifier module; 4-a level conversion module; 5-a second inverter module; 6-a first inverter; 7-a second inverter; 8-a first PMOS tube; 9-first NMOS tube; 10-a second PMOS tube; 11-a second NMOS tube; 12-a third PMOS tube; 13-third NMOS tube; 14-fourth PMOS tube; 15-fourth NMOS transistor; 16-fifth PMOS tube; 17-fifth NMOS tube; 18-sixth PMOS tube; 19-sixth NMOS transistor; 20-a third inverter; 21-seventh PMOS tube; 22-eighth PMOS transistor.
Detailed Description
In order to make the technical problems, technical solutions and advantages of the present invention more apparent, the following detailed description is given with reference to the accompanying drawings and specific embodiments.
The invention provides a level conversion circuit with pseudo-differential amplification, aiming at the problem that the conventional level conversion circuit cannot normally operate when working in a high-voltage domain.
Example 1:
as shown in fig. 1 to 4, an embodiment of the present invention provides a level shift circuit with pseudo-differential amplification, including: the first inverter module 1 is provided, and a first end of the first inverter module 1 inputs a clock signal; a first differential amplifier module 2, a first end of the first differential amplifier module 2 being electrically connected to a second end of the first inverter module 1; a second differential amplifier module 3, wherein a first end of the second differential amplifier module 3 is electrically connected with a third end of the first inverter module 1; a level conversion module 4, wherein a first end of the level conversion module 4 is electrically connected to a second end of the first differential amplifier module 2, and a second end of the level conversion module 4 is electrically connected to a second end of the second differential amplifier module 3; and the second inverter module 5, wherein the second inverter module 5 is electrically connected with the third end of the level conversion module 4.
Wherein the first inverter module 1 comprises: a first end of the first inverter 6 is electrically connected with a power supply end, a second end of the first inverter 6 is electrically connected with a ground end, and a clock signal is input to an input end of the first inverter 6; and a first end of the second inverter 7 is electrically connected with a power supply end, a second end of the second inverter 7 is electrically connected with a ground end, and an input end of the second inverter 7 is electrically connected with an output end of the first inverter 6.
Wherein the first differential amplifier module 2 comprises: a source terminal of the first PMOS transistor 8 is electrically connected to a power supply terminal, and a gate terminal of the first PMOS transistor 8 is electrically connected to a drain terminal of the first PMOS transistor 8; a first NMOS tube 9, a drain terminal of the first NMOS tube 9 being electrically connected to a drain terminal of the first PMOS tube 8, a gate terminal of the first NMOS tube 9 being electrically connected to an output terminal of the second inverter 7, a source terminal of the first NMOS tube 9 being electrically connected to a ground terminal; a second PMOS transistor 10, a source terminal of the second PMOS transistor 10 is electrically connected to a source terminal of the first PMOS transistor 8, and a gate terminal of the second PMOS transistor 10 is electrically connected to a gate terminal of the first PMOS transistor 8; a drain terminal of the second NMOS tube 11 is electrically connected to a drain terminal of the second PMOS tube 10, a gate terminal of the second NMOS tube 11 is electrically connected to an input terminal of the second inverter 7, and a source terminal of the second NMOS tube 11 is electrically connected to a source terminal of the first NMOS tube 9.
Wherein the second differential amplifier module 3 comprises: a third PMOS transistor 12, a source terminal of the third PMOS transistor 12 is electrically connected to a power supply terminal, and a gate terminal of the third PMOS transistor 12 is electrically connected to a drain terminal of the third PMOS transistor 12; a third NMOS tube 13, a drain terminal of the third NMOS tube 13 being electrically connected to a drain terminal of the third PMOS tube 12, a gate terminal of the third NMOS tube 13 being electrically connected to an input terminal of the second inverter 7, and a source terminal of the third NMOS tube 13 being electrically connected to a ground terminal; a fourth PMOS transistor 14, a source terminal of the fourth PMOS transistor 14 is electrically connected to a source terminal of the third PMOS transistor 12, and a gate terminal of the fourth PMOS transistor 14 is electrically connected to a gate terminal of the third PMOS transistor 12; a fourth NMOS tube 15, a drain terminal of the fourth NMOS tube 15 is electrically connected to a drain terminal of the fourth PMOS tube 14, a gate terminal of the fourth NMOS tube 15 is electrically connected to an output terminal of the second inverter 7, and a source terminal of the fourth NMOS tube 15 is electrically connected to a source terminal of the third NMOS tube 13.
Wherein, the level converting module 4 includes: a fifth PMOS transistor 16, wherein a source terminal of the fifth PMOS transistor 16 is electrically connected to a power supply terminal; a fifth NMOS transistor 17, a drain terminal of the fifth NMOS transistor 17 being electrically connected to a drain terminal of the fifth PMOS transistor 16, a gate terminal of the fifth NMOS transistor 17 being electrically connected to a drain terminal of the second NMOS transistor 11, and a source terminal of the fifth NMOS transistor 17 being electrically connected to a ground terminal; a sixth PMOS transistor 18, a source terminal of the sixth PMOS transistor 18 is electrically connected to the source terminal of the fifth PMOS transistor 16, a gate terminal of the sixth PMOS transistor 18 is electrically connected to the drain terminal of the fifth PMOS transistor 16, and a drain terminal of the sixth PMOS transistor 18 is electrically connected to the gate terminal of the fifth PMOS transistor 16; a sixth NMOS tube 19, a drain terminal of the sixth NMOS tube 19 is electrically connected to a drain terminal of the sixth NMOS tube 19, a gate terminal of the sixth NMOS tube 19 is electrically connected to a drain terminal of the fourth NMOS tube 15, and a source terminal of the sixth NMOS tube 19 is electrically connected to a source terminal of the fifth NMOS tube 17.
Wherein the second inverter module 5 comprises: a first end of the third inverter 20 is electrically connected to a power supply terminal, a second end of the third inverter 20 is electrically connected to a ground terminal, and an input end of the third inverter 20 is electrically connected to a drain terminal of the sixth NMOS transistor 19.
In the level shift circuit with pseudo-differential amplification according to the above embodiment of the present invention, the difference between the point a and the point B in fig. 2 is amplified by the first differential amplifier module 2 and the second differential amplifier module 3, respectively, and then sent to the level shift module 4. mp3 denotes a first PMOS transistor 8, mn3 denotes a first NMOS transistor 9, the output at point D in fig. 2 is used as the input of the fifth NMOS transistor 17, the output at point F in fig. 2 is used as the input of the sixth NMOS transistor 19, and points C and D in fig. 2 are in the VDDH voltage domain, so that the fifth NMOS transistor 17 and the sixth NMOS transistor 19 can be turned on quickly, as shown by the y waveform in fig. 4, and Vout2 in fig. 2 can output normally. The level conversion circuit with pseudo-differential amplification in fig. 2 can be applied to a scene with high requirements on conversion speed regardless of quiescent current.
Example 2:
the embodiment of the invention provides a level conversion circuit with pseudo-differential amplification, which comprises: the first inverter module 1 is provided, and a first end of the first inverter module 1 inputs a clock signal; a first differential amplifier module 2, a first end of the first differential amplifier module 2 being electrically connected to a second end of the first inverter module 1; a second differential amplifier module 3, wherein a first end of the second differential amplifier module 3 is electrically connected with a third end of the first inverter module 1; a level conversion module 4, wherein a first end of the level conversion module 4 is electrically connected to a second end of the first differential amplifier module 2, and a second end of the level conversion module 4 is electrically connected to a second end of the second differential amplifier module 3; and the second inverter module 5, wherein the second inverter module 5 is electrically connected with the third end of the level conversion module 4.
Wherein the first inverter module 1 comprises: a first end of the first inverter 6 is electrically connected with a power supply end, a second end of the first inverter 6 is electrically connected with a ground end, and a clock signal is input to an input end of the first inverter 6; and a first end of the second inverter 7 is electrically connected with a power supply end, a second end of the second inverter 7 is electrically connected with a ground end, and an input end of the second inverter 7 is electrically connected with an output end of the first inverter 6.
Wherein the first differential amplifier module 2 comprises: a source terminal of the first PMOS transistor 8 is electrically connected to a power supply terminal, and a gate terminal of the first PMOS transistor 8 is electrically connected to a drain terminal of the first PMOS transistor 8; a first NMOS tube 9, a drain terminal of the first NMOS tube 9 being electrically connected to a drain terminal of the first PMOS tube 8, a gate terminal of the first NMOS tube 9 being electrically connected to an output terminal of the second inverter 7, a source terminal of the first NMOS tube 9 being electrically connected to a ground terminal; a second PMOS transistor 10, a source terminal of the second PMOS transistor 10 is electrically connected to a source terminal of the first PMOS transistor 8, and a gate terminal of the second PMOS transistor 10 is electrically connected to a gate terminal of the first PMOS transistor 8; a drain terminal of the second NMOS tube 11 is electrically connected to a drain terminal of the second PMOS tube 10, a gate terminal of the second NMOS tube 11 is electrically connected to an input terminal of the second inverter 7, and a source terminal of the second NMOS tube 11 is electrically connected to a source terminal of the first NMOS tube 9.
Wherein the second differential amplifier module 3 comprises: a third PMOS transistor 12, a source terminal of the third PMOS transistor 12 is electrically connected to a power supply terminal, and a gate terminal of the third PMOS transistor 12 is electrically connected to a drain terminal of the third PMOS transistor 12; a third NMOS tube 13, a drain terminal of the third NMOS tube 13 being electrically connected to a drain terminal of the third PMOS tube 12, a gate terminal of the third NMOS tube 13 being electrically connected to an input terminal of the second inverter 7, and a source terminal of the third NMOS tube 13 being electrically connected to a ground terminal; a fourth PMOS transistor 14, a source terminal of the fourth PMOS transistor 14 is electrically connected to a source terminal of the third PMOS transistor 12, and a gate terminal of the fourth PMOS transistor 14 is electrically connected to a gate terminal of the third PMOS transistor 12; a fourth NMOS tube 15, a drain terminal of the fourth NMOS tube 15 is electrically connected to a drain terminal of the fourth PMOS tube 14, a gate terminal of the fourth NMOS tube 15 is electrically connected to an output terminal of the second inverter 7, and a source terminal of the fourth NMOS tube 15 is electrically connected to a source terminal of the third NMOS tube 13.
Wherein, the level converting module 4 includes: a fifth PMOS transistor 16, wherein a source terminal of the fifth PMOS transistor 16 is electrically connected to a power supply terminal; a fifth NMOS transistor 17, a drain terminal of the fifth NMOS transistor 17 being electrically connected to a drain terminal of the fifth PMOS transistor 16, a gate terminal of the fifth NMOS transistor 17 being electrically connected to a drain terminal of the second NMOS transistor 11, and a source terminal of the fifth NMOS transistor 17 being electrically connected to a ground terminal; a sixth PMOS transistor 18, a source terminal of the sixth PMOS transistor 18 is electrically connected to the source terminal of the fifth PMOS transistor 16, a gate terminal of the sixth PMOS transistor 18 is electrically connected to the drain terminal of the fifth PMOS transistor 16, and a drain terminal of the sixth PMOS transistor 18 is electrically connected to the gate terminal of the fifth PMOS transistor 16; a sixth NMOS tube 19, a drain terminal of the sixth NMOS tube 19 is electrically connected to a drain terminal of the sixth NMOS tube 19, a gate terminal of the sixth NMOS tube 19 is electrically connected to a drain terminal of the fourth NMOS tube 15, and a source terminal of the sixth NMOS tube 19 is electrically connected to a source terminal of the fifth NMOS tube 17.
Wherein the second inverter module 5 comprises: a first end of the third inverter 20 is electrically connected to a power supply terminal, a second end of the third inverter 20 is electrically connected to a ground terminal, and an input end of the third inverter 20 is electrically connected to a drain terminal of the sixth NMOS transistor 19.
A seventh PMOS transistor 21 is further disposed between the first PMOS transistor 8 and the power supply terminal, a source terminal of the seventh PMOS transistor 21 is electrically connected to the power supply terminal, a gate terminal of the seventh PMOS transistor 21 is electrically connected to the gate terminal of the third PMOS transistor 12, and a drain terminal of the seventh PMOS transistor 21 is electrically connected to the source terminal of the first PMOS transistor 8.
An eighth PMOS transistor 22 is further disposed between the third PMOS transistor 12 and the power supply terminal, a source terminal of the eighth PMOS transistor 22 is electrically connected to the power supply terminal, a gate terminal of the eighth PMOS transistor 22 is electrically connected to the gate terminal of the first PMOS transistor 8, and a drain terminal of the eighth PMOS transistor 22 is electrically connected to the source terminal of the third PMOS transistor 12.
In the level shift circuit with the pseudo differential amplification according to the embodiment of the present invention, since the static current exists in the level shift circuit with the pseudo differential amplification shown in fig. 2, the power consumption of the chip may be increased. In fig. 2, when the level at point a is low and the level at point B is high, the first NMOS transistor 9 is turned on, the first NMOS tube 9 is connected with a diode, a current path exists in a branch of the first NMOS tube 9 connected with the first PMOS tube 8, when the level of the point a is high and the level of the point B is low, the third PMOS transistor 12 is diode connected, a current path exists in a branch circuit of the third NMOS transistor 13 connected with the third PMOS transistor 12, when the input end of the first inverter 6 is at high level or low level, static current exists in the level shift circuit with pseudo differential amplification, the level shift circuit with pseudo differential amplification shown in fig. 3, the modification of fig. 2 is that the seventh PMOS transistor 21 and the eighth PMOS transistor 22 are added, in fig. 3, when the level at point a is low, the level at point E is high, while the level at point B is high, and the level at point C is low. At this time, the first PMOS transistor 8 in fig. 3 is turned off, the first NMOS transistor 9 is turned on, at this time, no current path exists in the branch formed by the first NMOS transistor 9 and the second PMOS transistor 10, the fourth PMOS transistor 14 in fig. 3 is turned off, the third NMOS transistor 13 is turned on, and no current path exists in the branch formed by the third NMOS transistor 13 and the third PMOS transistor 12. The z waveform in fig. 4 represents the normal output of Vout3 in fig. 3, but the circuit structure in fig. 3 has a longer delay time than the circuit structure in fig. 2, and the circuit in fig. 2 or fig. 3 is selected for level conversion according to actual needs and requirements. As shown in fig. 4, the h waveform is an output waveform of the conventional level shift circuit, the x waveform is an input signal waveform, the y waveform is an output waveform of the level shift circuit with pseudo differential amplification of fig. 2, and the z waveform is an output waveform of the level shift circuit with pseudo differential amplification of fig. 3.
The level shift circuit with pseudo-differential amplification according to the embodiment of the invention performs differential amplification on the input digital level through the differential amplifier and then performs level shift, solves the problem that the circuit cannot work in a high voltage domain, reduces the influence of quiescent current on the level shift speed, and has the advantages of simple structure, low cost and wide application range.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (8)
1. A level shift circuit with pseudo-differential amplification, comprising:
a first inverter module, a first end of which inputs a clock signal;
a first differential amplifier module having a first end electrically connected to a second end of the first inverter module;
a second differential amplifier module, wherein a first end of the second differential amplifier module is electrically connected with a third end of the first inverter module;
a first end of the level conversion module is electrically connected with a second end of the first differential amplifier module, and a second end of the level conversion module is electrically connected with a second end of the second differential amplifier module;
and the second inverter module is electrically connected with the third end of the level conversion module.
2. The level shift circuit with pseudo-differential amplification of claim 1, wherein the first inverter module comprises:
the first end of the first phase inverter is electrically connected with a power supply end, the second end of the first phase inverter is electrically connected with a grounding end, and a clock signal is input into the input end of the first phase inverter;
the first end of the second phase inverter is electrically connected with a power supply end, the second end of the second phase inverter is electrically connected with a grounding end, and the input end of the second phase inverter is electrically connected with the output end of the first phase inverter.
3. The level shift circuit with pseudo-differential amplification of claim 2, wherein the first differential amplifier module comprises:
the source end of the first PMOS tube is electrically connected with a power supply end, and the gate end of the first PMOS tube is electrically connected with the drain end of the first PMOS tube;
the drain end of the first NMOS tube is electrically connected with the drain end of the first PMOS tube, the gate end of the first NMOS tube is electrically connected with the output end of the second phase inverter, and the source end of the first NMOS tube is electrically connected with the grounding end;
the source end of the second PMOS tube is electrically connected with the source end of the first PMOS tube, and the gate end of the second PMOS tube is electrically connected with the gate end of the first PMOS tube;
and the drain end of the second NMOS tube is electrically connected with the drain end of the second PMOS tube, the gate end of the second NMOS tube is electrically connected with the input end of the second phase inverter, and the source end of the second NMOS tube is electrically connected with the source end of the first NMOS tube.
4. The level shift circuit with pseudo-differential amplification of claim 3, wherein the second differential amplifier module comprises:
the source end of the third PMOS tube is electrically connected with a power supply end, and the gate end of the third PMOS tube is electrically connected with the drain end of the third PMOS tube;
the drain end of the third NMOS tube is electrically connected with the drain end of the third PMOS tube, the gate end of the third NMOS tube is electrically connected with the input end of the second phase inverter, and the source end of the third NMOS tube is electrically connected with the grounding end;
a source terminal of the fourth PMOS tube is electrically connected with a source terminal of the third PMOS tube, and a gate terminal of the fourth PMOS tube is electrically connected with a gate terminal of the third PMOS tube;
and the drain end of the fourth NMOS tube is electrically connected with the drain end of the fourth PMOS tube, the gate end of the fourth NMOS tube is electrically connected with the output end of the second phase inverter, and the source end of the fourth NMOS tube is electrically connected with the source end of the third NMOS tube.
5. The level shift circuit with pseudo-differential amplification of claim 4, wherein the level shift module comprises:
a source end of the fifth PMOS tube is electrically connected with a power supply end;
the drain end of the fifth NMOS tube is electrically connected with the drain end of the fifth PMOS tube, the gate end of the fifth NMOS tube is electrically connected with the drain end of the second NMOS tube, and the source end of the fifth NMOS tube is electrically connected with the grounding end;
a source terminal of the sixth PMOS tube is electrically connected with a source terminal of the fifth PMOS tube, a gate terminal of the sixth PMOS tube is electrically connected with a drain terminal of the fifth PMOS tube, and a drain terminal of the sixth PMOS tube is electrically connected with a gate terminal of the fifth PMOS tube;
and the drain end of the sixth NMOS tube is electrically connected with the drain end of the sixth NMOS tube, the gate end of the sixth NMOS tube is electrically connected with the drain end of the fourth NMOS tube, and the source end of the sixth NMOS tube is electrically connected with the source end of the fifth NMOS tube.
6. The level shift circuit with pseudo-differential amplification of claim 5, wherein the second inverter module comprises:
and a first end of the third phase inverter is electrically connected with a power supply end, a second end of the third phase inverter is electrically connected with a grounding end, and an input end of the third phase inverter is electrically connected with a drain end of the sixth NMOS transistor.
7. The level shift circuit with pseudo-differential amplification according to claim 6, wherein a seventh PMOS transistor is further disposed between the first PMOS transistor and the power supply terminal, a source terminal of the seventh PMOS transistor is electrically connected to the power supply terminal, a gate terminal of the seventh PMOS transistor is electrically connected to the gate terminal of the third PMOS transistor, and a drain terminal of the seventh PMOS transistor is electrically connected to the source terminal of the first PMOS transistor.
8. The level shift circuit with pseudo-differential amplification according to claim 7, wherein an eighth PMOS transistor is further disposed between the third PMOS transistor and the power supply terminal, a source terminal of the eighth PMOS transistor is electrically connected to the power supply terminal, a gate terminal of the eighth PMOS transistor is electrically connected to the gate terminal of the first PMOS transistor, and a drain terminal of the eighth PMOS transistor is electrically connected to the source terminal of the third PMOS transistor.
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| US20030067323A1 (en) * | 2001-10-09 | 2003-04-10 | Samsung Electronics Co., Ltd. | Signal converting system having level converter for use in high speed semiconductor device and method therefor |
| US20050134314A1 (en) * | 2003-12-18 | 2005-06-23 | Prather Stephen M. | Method and circuit for translating a differential signal to complmentary CMOS levels |
| JP2011172065A (en) * | 2010-02-19 | 2011-09-01 | Nec Engineering Ltd | Level conversion circuit |
| CN105915207A (en) * | 2016-04-11 | 2016-08-31 | 电子科技大学 | Electric level shifting circuit |
| CN106656160A (en) * | 2016-09-20 | 2017-05-10 | 上海集成电路研发中心有限公司 | High-speed potential conversion circuit |
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Application publication date: 20210713 |