CN107453737A - A kind of low power consumption comparator circuit - Google Patents
A kind of low power consumption comparator circuit Download PDFInfo
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- CN107453737A CN107453737A CN201710676863.4A CN201710676863A CN107453737A CN 107453737 A CN107453737 A CN 107453737A CN 201710676863 A CN201710676863 A CN 201710676863A CN 107453737 A CN107453737 A CN 107453737A
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- nmos tube
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
- H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
- H03K5/249—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors using clock signals
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- Nonlinear Science (AREA)
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- Logic Circuits (AREA)
- Manipulation Of Pulses (AREA)
Abstract
The invention discloses a kind of low power consumption comparator circuit, including:Pre-amplification circuit, for input differential signal IP/IN to be carried out into pre-amplification under power control signal VCON control；Dynamic latching circuit, for the difference output OP/ON of the pre-amplification circuit to be carried out into dynamic latch under the control of clock signal clk；Power control circuit, for generating the power control signal VCON according to the output VOUT+/VOUT of the dynamic latching circuit under the control of clock signal clk, by the present invention, the power consumption of comparator circuit can be reduced.
Description
Technical field
The present invention relates to a kind of circuit, more particularly to a kind of low power consumption comparator circuit.
Background technology
Comparator is the conventional module in analog circuit, typically in ADC (Analog-to-Digital Converter, mould
Number converter), OSC (oscillator, oscillator) and it is various detection circuit in be all widely used.
In order to realize the comparison of quick high accuracy, a kind of common comparator architecture is pre-amplification (Pre-Amplifier)
The structure combined with dynamic latch (Dynamic Latch), as shown in figure 1, the comparator includes pre-amplification circuit 10 and moved
State latch cicuit 20, wherein, pre-amplification circuit (Pre-Amplifier) 10 is by NMOS tube MN1, MN2, MN3 and PMOS
MP1, MP2, MP3, MP4 are formed, for input differential signal IP/IN to be carried out into pre-amplification；Dynamic latching circuit (Dynamic
Latch) 20 it is made up of NMOS tube MN4, MN5, MN6, MN7, MN8 and PMOS MP5, MP6, MP7, MP8, in clock
The difference output OP/ON of pre-amplification circuit (Pre-Amplifier) 10 is subjected to dynamic latch under CLK control.
However, although this comparator circuit can be realized quick and compared in high precision, its pre-amplification circuit (Pre-
Amplifier too many power consumption) is consumed, causes the power consumption of circuit higher.
The content of the invention
To overcome above-mentioned the shortcomings of the prior art, the purpose of the present invention is to provide a kind of low power consumption comparator electricity
Road, to reduce the power consumption of circuit.
In view of the above and other objects, the present invention proposes a kind of low power consumption comparator circuit, including:
Pre-amplification circuit, for being put input differential signal IP/IN in advance under power control signal VCON control
Greatly；
Dynamic latching circuit, under the control of clock signal clk by the difference output OP/ON of the pre-amplification circuit
Carry out dynamic latch；
Power control circuit, for the output VOUT under the control of clock signal clk according to the dynamic latching circuit
+/VOUT- generates the power control signal VCON.
Further, the power control circuit includes a biconditional gate and one and door.
Further, two inputs of the biconditional gate connect the output VOUT+/VOUT- of the dynamic latching circuit,
Its output end connection input with door, it is described to be connected clock signal clk with another input of door, it is described and door
Output end VCON is connected to the pre-amplification circuit.
Further, the pre-amplification circuit includes the first NMOS tube, the second NMOS tube, the 3rd NMOS tube and first
PMOS, the second PMOS, the 3rd PMOS, the 4th PMOS.
Further, first PMOS, the second PMOS, the 3rd PMOS, the source electrode of the 4th PMOS connect power supply,
The source ground of 3rd NMOS tube, the grid and drain electrode short circuit of the 3rd PMOS and the drain electrode with first PMOS,
The grid of second PMOS, the drain electrode of first NMOS tube and the dynamic latching circuit are connected to form pre-amplification circuit
With phase output node OP, the grid and drain electrode short circuit of the 4th PMOS and the drain electrode with second PMOS, the first PMOS
Grid, the second NMOS tube drain electrode and the dynamic latching circuit be connected to form the anti-phase output section of the pre-amplification circuit
Point ON, in-phase input signals for 1 IP are connected to the grid of second NMOS tube, and rp input signal IN is connected to described first
The grid of NMOS tube, the source electrode of first NMOS tube and the second NMOS tube is connected to the drain electrode of the 3rd NMOS tube, described
The grid of 3rd NMOS tube is connected to the output end VCON with door.
Further, the dynamic latching circuit includes the 4th NMOS tube, the 5th NMOS tube, the 6th NMOS tube, the 7th
NMOS tube, the 8th NMOS tube and the 5th PMOS, the 6th PMOS, the 7th PMOS, the 8th PMOS.
Further, the 5th PMOS, the 6th PMOS, the 7th PMOS, the source electrode of the 8th PMOS connect power supply,
The source ground of 8th NMOS tube, the 7th PMOS, the grid of the 8th PMOS are connected to clock signal clk, institute
State the draining of the 7th PMOS, the draining of the 5th PMOS, the leakage of the grid, the 6th NMOS tube of the 6th PMOS
Pole, the grid of the 7th the NMOS tube group that is connected with an input of the biconditional gate claim anti-phase output node VOUT-, and the described 8th
The drain electrode of PMOS, the drain electrode of the 6th PMOS, the grid of the 5th PMOS, the drain electrode of the 7th NMOS tube, the 6th NMOS tube
Another input of grid and the biconditional gate is connected to form same phase output node VOUT+, the source electrode of the 6th NMOS tube
Connecting the drain electrode of the 4th NMOS tube, the source electrode of the 7th NMOS tube connects the drain electrode of the 5th NMOS tube, and described the
The source electrode of four NMOS tubes and the 5th NMOS tube is connected to the drain electrode of the 8th NMOS tube, the grid connection of the 8th NMOS tube
Clock signal clk.
Further, when clock signal clk is 0, the 7th PMOS, the 8th PMOS saturation conduction, described the
The drain electrode of seven PMOSs, the 8th PMOS is the anti-phase output node ON of the pre-amplification circuit, is with phase output node OP
High level VCC, while the 8th NMOS tube is ended, the dynamic latching circuit is in reset state, and the biconditional gate is defeated
Go out high level, the described and output VCON of door is 0, now turns off the electric current of the pre-amplification circuit.
Further, when clock signal clk changes to 1 from 0, the 7th PMOS, the cut-off of the 8th PMOS, while institute
The 8th NMOS tube saturation conduction is stated, the dynamic latching circuit enters working condition, and the biconditional gate exports logic 1, described
It is 1 with gate output terminal VCON, now opens the electric current of the pre-amplification circuit, comparator circuit work.
Further, when the further positive feedback of the dynamic latching circuit so that most output voltage is locked as VOUT+ at last
For 1, VOUT- is 0, and after comparator compares result, comparative result latches, and the biconditional gate exports low level 0, it is described with
The output VCON of door is 0, and the output VCON low levels turn off the electric current of the pre-amplification circuit.
Compared with prior art, a kind of low-power consumption comparison circuit of the present invention makes pre-amplification electric by increasing power control circuit
The electric current on road is all off in the most of the time, is only opened when relatively, is greatly reduced the power consumption of circuit, realize
The effective power consumption control of circuit, in practice it has proved that, the power consumption of circuit can reduce by more than 80%.
Brief description of the drawings
Fig. 1 is a kind of circuit diagram of low power consumption comparator circuit of prior art；
Fig. 2 is a kind of circuit structure diagram of low power consumption comparator circuit of the present invention；
Fig. 3 is the simulation result figure of the specific embodiment of the invention.
Embodiment
Below by way of specific instantiation and embodiments of the present invention are described with reference to the drawings, those skilled in the art can
Understand the further advantage and effect of the present invention easily by content disclosed in the present specification.The present invention can also pass through other differences
Instantiation implemented or applied, the various details in this specification also can be based on different viewpoints with application, without departing substantially from
Various modifications and change are carried out under the spirit of the present invention.
Fig. 2 is a kind of circuit structure diagram of low power consumption comparator circuit of the present invention.A kind of as shown in Fig. 2 low work(of the present invention
Comparator circuit is consumed, including:Pre-amplification circuit (Pre-Amplifier) 10, dynamic latching circuit (Dynamic latch) 20 Hes
Power control circuit (Power Control) 30.Wherein, pre-amplification circuit (Pre-Amplifier) 10 by NMOS tube MN1,
MN2, MN3 and PMOS MP1, MP2, MP3, MP4 composition, under power control signal VCON control by input difference
Signal IP/IN carries out pre-amplification；Dynamic latching circuit (Dynamic latch) 20 is by NMOS tube MN4, MN5, MN6, MN7, MN8
And PMOS MP5, MP6, MP7, MP8 composition, under clock CLK control by pre-amplification circuit (Pre-
Amplifier) 10 difference output OP/ON carries out dynamic latch；Power control circuit (Power Control) 30 is by XNOR
Door (XNOR) X1 and with door (AND) A1, under clock CLK control according to dynamic latching circuit (Dynamic latch)
20 output VOUT+/VOUT- generation power control signals VCON.
PMOS MP1, MP2, MP3, MP4, MP5, MP6, MP7, MP8 source electrode meet power supply VCC, NMOS tube MN3, MN8
Source ground GND, PMOS MP3 grid and drain electrode short circuit and the drain electrode with PMOS MP1, PMOS MP2 grid, NMOS
Pipe MN1 drain electrode and NMOS tube MN4 grid are connected to form the same phase output section of pre-amplification circuit (Pre-Amplifier) 10
Point OP, PMOS MP4 grid and drain electrode short circuit and drain electrode with PMOS MP2, PMOS MP1 grid, NMOS tube MN2
Drain electrode and NMOS tube MN5 grid are connected to form the anti-phase output node ON of pre-amplification circuit (Pre-Amplifier) 10, together
Phase input signal IP is connected to NMOS tube MN2 grid, and rp input signal IN is connected to NMOS tube MN1 grid, NMOS tube
MN1 and MN2 source electrode is connected to NMOS tube MN3 drain electrode, and NMOS tube MN3 grid is connected to and door (AND) A1 output end
VCON；The grid of PMOS MP7, MP8 is connected to clock CLK, PMOS MP7 drain electrode, PMOS MP5 drain electrode, PMOS
MP6 grid, NMOS tube MN6 drain electrode, NMOS tube MN7 grid are connected to organize with biconditional gate (XNOR) X1 input and claimed
Anti-phase output node VOUT-, PMOS MP8 drain electrode, PMOS MP6 drain electrode, PMOS MP5 grid, NMOS tube MN7
Drain electrode, NMOS tube MN6 grid are connected to organize with biconditional gate (XNOR) X1 another input and claimed with phase output node VOUT+,
NMOS tube MN6 source electrode connection NMOS tube MN4 drain electrode, NMOS tube MN7 source electrode connection NMOS tube MN5 drain electrode, NMOS tube
MN4 and MN5 source electrode is connected to NMOS tube MN8 drain electrode, NMOS tube MN8 grid connection clock CLK；Biconditional gate (XNOR)
X1 output end is connected to and door (AND) A1 input, clock CLK is connected with door (AND) A1 another input, with door
(AND) A1 output end VCON is connected to NMOS tube MN3 grid.
Illustrate the principle of the present invention below：
As CLK=0, PMOS MP7, MP8 saturation conduction, the drain electrode of PMOS MP7, MP8 is pre-amplification circuit (Pre-
Amplifier) 10 anti-phase output node ON, be high level VCC with phase output node OP, while NMOS tube MN8 ends, and moves
State latch cicuit (Dynamic latch) is in reset states, biconditional gate (XNOR) X1 output high level, because clock is believed
Number CLK is 0, and the output VCON with door (AND) A1 is 0, can now be closed the electric current of pre-amplification circuit (Pre-Amplifier)
Fall
When CLK changes to 1 from 0, the cut-off of PMOS MP7, MP8, while NMOS tube MN8 saturation conduction dynamic latching circuits
(Dynamic latch) enters working condition, it is assumed that the anti-phase output node ON electricity of pre-amplification circuit (Pre-Amplifier) 10
Force down in same phase output node OP voltages, then NMOS tube MN4 is faster than NMOS tube MN5 conductings, so as to NMOS tube MN4 drain electrode
Voltage is that NMOS tube MN6 source voltage is lower by the i.e. NMOS tube MN7 of the drain voltage than NMOS tube MN5 source voltage,
The drain voltage i.e. VOUT- for causing NMOS tube MN6 is less than NMOS tube MN7 drain voltage i.e. VOUT+ by this, with phase output voltage
VOUT+ will further speed up the cut-off that NMOS tube MN6 is turned on and accelerated NMOS tube MN7 higher than reversed phase output voltage VOUT-, same
Phase output voltage VO UT+ not yet reaches logic high 1 and before reversed phase output voltage VOUT- not yet reaches logic low 0, different
Nor gate (XNOR) will export logic 1, be 1 with door (AND) A1 output ends VCON because now clock CLK is height, now will be pre-
The electric current of amplifying circuit (Pre-Amplifier) is opened, comparator work
When the further positive feedback of latch so that most output voltage is locked as that VOUT+ is 1 at last and VOUT- is 0, compares
After device compares result, comparative result latches, biconditional gate (XNOR) X1 output low levels 0, although clock signal clk is 1, with
Door (AND) A1 output VCON turns off the electric current of pre-amplification circuit (Pre-Amplifier) for 0, VCON low levels, further
Reduce power consumption.
The mark that comparator compares result is VOUT+, and it is low that VOUT- mono-, which is high one,.
The anti-phase output node ON voltages of pre-amplification circuit (Pre-Amplifier) 10 are higher than in same phase output node OP electricity
Equally biconditional gate can be made to export logic low 0 after comparative result is obtained during pressure, also result in power control signal
VCON is logic low 0 so that pre-amplification circuit (Pre-Amplifier) 10 is closed.In the specific embodiment of the invention,
The truth table of its power control circuit is as shown in table 1 below：
The power control circuit truth table of table 1
Wherein,
Fig. 3 is the simulation result figure of the specific embodiment of the invention.In the specific embodiment of the invention, VCON control pre-amplifications
The tail current of circuit (Pre-Amplifier), in the most of the time, the electric current quilt of pre-amplification circuit (Pre-Amplifier)
Shut-off, only opened when relatively, therefore power consumption drops to 4.5uA from 21.8uA, it is close to reduce 80%.
In summary, a kind of low-power consumption comparison circuit of the present invention makes the electricity of pre-amplification circuit by increasing power control circuit
Stream is all off in the most of the time, is only opened when relatively, is greatly reduced the power consumption of circuit, realize circuit
Effective power consumption controls purpose, in practice it has proved that, the power consumption of circuit can reduce by more than 80%.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.Any
Art personnel can be modified above-described embodiment and changed under the spirit and scope without prejudice to the present invention.Therefore,
The scope of the present invention, should be as listed by claims.
Claims (10)
1. a kind of low power consumption comparator circuit, including:
Pre-amplification circuit, for input differential signal IP/IN to be carried out into pre-amplification under power control signal VCON control；
Dynamic latching circuit, for carrying out the difference output OP/ON of the pre-amplification circuit under the control of clock signal clk
Dynamic latch；
Power control circuit, for the output VOUT+ under the control of clock signal clk according to the dynamic latching circuit/
VOUT- generates the power control signal VCON.
A kind of 2. low power consumption comparator circuit as claimed in claim 1, it is characterised in that：The power control circuit includes one
Biconditional gate and one and door.
A kind of 3. low power consumption comparator circuit as claimed in claim 2, it is characterised in that：Two inputs of the biconditional gate
Connect the output VOUT+/VOUT- of the dynamic latching circuit, its output end connection input with door, described and door
Another input connection clock signal clk, it is described to be connected to the pre-amplification circuit with door output end VCON.
A kind of 4. low power consumption comparator circuit as claimed in claim 3, it is characterised in that：The pre-amplification circuit includes first
NMOS tube, the second NMOS tube, the 3rd NMOS tube and the first PMOS, the second PMOS, the 3rd PMOS, the 4th PMOS.
A kind of 5. low power consumption comparator circuit as claimed in claim 4, it is characterised in that：First PMOS, second
PMOS, the 3rd PMOS, the source electrode of the 4th PMOS connect power supply, the source ground of the 3rd NMOS tube, the 3rd PMOS
Grid and drain electrode short circuit and drain electrode, the leakage of the grid of the second PMOS, first NMOS tube with first PMOS
Pole and the dynamic latching circuit are connected to form the same phase output node OP of pre-amplification circuit, the grid of the 4th PMOS and leakage
It is extremely short to connect and the drain electrode with second PMOS, the grid of the first PMOS, the drain electrode of the second NMOS tube and the dynamic
Anti-phase output the node ON, in-phase input signals for 1 IP that latch cicuit is connected to form the pre-amplification circuit are connected to described second
The grid of NMOS tube, rp input signal IN are connected to the grid of first NMOS tube, first NMOS tube and second
The source electrode of NMOS tube is connected to the drain electrode of the 3rd NMOS tube, and the grid of the 3rd NMOS tube is connected to described defeated with door
Go out to hold VCON.
A kind of 6. low power consumption comparator circuit as claimed in claim 5, it is characterised in that：The dynamic latching circuit includes the
Four NMOS tubes, the 5th NMOS tube, the 6th NMOS tube, the 7th NMOS tube, the 8th NMOS tube and the 5th PMOS, the 6th PMOS
Pipe, the 7th PMOS, the 8th PMOS.
A kind of 7. low power consumption comparator circuit as claimed in claim 6, it is characterised in that：5th PMOS, the 6th
PMOS, the 7th PMOS, the source electrode of the 8th PMOS connect power supply, the source ground of the 8th NMOS tube, and the described 7th
PMOS, the grid of the 8th PMOS are connected to clock signal clk, the draining of the 7th PMOS, the 5th PMOS
Drain, the drain electrode of the grid of the 6th PMOS, the 6th NMOS tube, grid and the biconditional gate of the 7th NMOS tube
One input is connected to form anti-phase output node VOUT-, the drain electrode of the 8th PMOS, the drain electrode of the 6th PMOS, the 5th
The grid of PMOS, the drain electrode of the 7th NMOS tube, the grid of the 6th NMOS tube are connected with another input of the biconditional gate
For composition with phase output node VOUT+, the source electrode of the 6th NMOS tube connects the drain electrode of the 4th NMOS tube, and the described 7th
The source electrode of NMOS tube connects the drain electrode of the 5th NMOS tube, and the source electrode of the 4th NMOS tube and the 5th NMOS tube is connected to institute
State the drain electrode of the 8th NMOS tube, the grid connection clock signal clk of the 8th NMOS tube.
A kind of 8. low power consumption comparator circuit as claimed in claim 7, it is characterised in that：When clock signal clk is 0, institute
The 7th PMOS, the 8th PMOS saturation conduction are stated, the drain electrode of the 7th PMOS, the 8th PMOS is the pre-amplification electricity
The anti-phase output node ON on road, it is high level VCC with phase output node OP, while the 8th NMOS tube is ended, it is described dynamic
State latch cicuit is in reset state, and the biconditional gate exports high level, and the described and output VCON of door is 0, now by institute
The electric current for stating pre-amplification circuit is turned off.
A kind of 9. low power consumption comparator circuit as claimed in claim 8, it is characterised in that：When clock signal clk changes to 1 from 0
When, the 7th PMOS, the cut-off of the 8th PMOS, while the 8th NMOS tube saturation conduction, the dynamic latching circuit
Into working condition, the biconditional gate exports logic 1, and described and gate output terminal VCON is 1, now by the pre-amplification circuit
Electric current open, comparator circuit work.
A kind of 10. low power consumption comparator circuit as claimed in claim 9, it is characterised in that：When the dynamic latching circuit enters
One step positive feedback so that most output voltage is locked as that VOUT+ is 1 at last and VOUT- is 0, after comparator compares result, compares
As a result latch, the biconditional gate exports low level 0, and described with the output VCON of door is 0, and the output VCON low levels are by institute
The electric current for stating pre-amplification circuit is turned off.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710676863.4A CN107453737A (en) | 2017-08-09 | 2017-08-09 | A kind of low power consumption comparator circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710676863.4A CN107453737A (en) | 2017-08-09 | 2017-08-09 | A kind of low power consumption comparator circuit |
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| Publication Number | Publication Date |
|---|---|
| CN107453737A true CN107453737A (en) | 2017-12-08 |
Family
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Family Applications (1)
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| CN201710676863.4A Pending CN107453737A (en) | 2017-08-09 | 2017-08-09 | A kind of low power consumption comparator circuit |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108347234A (en) * | 2017-12-29 | 2018-07-31 | 成都华微电子科技有限公司 | high-speed comparator circuit based on inverter design |
| CN110568896A (en) * | 2018-06-05 | 2019-12-13 | 中芯国际集成电路制造(北京)有限公司 | Comparator, integrated circuit and method |
| CN111510118A (en) * | 2020-05-07 | 2020-08-07 | 西安交通大学 | Low-power-consumption high-speed comparator |
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| CN105680834A (en) * | 2016-01-11 | 2016-06-15 | 中国科学技术大学先进技术研究院 | High-speed low-power-consumption dynamic comparator |
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| CN101282117A (en) * | 2007-04-05 | 2008-10-08 | 中国科学院微电子研究所 | Dynamic comparer |
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| CN111510118B (en) * | 2020-05-07 | 2021-12-28 | 西安交通大学 | Low-power-consumption high-speed comparator |
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| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20171208 |