CN105159382B - Linear voltage regulator - Google Patents
Linear voltage regulator Download PDFInfo
- Publication number
- CN105159382B CN105159382B CN201510507257.0A CN201510507257A CN105159382B CN 105159382 B CN105159382 B CN 105159382B CN 201510507257 A CN201510507257 A CN 201510507257A CN 105159382 B CN105159382 B CN 105159382B
- Authority
- CN
- China
- Prior art keywords
- nmos tube
- circuit
- pmos
- connects
- grid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Amplifiers (AREA)
Abstract
The invention discloses a kind of linear voltage regulator, including: error amplifier, Voltage Cortrol device and feedback network.Error amplifier includes amplifier body, the first tail current source and active load；Amplifier body is differential configuration, and source all connects the first tail current source, and load end connects the first difference active load and the second difference active load of mirror image each other；Error amplifier also includes accelerating start-up circuit, accelerate the mirror image circuit that Part I circuit is the first difference active load of start-up circuit, the Part II circuit accelerating start-up circuit connects Part I circuit, accelerating the mirror image circuit that Part III circuit is described Part II circuit of start-up circuit, Part III circuit provides the second tail current to the source of two difference channels of amplifier body.The present invention can improve toggle speed.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit, particularly relate to a kind of linear voltage regulator.
Background technology
Linear voltage regulator is widely used in integrated circuits, as it is shown in figure 1, be the circuit diagram of existing linear voltage regulator；
Existing linear voltage regulator includes error amplifier, Voltage Cortrol device and feedback network.
Error amplifier includes the amplifier body being made up of NMOS tube MN1, MN2, MN3 and MN4, and amplifier
Body is the differential amplifier arrangements of cascade, and PMOS MP1, MP2, MP3 and MP4 form active load, NMOS
Pipe MN5 forms tail current source；Bias voltage VB3 is connected to the grid of NMOS tube MN5, and bias voltage VB1 connects
To NMOS tube MN2 and the grid of MN4, bias voltage VB2 is connected to the grid of PMOS MP2 and MP4.
Voltage Cortrol device is made up of NMOS tube MDRV, and the source electrode of NMOS tube MDRV is defeated as output voltage OUT's
Going out end, feedback network is formed by resistance R1 and R2 series connection.The grid of NMOS tube MN1 meets reference voltage VREF, NMOS
The grid of pipe MN2 connects the feedback voltage formed by resistance R1 and R2 dividing potential drop.
Existing linear voltage regulator passes through feedback voltage and the comparison of reference voltage, regulates the unlatching size of NMOS tube MDRV,
Thus stablizing of output voltage OUT is maintained when exporting curent change.
Although existing linear voltage regulator is capable of the output of burning voltage, but when powering on, DC operation can be there is
Time of the setting up slower problem of point.
Summary of the invention
The technical problem to be solved is to provide a kind of linear voltage regulator, can improve toggle speed.
For solving above-mentioned technical problem, the linear voltage regulator that the present invention provides includes: error amplifier, voltage adjuster
Part and feedback network.
Described error amplifier includes amplifier body, the first tail current source and active load.
Described amplifier body is differential configuration, and the source of two difference channels of described amplifier body all connects described
First tail current source, described active load includes that the first difference active load of mirror image each other and the second difference are active negative
Carrying, described first difference active load and described second difference active load are connected respectively to described amplifier body two
The load end of difference channel.
Described error amplifier also includes that described acceleration starts for accelerating the acceleration start-up circuit that linear voltage regulator starts
The Part I circuit of circuit is the mirror image circuit of described first difference active load, the second of described acceleration start-up circuit
Partial circuit connects described Part I circuit, and the Part III circuit of described acceleration start-up circuit is described Part II
The mirror image circuit of circuit, described Part III circuit provides the second tail current to two difference channels of described amplifier body
Source.
Further improving is that two difference channels of described amplifier body are all cascade amplifying circuit.
Further improving is that first difference channel of described amplifier body includes the first NMOS tube and second
NMOS tube, second difference channel of described amplifier body includes the 3rd NMOS tube and the 4th NMOS tube.
The source electrode of described first NMOS tube and the source electrode of described 3rd NMOS tube are connected together as described amplifier originally
The source of two difference channels of body.
The drain electrode of described first NMOS tube connects the source electrode of described second NMOS tube, the drain electrode of described second NMOS tube
Load end as described first difference channel.
The drain electrode of described 3rd NMOS tube connects the source electrode of described 4th NMOS tube, the drain electrode of described 4th NMOS tube
Load end as described second difference channel and the outfan as described amplifier body.
The grid of described first NMOS tube is as the input of first difference channel and connects reference voltage.
The grid of described 3rd NMOS tube as second difference channel input and connect described feedback network output
Feedback voltage.
The grid of described second NMOS tube connects the grid of described 4th NMOS tube and all connects the first bias voltage.
Further improving is that described first difference active load includes the first PMOS and the second PMOS, described
Second difference active load includes the 3rd PMOS and the 4th PMOS.
The source electrode of described first PMOS and the source electrode of described 3rd PMOS all connect supply voltage.
The drain electrode of described first PMOS connects the source electrode of described second PMOS, the drain electrode of described 3rd PMOS
Connect the source electrode of described 4th PMOS.
The drain electrode of the grid of described first PMOS, the grid of described 3rd PMOS and described second PMOS is all
Connect the drain electrode of described second NMOS tube.
The drain electrode of described 4th PMOS connects the drain electrode of described 4th NMOS tube.
The grid of described second PMOS and the grid of described 4th PMOS all connect the second bias voltage.
Further improving is that described first tail current source includes the 5th NMOS tube, the source electrode of described 5th NMOS tube
Ground connection, the drain electrode of described 5th NMOS tube connects the source electrode of described first NMOS tube, the grid of described 5th NMOS tube
Pole connects the 3rd bias voltage.
Further improving is that the Part I circuit of described acceleration start-up circuit includes the 5th PMOS and the 6th
PMOS, the source electrode of described 5th PMOS connects supply voltage, and the drain electrode of described 5th PMOS connects the described 6th
The source electrode of PMOS, the grid of described 5th PMOS connects the grid of described first PMOS, described 6th PMOS
The grid of pipe connects described second bias voltage, and the drain electrode of described 6th PMOS connects described Part II circuit.
Further improving is that the Part II circuit of described acceleration start-up circuit includes the 6th NMOS tube, described in add
The Part III circuit of speed start-up circuit includes the 7th NMOS tube, described 6th NMOS tube and described 7th NMOS tube
Source ground, the grid of described 6th NMOS tube and the grid of drain electrode and described 7th NMOS tube are all connected to institute
State Part I circuit.
The drain electrode of described 7th NMOS tube is connected to the source of described two difference channels of amplifier body.
Further improving is that described Voltage Cortrol device includes the 8th NMOS tube, the drain electrode of described 8th NMOS tube
Connecting supply voltage, the grid of described 8th NMOS tube connects the drain electrode of described 4th NMOS tube, described 8th NMOS
The source electrode of pipe is as the outfan of described linear voltage regulator.
Further improving and be, described feedback network is by the electricity being connected between outfan and the ground of described linear voltage regulator
Resistance string composition.
The start-up circuit that accelerates of the present invention can be by amplifier that mirror-image fashion is error amplifier in power up
Body improves load current and tail current such that it is able to improve the toggle speed of error amplifier.Meanwhile, the mistake of the present invention
The difference amplifier body of amplifier, Voltage Cortrol device and feedback network, all without change, can make the property of linear voltage regulator
Can be maintained and power consumption will not be increased.
Accompanying drawing explanation
The present invention is further detailed explanation with detailed description of the invention below in conjunction with the accompanying drawings:
Fig. 1 is the circuit diagram of existing linear voltage regulator；
Fig. 2 is the circuit diagram of present pre-ferred embodiments linear voltage regulator；
Fig. 3 is the loop network schematic diagram corresponding to Fig. 2；
Fig. 4 is the startup simulation curve of the embodiment of the present invention and existing linear voltage regulator.
Detailed description of the invention
Embodiment of the present invention linear voltage regulator includes: error amplifier, Voltage Cortrol device and feedback network.
Described error amplifier includes amplifier body, the first tail current source and active load.
Described amplifier body is differential configuration, and the source of two difference channels of described amplifier body all connects described
First tail current source, described active load includes that the first difference active load of mirror image each other and the second difference are active negative
Carrying, described first difference active load and described second difference active load are connected respectively to described amplifier body two
The load end of difference channel.
Described error amplifier also includes that described acceleration starts for accelerating the acceleration start-up circuit that linear voltage regulator starts
The Part I circuit of circuit is the mirror image circuit of described first difference active load, the second of described acceleration start-up circuit
Partial circuit connects described Part I circuit, and the Part III circuit of described acceleration start-up circuit is described Part II
The mirror image circuit of circuit, described Part III circuit provides the second tail current to two difference channels of described amplifier body
Source.
As in figure 2 it is shown, be the circuit diagram of embodiment of the present invention linear voltage regulator；Two difference of described amplifier body
Circuit is all cascade amplifying circuit.
First difference channel of described amplifier body includes the first NMOS tube MN1 and the second NMOS tube MN2, institute
Second difference channel stating amplifier body includes the 3rd NMOS tube MN3 and the 4th NMOS tube MN4.
The source electrode of described first NMOS tube MN1 and the source electrode of described 3rd NMOS tube MN3 are connected together as described
The source of two difference channels of amplifier body.
The drain electrode of described first NMOS tube MN1 connects the source electrode of described second NMOS tube MN2, described 2nd NMOS
The drain electrode of pipe MN2 is as the load end of described first difference channel.
The drain electrode of described 3rd NMOS tube MN3 connects the source electrode of described 4th NMOS tube MN4, described 4th NMOS
The drain electrode load end as described second difference channel of pipe MN4 and the outfan as described amplifier body.
The grid of described first NMOS tube MN1 is as the input of first difference channel and meets reference voltage VREF.
The grid of described 3rd NMOS tube MN3 is as the input of second difference channel and to connect described feedback network defeated
The feedback voltage gone out.
The grid of described second NMOS tube MN2 connects the grid of described 4th NMOS tube MN4 and all connects the first bias voltage
VB1。
Described first difference active load includes the first PMOS MP1 and the second PMOS MP2, described second difference
Active load includes the 3rd PMOS MP3 and the 4th PMOS MP4.
The source electrode of described first PMOS MP1 and the source electrode of described 3rd PMOS MP3 all meet supply voltage VDD.
The drain electrode of described first PMOS MP1 connects the source electrode of described second PMOS MP2, described 3rd PMOS
The drain electrode of pipe MP3 connects the source electrode of described 4th PMOS MP4.
The grid of described first PMOS MP1, the grid of described 3rd PMOS MP3 and described second PMOS
The drain electrode of MP2 all connects the drain electrode of described second NMOS tube MN2.
The drain electrode of described 4th PMOS MP4 connects the drain electrode of described 4th NMOS tube MN4.
The grid of described second PMOS MP2 and the grid of described 4th PMOS MP4 all connect the second bias voltage
VB2。
Described first tail current source includes the 5th NMOS tube MN5, the source ground of described 5th NMOS tube MN5, institute
The drain electrode stating the 5th NMOS tube MN5 connects the source electrode of described first NMOS tube MN1, described 5th NMOS tube MN5
Grid connect the 3rd bias voltage VB3.
The Part I circuit of described acceleration start-up circuit includes the 5th PMOS MPa1 and the 6th PMOS MPa2,
The source electrode of described 5th PMOS MPa1 meets supply voltage VDD, and the drain electrode of described 5th PMOS MPa1 connects institute
Stating the source electrode of the 6th PMOS MPa2, the grid of described 5th PMOS MPa1 connects described first PMOS MP1
Grid, the grid of described 6th PMOS MPa2 connects described second bias voltage VB2, described 6th PMOS
The drain electrode of pipe MPa2 connects described Part II circuit.
The Part II circuit of described acceleration start-up circuit includes the 6th NMOS tube MNa1, described acceleration start-up circuit
Part III circuit includes the 7th NMOS tube MNa2, described 6th NMOS tube MNa1 and described 7th NMOS tube MNa2
Source ground, the grid of described 6th NMOS tube MNa1 and drain electrode and the grid of described 7th NMOS tube MNa2
It is all connected to described Part I circuit.
The drain electrode of described 7th NMOS tube MNa2 is connected to the source of described two difference channels of amplifier body.
Described Voltage Cortrol device includes the 8th NMOS tube MDRV, and the drain electrode of described 8th NMOS tube MDRV connects electricity
Source voltage VDD, the grid of described 8th NMOS tube MDRV connects the drain electrode of described 4th NMOS tube MN4, and described the
The source electrode of eight NMOS tube MDRV is as the outfan of output signal OUT of described linear voltage regulator.
Described feedback network is made up of the resistance string being connected between outfan and the ground of described linear voltage regulator, this resistance
String is in series by resistance R1 and resistance R2.
The acceleration start-up circuit of present pre-ferred embodiments can be error amplifier by mirror-image fashion in power up
Amplifier body improve load current and tail current, understand shown in comparison diagram 1 and Fig. 2, present pre-ferred embodiments
By the mirror image effect of PMOS MPa1 and MPa2, can make PMOS MP1 of present pre-ferred embodiments, MP2,
MP3 and MP4 starts faster compared with the corresponding active load in Fig. 1, and is provided corresponding by NMOS tube MNa2
Tail current.So present pre-ferred embodiments can improve toggle speed.
It addition, illustrate that present pre-ferred embodiments can improve the principle of toggle speed from loop characteristics:
If: PMOS MPa1, MP1 and MP2 equivalently-sized, NMOS tube MNa1 and MNa2's is equivalently-sized；
Feedback factor B=1；The electric current flowing through NMOS tube MN5 is Ib, and the electric current flowing through PMOS MP1 is Ia.
As it is shown on figure 3, be the loop network schematic diagram corresponding to Fig. 2；Loop characteristics is:
During startup, F=1, G=∞, Ia=∞ (saturated)；
When stablizing, F=1/2, G=1, Ia=Ib；
Wherein F is closed loop gain, and G is open-loop gain, and the transformation for mula of the two is: G=F/ (1-F × B).
Understanding, in present pre-ferred embodiments, the value of Ia is infinitely great the most in theory, namely maximum saturation shape
State, so can make electric current during startup maximum, thus start quickly speed.
As shown in Figure 4, being the startup simulation curve of the embodiment of the present invention and existing linear voltage regulator, simulated conditions is:
Under conditions of power supply input 0 to 3.3V, export the stabilization time from 0 to 1.5V: wherein curve 101 is power supply
The change curve of voltage, curve 102 is the change curve of output signal OUT of present pre-ferred embodiments, curve 103
Change curve for output signal OUT of the available circuit shown in Fig. 1, it can be seen that opening of present pre-ferred embodiments
The dynamic time is 20.14 microseconds, and the startup time of available circuit framework is 42.59 microseconds.
Above by specific embodiment, the present invention is described in detail, but these have not constituted the limit to the present invention
System.Without departing from the principles of the present invention, those skilled in the art it may also be made that many deformation and improves, this
Also should be regarded as protection scope of the present invention a bit.
Claims (10)
1. a linear voltage regulator, it is characterised in that including: error amplifier, Voltage Cortrol device and feedback net
Network；
Described error amplifier includes amplifier body, the first tail current source and active load；
Described amplifier body is differential configuration, and the source of two difference channels of described amplifier body all connects described
First tail current source, described active load includes that the first difference active load of mirror image each other and the second difference are active negative
Carrying, described first difference active load and described second difference active load are connected respectively to described amplifier body two
The load end of difference channel；
Described error amplifier also includes that described acceleration starts for accelerating the acceleration start-up circuit that linear voltage regulator starts
The Part I circuit of circuit is the mirror image circuit of described first difference active load, the second of described acceleration start-up circuit
Partial circuit connects described Part I circuit, and the Part III circuit of described acceleration start-up circuit is described Part II
The mirror image circuit of circuit, described Part III circuit provides the second tail current to two difference channels of described amplifier body
Source.
2. linear voltage regulator as claimed in claim 1, it is characterised in that: two difference of described amplifier body
Circuit is all cascade amplifying circuit.
3. linear voltage regulator as claimed in claim 2, it is characterised in that: first difference of described amplifier body
Parallel circuit includes the first NMOS tube and the second NMOS tube, and second difference channel of described amplifier body includes the 3rd
NMOS tube and the 4th NMOS tube；
The source electrode of described first NMOS tube and the source electrode of described 3rd NMOS tube are connected together as described amplifier originally
The source of two difference channels of body；
The drain electrode of described first NMOS tube connects the source electrode of described second NMOS tube, the drain electrode of described second NMOS tube
Load end as described first difference channel；
The drain electrode of described 3rd NMOS tube connects the source electrode of described 4th NMOS tube, the drain electrode of described 4th NMOS tube
Load end as described second difference channel and the outfan as described amplifier body；
The grid of described first NMOS tube is as the input of first difference channel and connects reference voltage；
The grid of described 3rd NMOS tube as second difference channel input and connect described feedback network output
Feedback voltage；
The grid of described second NMOS tube connects the grid of described 4th NMOS tube and all connects the first bias voltage.
4. linear voltage regulator as claimed in claim 3, it is characterised in that: described first difference active load includes
First PMOS and the second PMOS, described second difference active load includes the 3rd PMOS and the 4th PMOS；
The source electrode of described first PMOS and the source electrode of described 3rd PMOS all connect supply voltage；
The drain electrode of described first PMOS connects the source electrode of described second PMOS, the drain electrode of described 3rd PMOS
Connect the source electrode of described 4th PMOS；
The drain electrode of the grid of described first PMOS, the grid of described 3rd PMOS and described second PMOS is all
Connect the drain electrode of described second NMOS tube；
The drain electrode of described 4th PMOS connects the drain electrode of described 4th NMOS tube；
The grid of described second PMOS and the grid of described 4th PMOS all connect the second bias voltage.
5. linear voltage regulator as claimed in claim 3, it is characterised in that: described first tail current source includes the 5th
NMOS tube, the source ground of described 5th NMOS tube, the drain electrode of described 5th NMOS tube connects a described NMOS
The source electrode of pipe, the grid of described 5th NMOS tube connects the 3rd bias voltage.
6. linear voltage regulator as claimed in claim 4, it is characterised in that: first of described acceleration start-up circuit
Parallel circuit includes the 5th PMOS and the 6th PMOS, and the source electrode of described 5th PMOS connects supply voltage, described
The drain electrode of the 5th PMOS connects the source electrode of described 6th PMOS, and the grid of described 5th PMOS connects described
The grid of the first PMOS, the grid of described 6th PMOS connects described second bias voltage, described 6th PMOS
The drain electrode of pipe connects described Part II circuit.
7. the linear voltage regulator as described in claim 4 or 6, it is characterised in that: the of described acceleration start-up circuit
Two partial circuits include that the 6th NMOS tube, the Part III circuit of described acceleration start-up circuit include the 7th NMOS tube,
Described 6th NMOS tube and the source ground of described 7th NMOS tube, the grid of described 6th NMOS tube and drain electrode with
And the grid of described 7th NMOS tube is all connected to described Part I circuit；
The drain electrode of described 7th NMOS tube is connected to the source of described two difference channels of amplifier body.
8. the linear voltage regulator as described in claim 3 or 4, it is characterised in that: described Voltage Cortrol device includes
8th NMOS tube, the drain electrode of described 8th NMOS tube connects supply voltage, and the grid of described 8th NMOS tube connects
The drain electrode of described 4th NMOS tube, the source electrode of described 8th NMOS tube is as the outfan of described linear voltage regulator.
9. the linear voltage regulator as described in claim 3 or 4, it is characterised in that: described feedback network is by being connected on
Resistance string composition between outfan and the ground of described linear voltage regulator.
10. linear voltage regulator as claimed in claim 8, it is characterised in that: described feedback network is described by being connected on
Resistance string composition between outfan and the ground of linear voltage regulator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510507257.0A CN105159382B (en) | 2015-08-18 | 2015-08-18 | Linear voltage regulator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510507257.0A CN105159382B (en) | 2015-08-18 | 2015-08-18 | Linear voltage regulator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105159382A CN105159382A (en) | 2015-12-16 |
| CN105159382B true CN105159382B (en) | 2016-11-23 |
Family
ID=54800265
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510507257.0A Active CN105159382B (en) | 2015-08-18 | 2015-08-18 | Linear voltage regulator |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105159382B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106647914B (en) * | 2017-02-08 | 2017-12-05 | 上海华虹宏力半导体制造有限公司 | Linear voltage regulator |
| WO2021081787A1 (en) * | 2019-10-30 | 2021-05-06 | 华为技术有限公司 | Operational amplifier and startup circuit for operational amplifier |
| CN112099560A (en) * | 2020-09-25 | 2020-12-18 | 上海华虹宏力半导体制造有限公司 | Linear voltage stabilizer |
| CN115328264A (en) * | 2021-05-11 | 2022-11-11 | 西安格易安创集成电路有限公司 | Amplifying circuit, linear voltage stabilizing circuit and electronic device |
| CN113760031B (en) * | 2021-09-13 | 2023-09-01 | 苏州大学 | Low quiescent current NMOS type full-integrated LDO circuit |
| CN116301190B (en) * | 2023-03-31 | 2024-01-05 | 荣湃半导体（上海）有限公司 | Auxiliary circuit and method for improving linearity of differential pair |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7714640B2 (en) * | 2008-02-15 | 2010-05-11 | Micrel, Inc. | No-trim low-dropout (LDO) and switch-mode voltage regulator circuit and technique |
| CN101957627B (en) * | 2010-11-02 | 2012-02-15 | 深圳市富满电子有限公司 | LDO constant voltage control circuit |
| US8624568B2 (en) * | 2011-09-30 | 2014-01-07 | Texas Instruments Incorporated | Low noise voltage regulator and method with fast settling and low-power consumption |
| EP2605102B1 (en) * | 2011-12-12 | 2014-05-14 | Dialog Semiconductor GmbH | A high-speed LDO Driver Circuit using Adaptive Impedance Control |
| CN107741754B (en) * | 2014-01-02 | 2020-06-09 | 意法半导体研发(深圳)有限公司 | LDO regulator with improved load transient performance for internal power supplies |
-
2015
- 2015-08-18 CN CN201510507257.0A patent/CN105159382B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN105159382A (en) | 2015-12-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105159382B (en) | Linear voltage regulator | |
| CN106647914B (en) | Linear voltage regulator | |
| CN102609025B (en) | Dynamic current doubling circuit and linear voltage regulator integrated with the circuit | |
| CN102707757A (en) | Dynamic discharge circuit and LDO integrated with same | |
| CN105940609A (en) | Buffer circuits and methods | |
| CN206379929U (en) | A kind of gain-adaptive error amplifier | |
| CN108073218A (en) | Operation amplifier circuit and band gap reference | |
| CN104216455A (en) | Low-power-consumption reference voltage source circuit for 4G (4th Generation) communications chip | |
| CN104199501A (en) | High-output impedance current source circuit | |
| TWI517557B (en) | Triple cascode power amplifier | |
| CN104881071A (en) | Low-power reference voltage source | |
| US8779853B2 (en) | Amplifier with multiple zero-pole pairs | |
| CN106936304B (en) | A kind of current limit circuit suitable for push-pull output stage LDO | |
| CN106059516B (en) | Track to track operational amplification circuit and ADC converter, dcdc converter and power amplifier | |
| CN107453737A (en) | A kind of low power consumption comparator circuit | |
| CN104460805A (en) | Reference current source with low temperature coefficient and low power supply voltage coefficient | |
| CN104898750B (en) | System and method for generating cascode current source bias voltage | |
| TWI468894B (en) | Low dropout regulator with improved transient response | |
| CN109687832A (en) | Full differential operational amplifier with start-up circuit | |
| CN106292832B (en) | A kind of compact CMOS mu balanced circuits of modified | |
| CN105468081B (en) | Mu balanced circuit with low pressure detection and its method for stabilizing voltage | |
| CN105007052B (en) | A kind of high-gain class-AB operational amplifier circuit | |
| CN108183691A (en) | Folded-cascode op amp | |
| JP2008205561A (en) | Source follower circuit and semiconductor device | |
| US9209761B2 (en) | Combined input stage for transconductance amplifier having gain linearity over increased input voltage range |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |